Semiconductor memory having tegs and testing method thereof

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention measures a semiconductor memory provided with a TEG (Test Element Group) used for measuring various characteristics necessary for the development and design of a semiconductor memory, or for checking a process at the time of production, and measuring electrical characteristics using this TEG. It relates to an inspection method of a semiconductor memory to be used.

【0002】

[Conventional technology]

Many semiconductor devices such as VLSIs that have complicated circuits inside are provided with a simple circuit for process check called a test element group (hereinafter referred to as TEG) on the same wafer.

【0003】

The TEG is used, for example, in a non-defective product check test when a semiconductor chip formed on a semiconductor chip different from the semiconductor device to be a product is formed and a circuit of the product is formed from a wafer.

【0004】

In addition, in order to measure the influence of variations from the design dimensions of devices caused by manufacturing processes such as photolithography and etching, TEGs are formed as close as possible to the same semiconductor chip as the product, and the TEG and the manufacturing method of the product are described. By making them equal, they may be used to monitor the element performance of the product.

【0005】

As an example of this, there is a method of measuring the characteristics of a semiconductor memory in which a large number of memory cells are arranged in a grid pattern using a TEG. In this case, the TEG is also composed of memory cells laid out in a grid pattern. ..

【0006】

When measuring using the TEG, an aluminum terminal called a pad is formed in the TEG in advance, and the probe needle provided on the measuring device side is applied to the pad to measure the electrical characteristics.

【0007】

Hereinafter, the semiconductor memory provided with the conventional TEG will be described with reference to FIGS. 11 and 12.

【0008】

FIG. 11 is a plan view showing the configuration of a TEG used in a conventional semiconductor memory. Further, FIG. 12 is a plan view showing a configuration example of a semiconductor memory provided with a conventional TEG.

【0009】

In FIG. 11, the TEG unit 302 used in the conventional semiconductor memory has the same scale as the product (here, as an example, the number of several K bits or more) in order to accurately evaluate the characteristics of the memory cells of the product. A memory cell array 302 composed of the above memory cells is formed.

【0010】

In addition, of these memory cell array 302, three word lines 305 and three bits for measuring electrical characteristics by applying a voltage to the memory cells for 9 bits each of the central portion 331 and the peripheral portion 332. The wire 304 is connected to each other, and a TEG pad 307 is provided at each end of the word wire 305 and the bit wire 304 to interface with the measuring device.

【0011】

Here, the three bit lines 304 (BL0 to BL2) connected to the 9-bit memory cells in the central portion 331 are connected to the drain regions of the transistors of each memory cell, and the three word lines 305 ( WL0 to WL2) are each connected to the gate electrode of the transistor.

【0012】

On the other hand, three bit lines 304 (BL3 to BL5) and three word lines 305 (WL3 to WL5) are also used as transistors in the 9-bit memory cells provided in the peripheral portion 332, as in the central portion 331. It is connected.

【0013】

Further, a source wiring 309 is connected to the source region of the transistor of each memory cell, and a TEG pad 307 is formed at the end thereof.

【0014】

Further, a wiring 310 for setting the substrate potential to a fixed potential is formed on the outside of the memory cell array 302, and a substrate potential fixing pad 311 is formed at the end thereof. Here, the wiring 310 is connected to a cell plate electrode (not shown) connected to a capacitor (not shown) connected to the source region of each transistor.

【0015】

As shown in FIG. 12, the TEG unit 302 is arranged as close as possible to the semiconductor memory circuit 402, which is a product in the semiconductor chip 401, and the variation in element dimensions caused by processes such as photolithography and etching becomes equivalent to that of the product. It is manufactured by the same manufacturing process as the product.

【0016】

By doing so, the characteristics of the memory cell formed in the TEG section 302 reflect the characteristics of the memory cell of the product, and by measuring the characteristics of the TEG section 302, the characteristics of the memory cell of the product can be measured. Obtainable.

【0017】

Further, if the electrical characteristics of the memory cells of the central portion 331 and the peripheral portion 332 of the memory cell array 302 of the TEG unit 302 are measured, the difference in manufacturing process conditions (for example, processing shape, processing dimension) due to the difference in position. It is also possible to measure the difference in electrical characteristics resulting from the above.

【0018】

[Problems to be Solved by the Invention]

However, in the conventional semiconductor memory equipped with the TEG as described above, in order to reflect the characteristics of the memory cell of the TEG part in the characteristics of the memory cell of the product, a memory cell of the same scale as the product is formed in the TEG part and the same. It had to be placed on a semiconductor chip or adjacent to the product on the same wafer.

【0019】

In such a case, since a memory cell array similar to that of the product is formed in the TEG section, the required chip area is almost doubled, and the number of chips in the product that can be taken out from one wafer is half that in the case where the TEG section is not mounted. It will be about. Therefore, there is a problem that the manufacturing cost per chip is doubled.

【0020】

On the other hand, as a method of suppressing an increase in the chip area and not reducing the number of product chips that can be taken out from one wafer, a method of reducing the scale of the memory cell array in the TEG section and arranging it at the end of the semiconductor chip as shown in FIG. 13 is used. is there.

【0021】

However, since the number of memory cells in the TEG section is reduced in this method, for example, when the product is a megabit-class memory cell array, the processing formation conditions of the product and the TEG section are different, so that the characteristics of the memory cells in the TEG section are different. Does not reflect the characteristics of the product's memory cells.

【0022】

This is because even if the TEG part is placed on the same semiconductor chip as the product, there is a difference in the etching rate such as reactive ion etching (RIE) due to the difference in the density of the element pattern (generally, this phenomenon is caused by the micro-loading effect). This is because there is a difference in electrical characteristics.

【0023】

FIG. 14 shows the relationship between the etching rate and the scale of the memory cell array.

【0024】

The graph shown in FIG. 14 shows the etching characteristics when a gate electrode is formed by a composite film of tungsten silicide (WSi) and polycrystalline silicon and the gate electrode is formed. For example, a power of 150 W and a pressure of 250 (mTorr) are shown. ), Reactive ion etching (RIE) characteristics are shown when helium (He) gas is used as the carrier gas and sulfur hexafluoride (SF6) gas and hydrogen bromide (HBr) gas are used as the etching gas. There is.

【0025】

As shown in FIG. 14, the etching rate tends to decrease as the scale of the memory cell array increases. For example, when the scale of the memory cell of the product is 64 Mbits, the memory cell of the TEG section must be megabits or more. The difference in etching rate from that of the product becomes large, and the difference in processing shape and processing size cannot be ignored.

【0026】

The present invention has been made to solve the problems of the conventional technology as described above, and accurately reflects various characteristics of the memory cell of the semiconductor memory to be a product without increasing the chip area of the semiconductor memory. The purpose is to provide a semiconductor memory equipped with a TEG.

【0027】

Further, the present invention provides a method for inspecting a semiconductor memory for measuring various characteristics of a memory cell by using the TEG for the semiconductor memory.

【0028】

[Means for solving problems]

In order to achieve the above object, the semiconductor memory provided with the TEG of the present invention is a semiconductor memory provided with a TEG whose predetermined electrical characteristics are measured in place of the memory cell array to be a product in order to evaluate the performance of the semiconductor memory. The TEG is simultaneously formed in the region where the memory cell array to be the product is formed by the same manufacturing method as the memory cell array to be the product, and is an interface means for independently measuring the predetermined electrical characteristics. It is characterized by having.

【0029】

Further, the semiconductor memory inspection method is a semiconductor memory inspection method for evaluating the performance of a semiconductor memory using a TEG in which a predetermined electrical characteristic is measured instead of a memory cell array as a product. , An interface means for independently forming the predetermined electrical characteristics of the TEG by simultaneously forming the memory cell array to be the product in the region where the memory cell array to be the product is formed by the same manufacturing method as the memory cell array to be the product. It is characterized in that the predetermined electrical characteristics of the TEG are measured via the above.

【0030】

Since the semiconductor memory provided with the TEG configured as described above is formed by the same manufacturing method in the same region as the memory cell in which the TEG is a product, it is possible to obtain a TEG having the same characteristics as the product.

【0031】

Therefore, since the TEG can be configured by a small number of memory cells, the occupied area of the TEG can be reduced, and the increase in the chip area due to the provision of the TEG can be prevented.

【0032】

BEST MODE FOR CARRYING OUT THE INVENTION

Next, the present invention will be described with reference to the drawings.

【0033】

The TEG for semiconductor memory shown in each of the following examples is applied to 64 Mbit DRAM (Dynamic Random Access Memory).

【0034】

The TEG mounted on the DRAM needs to be able to measure the following characteristics.

【0035】

(1) Sub-threshold characteristics of memory cell transistors (2) Drain current-drain voltage characteristics of the transistor of the memory cell (3) Isolation characteristics between memory cells (4) Capacitor capacitance characteristics (CV characteristics) for data retention and leakage current characteristics of the capacitance insulating film The TEG of the present invention is configured so that the characteristics of (1) to (4) above can be measured, and further accurately reflects the electrical characteristics of the memory cell of the product.

【0036】

(First Example) First, as a first embodiment of the semiconductor memory provided with the TEG of the present invention, a case where the transistor characteristics of the memory cell are measured by the TEG will be described.

【0037】

FIG. 1 is a plan view showing the configuration of the first embodiment of the semiconductor memory provided with the TEG of the present invention.

【0038】

In FIG. 1, four circuit blocks (memory cell array) each composed of a plurality of memory cells are formed on the semiconductor chip 1 to be a product, and each desired area in the memory cell array 2 is formed as needed. The TEG portion 3 is formed. The TEG section 3 is formed in at least one memory cell array 2 depending on the measurement content.

【0039】

Of the four memory cell array 2, in the memory cell array 2 shown in the lower left of FIG. 1 (when 64 Mbit DRAM is composed of four memory cell array 2, one memory cell array 2 is composed of 16 Mbit memory cells). A TEG section 3 is formed in the central portion thereof, and the TEG section 3 is composed of a memory cell for one bit.

【0040】

One bit wire 4 is connected to the drain region of the transistor of the memory cell, and a TEG drain electrode pad 6 is formed at the end thereof. Further, one word wire 5 is connected to the gate electrode, and a TEG gate electrode pad 8 is formed at the end thereof.

【0041】

On the other hand, in the memory cell array 2 shown in the lower right of FIG. 1, a TEG section 3 is formed in a peripheral portion thereof, and is composed of a memory cell for one bit as in the central portion. Further, in the transistor of the memory cell, one bit wire 4 is connected to the drain region as in the case of the TEG portion 3 formed in the central portion, and the drain electrode pad 6 for TEG is formed at the end portion thereof. Further, one word wire 5 is connected to the gate electrode, and a TEG gate electrode pad 8 is formed at the end thereof.

【0042】

Further, a source wiring 9 is connected to the source region of the transistor, and a TEG source electrode pad 7 is formed at the end thereof.

【0043】

A wiring 10 for setting the substrate potential of the semiconductor chip 1 to a fixed potential is formed in the outer region of the memory cell array 2, and a substrate potential fixing pad 11 is formed at the end thereof.

【0044】

Here, since the TEG unit 3 described above is incorporated in the area of the memory cell array 2 of the product, it is simultaneously manufactured by the same manufacturing process as the memory cell array 2 of the product.

【0045】

Therefore, for example, the difference in etching rate (micro-loading effect of reactive ion etching) caused by the difference in pattern density when etching the gate electrode is eliminated, and the memory cell to be the product and the memory cell of the TEG section 3 are eliminated. There is no difference in the processing dimensions of the gate electrode with.

【0046】

Therefore, since the memory cell of the TEG section 3 has the same characteristics as the memory cell of the product, even if the TEG section 3 is configured with only one bit of the memory cell, the transistor characteristic of the memory cell of the product is accurately reflected. It will be the one that was done.

【0047】

Therefore, it is possible to provide the TEG unit 3 capable of measuring the transistor characteristics of the memory cell without increasing the chip area of the semiconductor memory.

【0048】

Next, the configuration of the TEG unit 3 of this embodiment will be described in detail with reference to FIGS. 2 to 4.

【0049】

Note that FIGS. 2 to 4 describe the case where the TEG section 3 is located in the central portion of the memory cell array 2, but the configuration is the same when the TEG section 3 is located in the peripheral portion of the memory cell array 2. , The description is omitted.

【0050】

FIG. 2 is a circuit diagram showing an equivalent circuit of the TEG section shown in FIG. Further, FIG. 3 is an enlarged plan view showing the structure of the TEG portion shown in FIG. 1, and FIG. 4 is a cross-sectional view showing the structure of the TEG portion shown in FIG. 3 as viewed from the side surface.

【0051】

In FIG. 2, the TEG unit 3 is composed of a transistor characteristic evaluation cell 12 for measuring a transistor characteristic of a memory cell and a non-operating cell 13 formed in the same row.

【0052】

A word wire 5 is connected to the gate G of the transistor of the transistor characteristic evaluation cell 12, and a TEG gate electrode pad 8 is formed at the end thereof. A bit wire 4 is connected to the drain D of the transistor, and a TEG drain electrode pad 6 is formed at the end thereof. Further, a source wiring 9 having a TEG source electrode pad 7 formed at its end and one end of a capacitor 14 for holding data (holding a voltage) are connected to the source S of the transistor. The other end of the capacitor 14 is connected in common with each transistor in the memory cell array 2 by a cell plate electrode (not shown), and the cell plate electrode is connected to the TEG upper electrode pad 29 and has the same voltage as the TEG source electrode 7. Is applied.

【0053】

In FIG. 3, the transistor characteristic evaluation cell 12 is composed of an N-type semiconductor and has a source region 15 which is a source S of the transistor, an N-type semiconduct and a drain region 16 which is a drain D of the transistor, and a gate G of the transistor. It is composed of a gate electrode 17, a bit wire contact 18 to which the bit wire 4 and the drain region 16 are connected, and a node contact 19 to which the source wiring 9 and the source region 15 are connected.

【0054】

A bit wire 4 is connected to the drain electrode pad 6 for TEG, and a word wire 5 which is the same as the memory cell to be a product is connected to the gate electrode pad 8 for TEG.

【0055】

Further, the source wiring 9 is connected to the source region 15 via the node contact 19, and the source electrode pad 7 for TEG is formed in the source wiring 9.

【0056】

Note that the memory cell (non-operating cell 13) on the same row as the transistor characteristic evaluation cell 12 is a memory cell because the drain and source of the transistor are not connected to the bit line 4 and the source wiring 9, respectively. Never used.

【0057】

In FIG. 4, a gate electrode 17 and a word line 5 (not shown) connected to the gate electrode 17 are formed on the silicon substrate 20 made of a P-type semiconductor via a field oxide film 21 or a gate oxide film 22, and the silicon substrate 20 is formed. A source region 15 and a drain region 16 are formed in the vicinity of the upper surface of the silicon wafer with the gate electrode 17 interposed therebetween.

【0058】

Further, a first interlayer insulating film 23 is formed on the silicon substrate 20, and a bit wire 4 is formed on the first interlayer insulating film 23. An opening reaching the drain region 16 is formed in the first interlayer insulating film 23, and the drain region 16 formed near the upper surface of the silicon substrate 20 and the bit wire 4 are connected by the bit wire contact 18 by the opening. Will be done.

【0059】

A second interlayer insulating film 24 is formed on the bit wire 4, and a source wiring 9 is formed on the second interlayer insulating film 24. An opening reaching the source region 15 was formed in the second interlayer insulating film 24, and the opening was formed near the upper surface of the source wiring 9 and the silicon substrate 20 formed on the second interlayer insulating film 24. The source area 15 is connected with the node contact 19.

【0060】

A cell plate electrode 26 is formed on the source wiring 9 via the capacitive insulating film 25, and the capacitor 14 is formed by the source wiring 9, the capacitive insulating film 25, and the cell plate electrode 26.

【0061】

Next, the procedure for measuring the transistor characteristics of the memory cell using the TEG unit 3 as described above will be described by taking the case of measuring the sub-threshold characteristics of the transistor as an example.

【0062】

First, 0 V is applied to the TEG source electrode pad 7 shown in FIG. 1, and a positive voltage in the range of 0.1 to 5 V, for example, a voltage of about 3 V is applied to the TEG drain electrode pad 6.

【0063】

In this state, a voltage of, for example, -1V to + 3V is applied to the TEG gate electrode pad 8 in 0.01V steps, and the current flowing from the TEG drain electrode pad 6 at this time is measured with an ammeter.

【0064】

This makes it possible to measure the sub-threshold characteristics of the transistor.

【0065】

(Second Example) Next, as a second example of the semiconductor memory provided with the TEG of the present invention, a case where the capacitor characteristics of the memory cell are evaluated using the TEG will be described.

【0066】

FIG. 5 is a plan view showing the configuration of a second embodiment of the semiconductor memory provided with the TEG of the present invention.

【0067】

In FIG. 5, four circuit blocks (memory cell array) each composed of a plurality of memory cells are formed on the semiconductor chip 101 to be a product, and each desired region in the memory cell array 102 is formed as needed. The TEG portion 103 is formed. The TEG section 103 is formed in at least one memory cell array 102 depending on the measurement content.

【0068】

Of the four memory cell array 102, the TEG section 103 is formed in the central portion of the memory cell array 102 shown in the lower left of FIG. 5, and the TEG section 103 contains one vertical row (several tens of K bits) shown in FIG. Capacitors 114 (not shown) are formed in each of the memory cell areas (not shown).

【0069】

One end of the capacitor 114 is connected to the lower electrode wiring 127, and the lower electrode pad 128 for TEG is formed at the end thereof.

【0070】

Further, the other end of the capacitor 114 is commonly connected by a cell plate electrode described later, and the cell plate electrode is connected to the upper electrode pad 129 for TEG.

【0071】

On the other hand, in the memory cell array 102 shown in the lower right of FIG. 5, a TEG section 103 is formed in the peripheral portion thereof, and a capacitor 114 is formed in the area of the memory cell for one vertical row shown in FIG. 5 in the TEG section 103. Has been done. Similar to the TEG portion 103 formed in the central portion, one end of each of these capacitors 114 is connected to the lower electrode wiring 127, and the other ends are connected in common with the cell plate electrode described later.

【0072】

Here, in order to measure the capacitor characteristics (CV characteristics) with high accuracy, the total capacity of the capacitor 114 needs to be about several tens of pF. Since the capacitance value of the capacitor 114 per memory cell is 20fF to 30fF, in this embodiment, in order to obtain the capacitance value required for the above measurement, several K-bit capacitors (one vertical row shown in FIG. 5) are used. 114 is formed in the TEG portion 103.

【0073】

Since the TEG unit 103 described above is incorporated in the area of the memory cell array 102 of the product, it is simultaneously manufactured by the same manufacturing process as the memory cell array 102 of the product.

【0074】

Therefore, as in the first embodiment, since the capacitor 114 of the TEG unit 103 is formed with the same characteristics as the capacitor of the memory cell of the product, it accurately reflects the capacitor characteristics of the memory cell of the product.

【0075】

Therefore, the TEG unit 103 capable of measuring the capacitor characteristics of the memory cell without increasing the chip area of the semiconductor memory can be provided.

【0076】

Next, the configuration of the TEG unit 103 of this embodiment will be described in detail with reference to FIGS. 6 to 8.

【0077】

Although FIGS. 6 to 8 are described in the case where the TEG section 103 is located in the central portion of the memory cell array 102, the configuration is the same when the TEG section 103 is formed in the peripheral portion of the memory cell array 102. , The description is omitted.

【0078】

FIG. 6 is a circuit diagram showing an equivalent circuit of the TEG section shown in FIG. Further, FIG. 7 is an enlarged plan view showing the structure of the TEG portion shown in FIG. 5, and FIG. 8 is a cross-sectional view showing the structure seen from the side surface of the TEG portion shown in FIG.

【0079】

In FIG. 6, the TEG unit 103 is composed of the capacitor evaluation cell 112 for measuring the capacitor characteristics of the memory cell, and the capacitor evaluation cell 112 is composed of the number of capacitors 114 corresponding to the memory cells for 8 bits. There is.

【0080】

One end of the capacitor 114 (capacitive storage electrode described later) is connected to the lower electrode wiring 127, and a lower electrode pad 128 for TEG is formed at the end thereof. Further, the other end of the capacitor 114 is commonly connected to the cell plate electrode described later, and the cell plate electrode is connected to the upper electrode pad 129 for TEG.

【0081】

In FIG. 7, the capacitor evaluation cell 112 has a capacitance storage electrode 130 which is one electrode of the capacitor 114, a cell plate electrode 126 which is the other electrode of the capacitor 114, a lower electrode wiring 127, and a lower electrode wiring 127 and capacitance storage. It is composed of node contacts 119 connecting the electrodes 130.

【0082】

In FIG. 8, a lower electrode wiring 127 is formed on a silicon substrate 120 made of a P-type semiconductor via a field oxide film 121, and a first interlayer insulating film 123 is formed on the lower electrode wiring 127. .. A bit wire 104 used in a product memory cell is formed on the first interlayer insulating film 123, and a second interlayer insulating film 124 is formed on the bit wire 104. A capacitance storage electrode 130 serving as one electrode of the capacitor 114 is formed on the second interlayer insulating film 124. An opening reaching the lower electrode wiring 127 is formed in the second interlayer insulating film 124, and the capacitance storage electrode 130 and the lower electrode wiring 127 are connected by the node contact 119 by this opening.

【0083】

Further, a cell plate electrode 126 which is the other electrode of the capacitor 114 is formed on the capacitance storage electrode 130 via the capacitance insulating film 125, and the capacitor is formed by the capacitance storage electrode 130, the capacitance insulating film 25, and the cell plate electrode 26. 114 is composed. The cell plate electrode 126 is connected to the TEG upper electrode pad 129 shown in FIG.

【0084】

Next, the procedure for measuring the capacitor characteristics of the memory cell using the TEG unit 103 of this embodiment will be described by taking the case of measuring the leakage current characteristics of the capacitive insulating film as an example.

【0085】

First, 0 V is applied to the lower electrode pad 128 for TEG shown in FIG.

【0086】

In this state, a positive or negative voltage in the range of 0V to 3V is applied to the TEG upper electrode pad 129 in steps of 0.1V, and the current flowing from the TEG upper electrode pad 129 at this time is measured with an ammeter.

【0087】

This makes it possible to measure the leakage current characteristic of the capacitive insulating film of the capacitor.

【0088】

(Third Example) Next, as a third embodiment of the semiconductor memory provided with the TEG of the present invention, a case where the isolation characteristics between memory cells are evaluated using the TEG will be described.

【0089】

FIG. 9 is a plan view showing the configuration of a third embodiment of the semiconductor memory provided with the TEG of the present invention.

【0090】

In FIG. 9, four circuit blocks (memory cell array) each composed of a plurality of memory cells are formed on the semiconductor chip 201 to be a product, and each desired region in the memory cell array 202 is formed as needed. The TEG portion 203 is formed. The TEG unit 203 is formed in at least one memory cell array 202 depending on the measurement content.

【0091】

Of the four memory cell array 202, the TEG section 203 is formed in the central portion of the memory cell array 202 shown in the lower left of FIG. 9, and the TEG section 203 is composed of memory cells for 2 bits. A bit wire 204 is connected to each drain region of the transistor of the memory cell, and a TEG drain electrode pad 206 is formed at the end thereof. Further, a word wire 205 is connected to each of the gate electrodes, and a TEG gate electrode pad 208 is formed at the end thereof.

【0092】

On the other hand, in the memory cell array 202 shown in the lower right of FIG. 1, a TEG section 203 is formed in the peripheral portion thereof, and is composed of memory cells for 2 bits. Similar to the TEG portion 203 formed in the central portion, the bit wire 204 is connected to the drain region and the word wire 5 is connected to the gate electrode of each of the transistors of these memory cells.

【0093】

Further, a source wiring 209 is connected to each source region of the transistor, and a TEG source electrode pad 207 is formed at the end thereof.

【0094】

A wiring 210 for setting the substrate potential of the semiconductor chip 201 to a fixed potential is formed in the outer region of the memory cell array 202, and a substrate potential fixing pad 211 is formed at the end thereof.

【0095】

Here, the above-mentioned TEG unit 203 is incorporated in the area of the memory cell array 202 of the product, and is simultaneously manufactured by the same manufacturing process as the memory cell array 202 of the product.

【0096】

Therefore, since the memory cell of the TEG section 203 is formed with the same characteristics as the memory cell of the product as in the first embodiment, the isolation characteristic between the memory cells of the TEG section 203 is the isolation between the memory cells of the product. It accurately reflects the characteristics.

【0097】

Therefore, it is possible to provide a TEG unit capable of measuring the isolation characteristics without increasing the size of the chip area of the semiconductor memory.

【0098】

Next, the configuration of the TEG unit 203 of this embodiment will be described in detail with reference to FIG.

【0099】

Note that FIG. 10 describes the case where the TEG portion is located in the central portion of the memory cell array, but the description is omitted because the configuration is the same when the TEG portion is located in the peripheral portion of the memory cell array. Further, since the cross-sectional view of the memory cell array is the same as that shown in FIG. 4 shown in the first embodiment, the description thereof will be omitted.

【0100】

FIG. 10 is an enlarged plan view showing the structure of the TEG portion shown in FIG.

【0101】

In FIG. 10, the element separation characteristic evaluation cell 212 composed of 2-bit memory cells has an N-type semiconducting source region 215 and an N-type semiconducting transistor drain. It is composed of a drain region 216, a gate electrode 217 that serves as a gate for a transistor, a bit wire contact 218 that connects the bit wire 204 and the drain region 216, and a node contact 219 that connects the source wiring 209 and the source region 215.

【0102】

A bit wire 204 is connected to the drain electrode pad 206 for TEG, and a word wire 214 which is the same as the memory cell to be a product is connected to the gate electrode pad 219 for TEG.

【0103】

Further, in the source region 215 of the transistor of the element separation characteristic evaluation cell 212, a source wiring 209 in which a TEG source electrode pad 207 is formed at the end thereof, and a capacitor for holding data (holding voltage) (holding voltage). One end (not shown) is connected. The other end of the capacitor is commonly connected to each transistor in the memory cell array 202 by a cell plate electrode (not shown), and the cell plate electrode is connected to the TEG upper electrode pad 229 and has the same voltage as the TEG source electrode pad 207. Is applied.

【0104】

Next, a procedure for measuring the isolation characteristics between memory cells using the TEG unit 203 described above will be described.

【0105】

First, for example, a voltage of 3V is applied to each of the two TEG gate electrode pads 208, and 0V is applied to each of the TEG drain electrode pad 206 and the TEG source electrode pad 207 connected to one of the memory cells.

【0106】

In such a state, a positive voltage is applied to the TEG drain electrode pad 206 and the TEG source electrode pad 207 connected to the other memory cell in the range of 0 to 15 V in 0.1 V steps, respectively, and at this time, the TEG drain is applied. By measuring the current flowing from the electrode pad 206 with an ammeter, the element separation characteristics between the memory cells can be measured.

【0107】

In this case, the separation characteristic between the bit line contact 218 of one memory cell and the node contact 219 of the other memory cell and the separation characteristic between the two node contacts 219 can be measured at the same time.

【0108】

As another measurement method, 0 V is applied to each of the two TEG gate electrode pads 208, and 0 V is applied to the TEG source electrode pad 207 connected to one of the memory cells.

【0109】

In this state, a positive voltage is applied to the TEG source electrode pad 207 connected to the other memory cell in the range of 0 to 15V in 0.1V steps, and the current flowing from the TEG drain electrode pad 206 at this time is measured by an ammeter. By measuring, the element separation characteristics between the memory cells can be measured.

【0110】

In this case, only the isolation characteristics of the leak path between the two node contacts 219 shown in FIG. 10 can be measured, and the data excluding the values of the other leak paths (between bit contact and node contact) can be obtained. it can.

【0111】

[Effect of the invention]

Since the present invention is configured as described above, the effects described below are obtained.

【0112】

By simultaneously forming the TEG in the area where the product memory array is formed by the same manufacturing method as the product memory array and having an interface means for independently measuring a predetermined electrical characteristic, the product and the product It is possible to obtain a TEG having the same characteristics as the memory cell.

【0113】

Therefore, the TEG can be configured with the minimum required memory cell array, and the increase in chip area, which has been a problem in the conventional semiconductor memory TEG, can be suppressed.

[Simple explanation of drawings]

[Figure 1]

It is a top view which shows the structure of 1st Example of the semiconductor memory provided with TEG of this invention.

[Figure 2]

It is a circuit diagram which shows the equivalent circuit of the TEG part shown in FIG.

[Fig. 3]

It is an enlarged plan view which shows the structure of the TEG part shown in FIG.

[Fig. 4]

It is sectional drawing which shows the structure seen from the side surface of the TEG part shown in FIG.

[Fig. 5]

It is a top view which shows the structure of the 2nd Example of the semiconductor memory provided with the TEG of this invention.

[Fig. 6]

It is a circuit diagram which shows the equivalent circuit of the TEG part shown in FIG.

[Fig. 7]

It is an enlarged plan view which shows the structure of the TEG part shown in FIG.

[Fig. 8]

It is sectional drawing which shows the structure seen from the side surface of the TEG part shown in FIG.

[Fig. 9]

It is a top view which shows the structure of the 3rd Example of the semiconductor memory provided with the TEG of this invention.

[Fig. 10]

It is an enlarged plan view which shows the structure of the TEG part shown in FIG.

[Fig. 11]

It is a top view which shows the structure of TEG used for the conventional semiconductor memory.

[Fig. 12]

It is a top view which shows the structural example of the semiconductor memory which provided with the conventional TEG.

[Fig. 13]

It is a top view which shows the other configuration example of the semiconductor memory which provided with the conventional TEG.

[Fig. 14]

It is a graph which shows the relationship of the etching rate with respect to the scale of a memory cell array.

[Explanation of symbols]

1, 101, 201 semiconductor chips 2, 102, 202 memory cell array 3, 103, 203 TEG section 4, 104, 204 bit lines 5,205 word line Drain electrode pad for 6,206 TEG Source electrode pad for 7,207 TEG Gate electrode pad for 8,208 TEG 9,209 Source wiring 10, 210 wiring 11, 211 Substrate potential fixing pad 12 Transistor characterization cell 13 Non-working cell 14,114 capacitors 15,215 Source area 16,216 drain area 17,217 Gate electrode 18,218 Bit wire contacts 19, 119, 219 node contacts 20, 120 silicon substrate 21,121 Field oxide film 22 Gate oxide film 23, 123 First interlayer insulating film 24, 124 Second interlayer insulating film 25, 125 Capacitive insulating film 26, 126 Cell plate electrode Upper electrode pad for 29, 129, 229 TEG 112 Capacitor evaluation cell 127 Lower electrode wiring 128 Lower electrode pad for TEG 130 Capacity storage electrode 212 Element separation characteristic evaluation cell