Frequency offset correction device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a frequency offset correction device that is used as a receiver of a base station of a mobile communication system using a code division multiple access (CDMA) and corrects a frequency offset generated in a communication line or the like.

【0002】

[Conventional technology]

Conventionally, in this type of receiver, a frequency offset generated in a transmission line due to the Doppler effect and a frequency offset in which the frequency error of the oscillator between the receiver and the transmitting device cannot be removed by the demodulator are generated. In this case, a detection error occurs and a transmission error of transmission information occurs. Therefore, a correction process for removing the frequency offset is performed.

【0003】

FIG. 7 is a block diagram showing a configuration of a conventional frequency offset correction device. In FIG. 7, this example is a receiver of a CDMA base station device provided with a plurality of correlators for multi-pass countermeasures, and signals from the same transmitting side are received by a plurality of antennas (not shown), and the combined reception signal thereof. The received radio frequency (RF) signal such as is input to the frequency conversion circuit 90, mixed with the local oscillator signal from the local oscillator 91, and the base band (BB) signal is input to the correlation circuit 93a, 93b ... 93n. .. In the correlation circuits 93a to 93n, despreading is performed with a diffusion code shifted in time, and the correlation value signal is output to the detection circuits 94a, 94b ... 94n.

【0004】

The respective detection signals from the detection circuits 94a to 94n are added and combined by the additive synthesis circuit 95 and output. This output signal (additional composite signal) is input to the frequency offset detection circuit 92, where a known pilot signal portion of the output signal is compared with a theoretical value to detect the frequency offset. The voltage of this frequency offset value is input to a local oscillator 91 such as a voltage controlled oscillator (VCO), and the oscillation frequency is varied to correct (cancel) the frequency offset.

【0005】

FIG. 8 is a block diagram showing another configuration example of the conventional frequency offset correction device. In FIG. 8, this example is a receiver of a CDMA base station apparatus that divides a received high-frequency signal into a plurality of channels and uses the signals from the same transmitting side with a plurality of antennas (not shown) as in the configuration of FIG. Is received, and a received high frequency signal such as the combined received signal is input to the frequency conversion circuit 100. Here, the baseband (BB) signal obtained by mixing with the local oscillation signal from the local oscillator 101 is divided into a plurality of channels and input to the reception demodulation processing units A ... N that transmit the output signal. ..

【0006】

The reception / demodulation processing units A ... N of each channel have the same configuration and perform the same operation. In the reception demodulation processing units A ... N, the baseband signals are input to the correlation circuits 104a, 104b ... 104n through the frequency offset correction circuit 103, respectively. In the correlation circuits 104a to 104n, the baseband signal is despread with a diffusion code shifted in time, and the correlation value signal is output to the detection circuits 105a, 105b ... 105n.

【0007】

The respective detection signals from the detection circuits 105a to 105n are added by the addition synthesis circuit 106, combined, and output. This output signal (additional composite signal) is input to the frequency offset detection circuit 102, where a known pilot signal portion of the output signal is compared with a theoretical value to detect the frequency offset. This frequency offset value is input to the frequency offset correction circuit 103 to correct (cancel) the frequency offset of the baseband signal.

【0008】

As a proposal for performing such frequency offset correction, the communication path frequency offset correction device described in Japanese Patent Application Laid-Open No. 62-219832 is known. In this publication example, noise in a decoding signal in confidential communication, that is, noise (level) whose level increases when the frequency offset becomes large is detected, and control is performed so as to reduce this noise.

【0009】

[Problems to be Solved by the Invention]

However, in the frequency offset correction device of the above-mentioned conventional example, in the example shown in FIG. 7, the received high frequency signal cannot be divided into a plurality of channels and used. The same applies to the example of JP-A-62-219832. Further, in the example shown in FIG. 8, the received high-frequency signal can be divided into a plurality of channels and used, but the baseband signal in the frequency offset correction circuit 103 is high-speed, and when sampling and correcting the frequency offset. The amount of calculation of is increased, and the processing time is increased. For example, when the chip rate is 128 chips / symbol, even if the symbol rate is 60 k / sec, it is necessary to calculate 7.68 M chips per second, and there is a drawback that data transmission at higher speed cannot be performed.

【0010】

The present invention solves such a drawback in the conventional technique, and reduces the amount of calculation for frequency offset correction, reduces the processing time, and enables high-speed data transmission and the like. The purpose is to provide a correction device.

【0011】

[Means for solving problems]

In order to achieve the above object, the frequency offset correction device according to claim 1 has a receiving means for outputting a baseband signal obtained by demodulating a received high frequency signal and a receiving means for converting the baseband signal from the receiving means into a digital signal. A / D conversion means, a plurality of correlation processing means for obtaining a correlation signal in which the digital baseband signal from the A / D conversion means is back-spread by a diffusion signal shifted in time, and each correlation signal from the correlation processing means. Frequency offset detection that detects the frequency offset value by using a plurality of detection means for detecting, an addition synthesis means that adds and synthesizes each detection signal from the detection means, and a known part of the signal from the addition synthesis means. The configuration includes means and frequency offset correction means for removing and correcting the frequency offset value detected by the frequency offset detecting means from the signal from the addition / synthesizing means.

【0012】

The frequency offset correction device according to claim 2 has, as the detection means, a delay circuit that delays the correlation value signal from the correlation processing means by one symbol, and one symbol from the correlation value signal from the correlation processing means and the delay circuit. It is configured to perform delay detection by providing a multiplication unit that outputs a detection signal multiplied by a correlation value signal with a minute delay.

【0013】

The frequency offset correction device according to claim 3 has, as the detection means, a sequential follow-up synchronous detection processing circuit and a detection in which the estimated fading vector is delayed by one symbol, and after complex conjugate conversion, it is multiplied by a correlation value signal. It is configured to perform sequential follow-up synchronous detection with a multiplication unit that outputs a signal.

【0014】

The frequency offset correction device according to claim 4, as the frequency offset detecting means, is a complex conjugate of a known signal theoretical value generating unit that generates a theoretical value of a known signal and a known signal theoretical value from the known signal theoretical value generating unit. The first complex conjugate converter that outputs the converted signal and the first complex conjugate converter that detects the phase shift between the known portion of the signal that is additively synthesized by the additive synthesis means and the signal that has been complex conjugate converted by the first complex conjugate converter. The multiplication part of, the n symbol delay part that delays the phase shift signal from the first multiplication part by n symbols, and the second complex conjugate conversion part that performs the complex conjugate conversion of the phase shift signal delayed by n symbols by the n symbol delay part. And the second multiplication part that multiplies the phase shift signal from the first multiplication part and the complex conjugate conversion signal from the second complex conjugate conversion part, and subtract n from the number of symbols from the second multiplication part. An integrating unit that integrates the rotation vector for the number of symbols, a vector / angle conversion unit that converts the vector integrated by the integrating unit into an angle, and a rotation angle between n symbols divided by the number of symbols to rotate per symbol. A 1 / n multiplication unit for finding the angle, an angle / vector conversion unit that converts the rotation angle per symbol into a frequency offset vector with norm 1, and a hold that holds the frequency offset vector until the next frequency offset vector is obtained. It is a configuration including a part.

【0015】

The frequency offset correction device according to claim 5 has, as the frequency offset detecting means, a first multiplication unit that multiplies the frequency offset correction vector and the frequency offset vector, a hold unit that holds the frequency offset correction vector, and a first unit. The complex conjugate conversion unit that performs the complex conjugate conversion of the vector multiplied by the multiplication unit of, and the second multiplication unit that sends the output signal obtained by multiplying the vector obtained by the complex conjugate conversion by the complex conjugate conversion unit and the combined signal. It is a configuration to be provided.

【0016】

The frequency offset correction device according to claim 6 has, as the frequency offset correction means, a complex conjugate conversion unit that performs complex conjugate conversion of the frequency offset vector from the frequency offset detecting means, and a signal and a complex after addition synthesis by the addition synthesis means. It is configured to include a multiplication unit that outputs an output signal corrected by multiplying the frequency offset vector obtained by complex conjugate conversion from the conjugate conversion unit.

【0017】

These frequency offset correction devices can be suitably used as a demodulator for code division multiple access.

【0018】

[Action]

The frequency offset correction device according to claim 1, 2, 3, 4, 5, 6 having such a configuration is applied to a demodulator for code division multiplex transmission, and diffuses a digitized baseband signal in a time-shifted manner. Each correlation signal that is back-diffused by the signal is detected, and each of these detection signals is added and synthesized. A frequency offset value is detected using a known portion of the synthesized signal, and correction for removing the detected frequency offset is performed. That is, the frequency offset is detected from the low-speed data obtained by adding and synthesizing, and the output signal is rotated in the reverse direction to correct the frequency offset.

【0019】

As a result, even if the number of passes such as antennas is increased in the receiving device equipped with the device as a countermeasure against multipath, the frequency offset of each pass is the same, so that when correcting the frequency offset. The amount of calculation of is reduced, and the processing time is reduced. Further, when the amount of calculation is predetermined, a larger number of paths can be combined, and the quality of the received signal is improved. Further, it is possible to cope with the case where one received high frequency signal is divided into a plurality of channels and used.

【0020】

[Example]

Next, an embodiment of the frequency offset correction device of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment of the frequency offset correction device of the present invention. In FIG. 1, this first embodiment is provided in a receiver of a CDMA base station apparatus that delay-detects a received high-frequency signal and further divides it into a plurality of channels for use, and uses a plurality of antennas (not shown). A frequency conversion circuit 1 that receives a signal from the same transmitting side, mixes a received high frequency signal (RF signal) such as a combined reception signal with a local oscillation signal, and outputs a frequency-converted baseband (BB) signal, and this A local oscillator 2 that sends a local oscillation signal to the frequency conversion circuit 1 is provided.

【0021】

Further, an A / D converter 3 that quantizes and samples (digitizes) the baseband signal, and a reception demodulation processing unit A ... N that demodulates each channel having the same configuration are provided. Further, the output signal is rotated in the reverse direction based on the frequency offset detection circuit 7 that detects the frequency offset by comparing the known pilot signal portion of the output signal with the theoretical value and the frequency offset value from the frequency offset detection circuit 7. A frequency offset correction circuit 8 for correcting the frequency offset is provided.

【0022】

The reception demodulation processing unit A ... N detects the correlation circuits 4a, 4b ... 4n that output the correlation value signals that are back-spread with the diffusion codes that are staggered in time, and the correlation value signals from each of them. It has a detection circuit 5a, 5b ... 5n that outputs the detected detection signal, and an addition synthesis circuit 6 that synthesizes and outputs the detection signals from the detection circuits 5a to 5n.

【0023】

FIG. 2 is a block diagram showing a detailed configuration of the detection circuits 5a to 5n in FIG. In FIG. 2, this example shows a delay circuit 14 that delays the correlation value signal from the correlation circuits 4a to 4n by one symbol, and a delay circuit 14 that delays the correlation value signal from the correlation circuits 4a to 4n and the delay circuit 14 by one symbol. It has a multiplication unit 15 that outputs a multiplication signal (detection signal) with the correlation value signal.

【0024】

FIG. 3 is a block diagram showing a detailed configuration of the frequency offset detection circuit 7 and the frequency offset correction circuit 8 in FIG. In FIG. 3, the frequency offset detection circuit 7 outputs the theoretical value of the known signal generated by the known signal theoretical value generating unit 20 that generates the theoretical value of the known signal and the theoretical value of the known signal from the known signal theoretical value generating unit 20 by complex conjugate conversion. The complex conjugate conversion unit 21 is provided.

【0025】

Further, a multiplication unit 22 that detects the phase shift between the known part of the additively synthesized signal and the signal that has undergone the complex conjugate conversion, an n symbol delay unit 23 that delays the phase shift signal from this by n symbols, and this n symbol delay. The complex conjugate conversion unit 24 that performs the complex conjugate conversion of the phase shift signal, the multiplication unit 25 that multiplies the phase shift signal and the complex conjugate conversion signal from the complex conjugate conversion unit 24, and the number of symbols obtained by subtracting n from the number of symbols. There is an integrating unit 26 that integrates the rotation vector of.

【0026】

In addition, a vector / angle conversion unit 27 that converts the integrated vector into an angle, and a 1 / n multiplication unit 28 for dividing the rotation angle between n symbols by the number of symbols to obtain the rotation angle per symbol, and 1 It has an angle / vector conversion unit 29 that converts the rotation angle per symbol into a frequency offset vector of norm 1, and a hold unit 30 that holds the frequency offset vector until the next frequency offset vector is obtained.

【0027】

The frequency offset correction circuit 8 converts the complex conjugate conversion unit 31 that performs complex conjugate conversion of the frequency offset vector from the frequency offset detection circuit 7 and the signal after addition synthesis and the frequency offset vector that has been complex conjugate converted from the complex conjugate conversion unit 31. A multiplication unit 32 that multiplies and sends an output signal corrected for its frequency offset is provided.

【0028】

Next, the operation of this first embodiment will be described. The received high frequency signal (RF signal) is mixed with the local oscillation signal from the local oscillator 2 by the frequency conversion circuit 1 to output the frequency-converted baseband (BB) signal. This baseband signal is digitized by the A / D converter 3 and input to the reception / demodulation processing unit A ... N. The sampling frequency of the A / D converter 3 is the same as the chip rate.

【0029】

In the reception demodulation processing unit A ... N, the correlation circuits 4a to 4n output the correlation value signal despread by the diffusion code obtained by shifting the baseband signal with time to the detection circuits 5a to 5n. The correlation value signal is an integral of one symbol obtained by multiplying the digitized baseband signal from the A / D converter 3 by the diffusion signal. In the detection circuits 5a to 5n, the detection is performed by multiplying the demodulation conjugate of the signal one symbol before, and the delay circuit 14 shown in FIG. 2 delays the correlation value signal from the correlation circuits 4a to 4n by one symbol. , The multiplication unit 15 multiplies the correlation value signal to detect it.

【0030】

The detection signals from the detection circuits 5a to 5n are combined by the additive synthesis circuit 6 and output. This output signal is input to the frequency offset detection circuit 7, where the known pilot signal portion is compared with the theoretical value, the frequency offset is detected, and the output signal is output to the frequency offset correction circuit 8. The frequency offset correction circuit 8 reversely rotates the output signal based on the frequency offset value from the frequency offset detection circuit 7 and transmits the output signal corrected for the frequency offset.

【0031】

In this case, in the frequency offset detection circuit 7 shown in FIG. 3, the known portion of the additively synthesized signal and the theoretical value of the known signal from the known signal theoretical value generation unit 20 are complex conjugate-converted by the complex conjugate conversion unit 21. And are multiplied by the multiplication unit 22 to detect the phase shift. The multiplication unit 25 multiplies the signal indicating this phase shift and the signal indicating this phase shift by n symbol delay from the n symbol delay unit 23 and the complex conjugate conversion by the complex conjugate conversion unit 24. Further, the integrating unit 26 integrates the rotation vector for the number of symbols obtained by subtracting n from the number of symbols of the known signal. Therefore, signals other than known signals are zero.

【0032】

The vector integrated by the integrating unit 26 is converted into an angle by the vector / angle conversion unit 27. This transformation gives the angle of rotation between n symbols. This angle is divided by the number of symbols by the 1 / n multiplication unit 28 to obtain the rotation angle per symbol, and the angle / vector conversion unit 29 converts the rotation angle per symbol into a frequency offset vector of norm 1. , The hold unit 30 holds the vector until the next frequency offset vector is obtained. In this way, the frequency offset is detected.

【0033】

For example, if the number of symbols in the pilot signal is 5 and the number of data symbols between the pilot and the next pilot is 70 and n = 2, find the rotation vector between the first and third symbols of the pilot. , Find the rotation vector between the 2nd and 4th symbols, and further find the rotation vector between the 3rd and 5th symbols. The frequency offset vector is obtained by integrating these three rotation vectors, transforming the rotation vector by an angle, multiplying it by 1/2, and transforming the vector. The hold unit 30 holds between these 75 symbols.

【0034】

In the frequency offset correction circuit 8 shown in FIG. 3, since the signal after addition and synthesis in the frequency offset detection circuit 7 is rotated by the frequency offset, all the symbol signals are rotated in the reverse direction by the frequency offset. That is, the complex conjugate conversion unit 31 performs complex conjugate conversion of the frequency offset vector, and the signal after addition and synthesis is multiplied by the multiplication unit 32 to obtain an output signal with the frequency offset corrected.

【0035】

Next, the second embodiment will be described. FIG. 4 is a block diagram showing the configuration of the second embodiment. In FIG. 4, the second embodiment is provided in a receiver of a CDMA base station apparatus that sequentially follows and synchronously detects a received high-frequency signal and further divides the received high-frequency signal into a plurality of channels for use. That is, the configuration of the frequency offset correction circuit 8a in the first embodiment is as shown in FIG. Further, as shown in FIG. 6 for a detailed configuration, a frequency offset correction / discrimination circuit 45 for performing frequency offset correction and discrimination with respect to the output signal from the frequency offset correction circuit 8a is provided.

【0036】

Further, as shown in FIG. 6, a sequential follow-up synchronous detection circuit 44 corresponding to the detection circuits 5a to 5n in the first embodiment and performing sequential follow-up synchronous detection and an estimated fading vector Z (n). ) Is delayed by one symbol, and a multiplication unit 46 is provided to output a detection signal obtained by multiplying the correlation value signal by the complex conjugate conversion. Other configurations are the same as in FIG. 1, and are omitted in the figure.

【0037】

FIG. 5 is a block diagram showing a detailed configuration of the frequency offset correction circuit 8a in FIG. In FIG. 5, the frequency offset correction circuit 8a is provided with a multiplication unit 61 for multiplying the frequency offset correction vector and the frequency offset vector, and a hold unit 62 for holding the frequency offset correction vector. Further, a complex conjugate conversion unit 63 for performing complex conjugate conversion of the vector multiplied by the multiplication unit 61 and a multiplication unit 64 for multiplying the combined signal by adding the vector subjected to the complex conjugate conversion are provided.

【0038】

The frequency offset detection circuit 7 has the same configuration as that shown in FIG. 3, and the frequency offset detection circuit 7 of FIG. 3 will be described below in duplicate.

【0039】

FIG. 6 is a block diagram showing a detailed configuration of the sequential follow-up synchronous detection circuit 44 and the frequency offset correction / discrimination circuit 45 in FIG. In FIG. 6, the sequential follow-up synchronous detection circuit 44 weights the delay unit 70 that delays the added θ (n) signal, the correlation value signal i up to the previous symbol, and the determination signal o, as will be described later. A multiplication unit 71 that outputs the sum of correlations θ (n-1) multiplied by λ is provided.

【0040】

Further, an addition unit 72 that adds the correlation value signal i up to the previous symbol and the signal multiplied by λ by the multiplication unit 71, and a multiplication unit 73 that multiplies the correlation value signal i and the signal obtained by complex conjugate conversion of the determination signal o. , A delay unit 74 for delaying the φ (n) signal, which is the sum of the determination signal o and the weighted sum φ (n-1) multiplied by λ, is provided. Further, the multiplication unit 75 that multiplies the weighted sum φ (n-1) of the norm of the judgment signal o up to the previous symbol by λ, and the judgment signal o and the weighted sum φ (n-1) multiplied by λ are added. An addition unit 76 is provided.

【0041】

Further, a multiplication unit 77 for multiplying the determination signal o and the complex conjugate-converted signal, and a complex conjugate conversion unit 78 for performing the complex conjugate conversion for obtaining the correlation between the determination signal o and the correlation value signal i are provided. .. Further, the division unit 79 that divides θ (n) by φ (n) to obtain the estimated fading vector Z (n), the delay unit 80 that delays the estimated fading vector Z (n) by one symbol, and 1 It has a complex conjugate conversion unit 81 that performs complex conjugate conversion of the estimated fading vector Z (n) delayed by a symbol.

【0042】

The frequency offset correction / discrimination circuit 45 outputs a known signal portion such as a pilot signal obtained by rotating this theoretical value by the frequency offset as a judgment signal o, and outputs a signal other than the known signal through the frequency offset correction circuit 8a. It has a frequency offset correction unit 82 that determines whether the signal is positive or negative, and a signal determination unit 83 that obtains a determination signal o obtained by multiplying the frequency offset vector when the signal is other than a known signal.

【0043】

Next, the operation of this second embodiment will be described. In FIG. 4, the operation up to the correlation circuit 4a is the same as the configuration shown in FIG. That is, the reception demodulation processing unit (reception demodulation processing unit A ... N in FIG. 1) that frequency-converts the received high-frequency signal, converts this baseband signal into a digital signal, and demodulates each channel having the same configuration. Demodulate. Further, the frequency offset detection circuit 7 detects the frequency offset, and the frequency offset correction circuit 8a transmits an output signal corrected by the frequency offset correction circuit 8a based on the frequency offset value.

【0044】

Hereinafter, the operation of sequential follow-up synchronous detection will be described. Here, from the detected signal y in FIG. 6, the signal o estimated to have been transmitted (received high frequency signal) is determined, the determination signal o is correlated with the correlation value signal i, and fading is performed sequentially. Estimate the signal. This estimated signal Z is multiplied by the correlation value signal i to perform sequential follow-up synchronous detection.

【0045】

First, in FIG. 6, in order to obtain the correlation between the correlation value signal i and the determination signal o, the correlation value signal i and the signal obtained by complex conjugate conversion of the determination signal o by the complex conjugate conversion unit 78 are multiplied by the multiplication unit 73. .. Further, the sum θ (n-1) of the weighted correlation between the correlation value signal i up to the previous symbol and the determination signal o is multiplied by λ in the multiplication unit 71. Then, the signal from the multiplication unit 71 and the signal from the multiplication unit 73 are added by the addition unit 72. This added θ (n) is delayed by the delay unit 70 and is used as θ (n-1) in the next symbol calculation.

【0046】

In the same way, in order to obtain the norm of the judgment signal o, the judgment signal o and the signal obtained by complex conjugate conversion of this judgment signal o by the complex conjugate conversion unit 78 are multiplied by the multiplication unit 77, and the judgment signal o up to the previous symbol o. The weighted sum φ (n-1) of the norm of is multiplied by λ by the multiplication unit 75, and the signal from the multiplication unit 77 and the signal from the multiplication unit 75 are further added by the addition unit 76. This added φ (n) is delayed by the delay unit 74 and is used as φ (n-1) in the next symbol calculation.

【0047】

Since the correlation between the correlation value signal i and the determination signal o and the norm of the determination signal o are exponentially weighted and added, an estimation signal is created from the data of several symbols in the past. The fading vector Z (n) obtained by dividing θ (n) by φ (n) with the divider 79 is obtained. That is, the value of the estimated fading vector Z (n) is delayed by one symbol in the delay unit 80, further subjected to the complex conjugate conversion by the complex conjugate conversion unit 81, and then multiplied by the correlation value signal i and the multiplication unit 46. Obtain the detection output.

【0048】

The determination signal o required for the operation of the sequential follow-up synchronous detection circuit 44 in the sequential follow-up synchronous detection circuit 44 is output from the frequency offset correction / discrimination circuit 45. In the frequency offset correction / discrimination circuit 45, the judgment signal o is obtained by rotating the theoretical value of a known signal portion such as a pilot signal by the frequency offset. Further, the signal o for which the positive / negative judgment of the output signal is rotated by the frequency offset is defined as the judgment signal o.

【0049】

In the frequency offset correction / discrimination circuit 45, the determination signal o is obtained by the signal determination unit 83 rotating the theoretical value of a known signal portion such as a pilot signal by the frequency offset. If it is not a known signal, the positive / negative judgment is made for the output signal through the additive synthesis circuit 6 and the frequency offset correction circuit 8a. Further, the frequency offset correction unit 82 multiplies the frequency offset vector to obtain the determination signal o. As a result, when the correlation between the correlation value signal i and the determination signal o is obtained, the rotation of the correlation value signal i due to the frequency offset is canceled. That is, the same result as in the case of sequential follow-up synchronous detection after correcting the frequency offset can be obtained.

【0050】

The sequential follow-up synchronous detection signal through the sequential follow-up synchronous detection circuit 44 and the multiplication unit 46 is added and synthesized by the additive synthesis circuit 6 together with other sequential follow-up synchronous detection signals. Since this data rotates according to the frequency offset as in the first embodiment, the frequency offset correction circuit 8a rotates in the reverse direction by the frequency offset detected by the frequency offset detection circuit 7 to perform correction.

【0051】

The operation of the frequency offset detection circuit 7 shown in FIG. 5 in this case is the same as that of the first embodiment. The frequency offset correction circuit 8a offsets the frequency by the frequency offset with respect to the combined signal added by the addition / synthesis circuit 6. Specifically, since the signal rotates by the frequency offset, the frequency offset correction vector held by the hold unit 62 and the frequency offset vector are multiplied by the multiplication unit 61, and further, the complex conjugate conversion is performed by the complex conjugate conversion unit 63. The resulting vector is added and the synthesized signal is multiplied by the multiplication unit 64.

【0052】

As a result, the same signal as when the frequency offset is corrected in each path (received high frequency signal) is obtained. That is, the frequency offset correction is once / symbol, and the amount of calculation is smaller than when the frequency offset correction is performed for each pass or when the frequency offset correction is performed for the baseband signal. The processing time will be reduced.

【0053】

As described above, in the first and second embodiments, the frequency offset is detected in the low-speed data added and synthesized, and the output signal is rotated in the reverse direction to correct the frequency offset. As a result, even if the number of passes such as antennas is increased as a countermeasure against multipath, the frequency offset of each pass is the same, so that the amount of calculation for correcting the frequency offset is reduced and the processing time is reduced. It can be reduced, for example, to enable higher speed data transmission. On the contrary, when the amount of calculation is limited, a larger number of paths can be combined, and the quality of the received signal is improved. Further, since the reception demodulation processing units A ... N are provided, it is possible to deal with the case where one received high frequency signal is divided into a plurality of channels and used.

【0054】

[Effect of the invention]

As is clear from the above description, according to the frequency offset correction device according to claim 1,2,3,4,5,6,7, the digitized baseband signal is reversed with a time-shifted diffusion signal. Each diffused correlation signal is detected, and each of these detection signals is added and synthesized. The frequency offset value is detected by using the known part of the synthesized signal, and the corrected frequency offset is removed. That is, since the frequency offset is corrected by the low-speed data that is added and synthesized, there is an effect that the amount of calculation is reduced, the processing time is reduced, and data transmission at higher speed is possible.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the structure of the 1st Example of the frequency offset correction apparatus of this invention.

[Figure 2]

It is a block diagram which shows the detailed structure of the detection circuit in FIG.

[Fig. 3]

It is a block diagram which shows the detailed structure of the frequency offset detection circuit and the frequency offset correction circuit in FIG.

[Fig. 4]

It is a block diagram which shows the structure of the 2nd Example.

[Fig. 5]

It is a block diagram which shows the detailed structure of the frequency offset correction circuit in FIG.

[Fig. 6]

It is a block diagram which shows the detailed structure of the sequential follow-up synchronous detection circuit and frequency offset correction / discrimination circuit in FIG.

[Fig. 7]

It is a block diagram which shows the structure of the frequency offset correction apparatus of the conventional example.

[Fig. 8]

It is a block diagram which shows the structure of the frequency offset correction apparatus of another conventional example.

[Explanation of symbols]

4a ~ 4n Correlation circuit 5a ~ 5n detection circuit 6 Additive synthesis circuit 7 Frequency offset detection circuit 8a, 8 frequency offset correction circuit 14 Delay circuit 15 Multiplying part 44 Sequential follow-up synchronous detection circuit 45 Frequency offset correction / discrimination circuit 46 Multiplying part