Data generating method, data generator, disk and data transmitter

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a data forming method for forming an error correction code suitable for transmission and recording of digital data.

【0002】

[Conventional technology]

As error correction codes used for transmission and recording of digital data, many methods and devices for product-coding error-correcting code sequences such as Reed-Solomon codes and interleaving data before and after product coding have been put into practical use. There is.

【0003】

Product coding of two series of error correction codes is such that each data symbol is included in two error correction codes, so that even if one error correction code becomes uncorrectable, the other error correction If the code can be corrected, there is an effect that repeated correction based on the correction result becomes possible. Further, by generating a disappearance pointer in the other error correction code based on one uncorrectable error correction code, there is an effect that it is possible to correct the loss error with a large number of correction symbols. Therefore, the product coding technique has been widely used conventionally. Further, data interleaving has the effect of lengthening the correctable burst error by dispersing the burst error, and is therefore used in most recording systems in which burst error is likely to occur.

【0004】

However, in the conventional product coding technology of two series of error correction codes, the external code (first error correction code) is protected by the internal code (second error correction code), but the internal code is protected. Since (the second error correction code) is not protected by any of them, the above correction cannot be performed when the second error correction code becomes uncorrectable.

【0005】

In addition, both the product code configuration and the data interleaving are expensive because the coding device and the recovery device require a memory having a size commensurate with the product code configuration length and the interleaving length and its control circuit. Long product codes and long interleaved codes with error correction capability have the drawback of complicating the device. That is, the conventional product code component with interleaving is, for example, as shown in FIG. 13, delayers 53-1 and 53 for interleaving provided between the error correction coding devices 51 and 52 of two systems. Since -2 ... is set with different delay amounts for each symbol, delayers 53-1 and 53-2 ... with different delay amounts are used as one of the first error correction code systems. It is necessary to use the number equal to the code symbol length. For this reason, it has been difficult to perform long interleaving between code sequences having a long code symbol length with improved error correction capability.

【0006】

[Problems to be Solved by the Invention]

The present invention has been made in view of such a point, and an object of the present invention is to provide a system capable of enhancing the protection of the second error correction code and strengthening the error correction capability.

【0007】

Another object of the present invention is to provide a system capable of significantly reducing the complexity of hardware for processing an extremely large product code or interleave length.

【0008】

[Means for solving problems]

In order to solve such a problem, the data forming method of the present invention according to claim 1 includes a step of dividing data into data packets of a certain length and forming a sector packet composed of a plurality of divided data packets, and the sector packet. The first code obtained by generating the first error correction code of each series in the sector packet obtained by adding the second error correction code added to the previous sector packet and adding it to each data packet. A step of forming a sequence, a step of interleaving a sector packet in which the first code sequence is stacked in the order of division, and an interleaving process by stacking a plurality of stages, and a step of generating a second error correction code of each sequence after the interleave processing are generated for each. It includes a step of forming a second code sequence added to the sequence.

【0009】

The data forming method of the present invention according to claim 2 includes a step of dividing data into data packets of a certain length and forming a sector packet composed of a plurality of divided data packets, and a sector packet immediately before the sector packet. The step of generating the first error correction code of each series in the sector packet to which the second error correction code added to is added to form the first code sequence added to each data packet, and A step of performing intra-block interleaving processing on sector packets in which the first code sequence is stacked in the order of division, and a block interleaving process in which block interleaving processing is performed on a block-by-block basis by stacking multiple stages of sector packets subjected to intra-block interleaving processing. It includes a step to be performed and a step of forming a second code sequence formed by generating a second error correction code of each series after the block interleaving process and adding the code to each series.

【0010】

The data forming apparatus of the present invention according to claim 3 is a sector packet forming means for dividing data into data packets having a fixed length and forming a sector packet composed of a plurality of divided data packets, and one before the sector packet. Generates the first error correction code of each series in the sector packet by adding the second error correction code added to the sector packet of, and forms the first code sequence added to each data packet. The first code sequence forming means, the interleaving processing means for performing interleaving processing by stacking a plurality of stages of sector packets in which the first code sequences are stacked in the division order, and the second error correction code of each sequence after the interleaving processing are used. It is provided with a second code sequence forming means for forming a second code sequence that is generated and added to each sequence.

【0011】

The data forming apparatus of the present invention according to claim 4 is a sector packet forming means for dividing data into data packets having a fixed length and forming a sector packet composed of a plurality of divided data packets, and one before the sector packet. Generates the first error correction code of each series in the sector packet by adding the second error correction code added to the sector packet of the above, and forms the first code sequence added to each data packet. An intra-block interleaving processing means that performs intra-block interleaving processing in each block by stacking a first code sequence forming means and a sector packet in which the first code sequence is overlapped in a dividing order, and a sector packet in which intra-block interleaving processing is performed. A block interleaving processing means that performs block interleaving processing in block units by stacking multiple stages, and a second code sequence that generates a second error correction code for each series after block interleaving processing and adds it to each series. It is provided with a second code sequence forming means for forming the above.

【0012】

The disk of the present invention according to claim 5 divides data into data packets of a certain length, and is added to a sector packet composed of a plurality of divided data packets and a sector packet immediately before the sector packet. It is generated for each series in the sector packet to which the error correction code of is added, and is generated for each series after the first error correction code added to the sector packet and the interleaving process, and is added to the sector packet. It also has a second error correction code.

【0013】

The disk of the present invention according to claim 6 divides data into data packets of a certain length, and is added to a sector packet composed of a plurality of divided data packets and a sector packet immediately before the sector packet. It is generated for each series in the sector packet to which the error correction code of is added, and is generated for each series after the first error correction code added to the sector packet and the interblock interleaving process and the block interleaving process. It includes a second error correction code added to the sector packet.

【0014】

The data transmission apparatus of the present invention according to claim 7 has (k × m-po) symbol × n lines for any positive integers k, m, n, pi and a positive integer po smaller than k × m. From the original data packet composed of and the second parisity symbol having the pi symbol × n-line configuration generated and added by the second coding means, the first parisity symbol of po symbol × n-row is generated. In addition, a set consisting of the first error correction code n series of code length (k × m + pi) symbols is formed, and the first error correction code sequence of (k × m + pi) symbol × n lines is formed. The first coding means to be used and the coded packet data formed in the first correction code sequence and arranged in the matrix, excluding the part of the pi symbol × n rows (k × m) of the symbol × n rows. A block delay that divides a part into k blocks of m symbol x n rows in size and arranges the divided k blocks as one diagonal element block of a block matrix of k blocks x k rows. For the arrangement means and a plurality of original data packets to be transmitted sequentially and sequentially, while performing the first coding and block delay arrangement in sequence, k blocks × 1 line, that is, after block delay arrangement (k × m). ) From a matrix of symbol x n rows, a second parity symbol of pi symbol x n rows is generated and added, and each code length consists of a second error correction code n series of (k x m + pi) symbols. After the formation of the second coding means for forming the second error-correcting code of (k × m + pi) symbol × n rows and the second error-correcting code sequence formed by the second coding means. It is provided with a means for sequentially outputting and transmitting n rows of the matrix symbols in the row direction (k × m + pi) as the final coded packet data which is the second error correction code sequence.

【0015】

In the data transmission device of the present invention according to claim 8, in the data transmission device of claim 7, the symbol arrangement order of the original packet data composed of (k × m-po) symbol × n rows is in the row direction ( k × m-po) The feature is that the symbol × n lines. In the data transmission device of the present invention according to claim 9, in the data transmission device of claim 7, the first coding means for forming the first error correction code n series of the code length (k × m) symbol is (k × m-po) The original data packet matrix of symbol × n rows is included on the left end side (k × m) The row number of the matrix of symbol × n rows is 0 to n-1, and the column number is 0 to k × m. When -1, the row with row number 0 is rotated and arranged in the row corresponding to row number n to convert it into a row circular matrix that can handle rows with row number n or more, and the i-th row (k × m-po) The position of the (i + k × m-po-1) row (k × m-po-1) column obtained by incrementing the row number and column number by 1 from i row 0 column. The i-th first error correction code is obtained by incrementing the row number and column number by 1 from i row 0 column (i + k × m-po-1) row (k). Place (k × m-po) original data symbols up to the × m-po-1) column at the positions of row numbers 0 to n-1 and row numbers k × m to k × m + po-1. The row number and column number are incremented by 1 from the i-row (k x m) column of the row-circular matrix of the second parity symbol of the pi symbol × n rows generated and added by the corrected second coding means. From the pi second parity symbols up to the (i + pi-1) row (k × m + pi-1) column obtained by the above, po first parity symbols are generated, and (i +) k × m-po) From row (k × m-po) columns to (i + k × m-1) rows (k × m-1) columns obtained by incrementing the row number and column number by one It is characterized in that it is inserted and arranged as po first parity symbols to form a code.

【0016】

The data transmission device of the present invention according to claim 10 is the data transmission device according to claim 9, when the first coding means performs the first coding after the block delay arrangement, the first coding is performed. The feature is that the same result as the one in which the block delay arrangement is performed later can be obtained.

【0017】

The data transmission device of the present invention according to claim 11 is a second coding means for forming a second error correction code n series of code length (k × m + pi) symbols in the data transmission device of claim 7. However, the data transmission device is characterized in that pi second parity symbols are added to each row of (k × m) symbol × n rows after the block delay arrangement.

【0018】

The data transmission device of the present invention according to claim 12 is the data transmission device of claim 7, wherein m is equal to n.

【0019】

In the data transmission device of the present invention according to claim 13, in the data transmission device of claim 7, the means for sequentially outputting and transmitting the second error correction code sequence as the final coded packet data is the second error correction code 1. It is characterized by constructing a synchronization frame in which the length of a fraction of an integer of the (k × m + pi) symbol, which is the code length of the series, is one unit.

【0020】

The data transmission device of the present invention according to claim 14 is characterized in that the relationships of all rows and columns are exchanged in the data transmission devices of claims 7 to 13.

【0021】

[Action]

In the present invention, since the first error correction code of each series in the sector packet obtained by adding the second error correction code added to the sector packet immediately before the sector packet is generated, the second error correction code is generated. The error correction code of is protected by this first error correction code. Therefore, the error correction capability can be strengthened. Further, in the present invention, the coding or recombining process, in which the memory size and the control circuit scale thereof have increased in proportion to the product code configuration length and the interleave length, is the same process for each small block. By adopting a coding method that only needs to be performed many times, it is sufficient that there are several types of circuit blocks that perform the same processing. That is, a block interleaving method is adopted in which one code sequence set is divided into a plurality of blocks and interleaved for each block, which was conventionally performed for each symbol.

【0022】

[Example]

Hereinafter, the details of the examples of the present invention will be described with reference to the drawings.

【0023】

First, the procedure of data formation according to the present invention will be described with reference to FIGS. 1 to 5.

【0024】

As shown in FIG. 1, the original data packet before encoding is composed of (9 × 16-14) symbols × 16 lines from the left end. The data arrangement order in the original data packet matrix of 130 symbols × 16 rows is 130 symbols in the order of 0 to 129 columns in each row, and these are arranged in the order of 0 to 15 rows. Further, the second parity symbol 8 symbols × 16 rows generated immediately before by the second coding means described later are shown in the rightmost 8 columns in FIG. 1 for the first coding.

【0025】

In the first coding, the first parity symbol of 14 symbols × 16 rows generated from the original data packet matrix 130 symbols × 16 rows and the second parity symbol shown at the right end is inserted into columns 130 to 143. Form a series of 16 external codes with 152 symbols x 16 lines.

【0026】

This first code sequence is, for example, 16 sequences of Reed-Solomon (152, 138, 15) codes, and is formed so that the code words of each of the 16 sequences are as shown by arrows in FIG.

【0027】

Next, in the original data packet excluding the second parity symbol in FIG. 1 and the matrix of the first parity symbol 144 symbols × 16 rows, the row numbers are 0 to 15, the column numbers are 0 to 143, and the row numbers are set. The line with line number 0 is rotated and arranged on the line corresponding to 16, and the line with line number 16 or more is handled.

【0028】

Then, as shown in FIG. 2, the symbol in the i (0 i 15) th row is obtained by incrementing the row number and the column number by 1 from i row 0 column (i + 143) row 143 columns. Relocate to the position up to.

【0029】

Figure 2 does not show the second parity symbol placed on the far right to generate the first parity symbol, but the arrows in Figure 2 show the sequence of first codewords after relocation. .. Therefore, in the generation of the first parity symbol, after rearranging the symbol of the original data packet part in Fig. 1 as shown in Fig. 2, the second parity symbol is placed at the right end and the code word is a series of arrows. The first coding may be performed so as to be.

【0030】

In any case, the first code sequence is finally formed as shown in FIG. 2 in which 16 codes diagonally scan a matrix of 144 symbols × 16 rows. Therefore, when a second code sequence is to be formed by intersecting the first code sequence for product coding, all 16 codes constituting the first code sequence are rows of a matrix. Since the same diagonal scan is periodically repeated for every 16 symbol strings corresponding to the number, as it is, only one symbol in one code constituting the first code sequence forms the second code sequence. It cannot be included in one constituent code. Therefore, in order to make it possible to form a product code by further intersecting the second code sequence on the first code sequence and at the same time to enhance the burst error correction capability, the first code sequence is interleaved. At this time, the interleave skillfully utilizes the property that all 16 codes constituting the first code sequence periodically repeat the same diagonal scan for every 16 symbol strings, which is a number corresponding to the number of rows in the matrix. By performing block interleaving in which the unit is a block of 16 rows × 16 columns, the configuration of the device related to the delay device, memory control, and formation of the second code sequence is simplified.

【0031】

That is, as shown in FIG. 3, 144 symbols × 16 rows are first divided into 9 blocks having a size of 16 symbols × 16 rows, and the divided 9 blocks are divided into 9 blocks × by a delayer. Place the block containing 0 columns in the 9-row block matrix as one diagonal element block with the first block at the upper left position.

【0032】

Next, 9 blocks × 1 line, that is, after the block delay arrangement (9 × 16), while sequentially performing the first coding and block delay arrangement for a plurality of original data packets to be transmitted sequentially. A second parity symbol with 8 symbols x 16 rows is added to a matrix with 16 rows of symbols, and a set consisting of 16 series of second error correction codes with a code length of (9 x 16 + 8) is added. None, 152 symbols x 16 lines of internal code (second error correction code) form a series. The second code (internal code) series formed in this way is shown in the frame of 152 symbols × 16 lines in FIG. 3, for example, 16 series of Reed-Solomon (152, 144, 9) codes. is there. This series of operations is performed line by line, and 14 lines of 152 symbols are sequentially output and transmitted as final coded packet data in the line direction.

【0033】

FIG. 4 shows a basic configuration example of an apparatus that performs the first coding (formation of the outer code sequence) to the second coding (formation of the inner code sequence) described above.

【0034】

In FIG. 4, the original data packets of 130 symbols × 16 lines are sequentially input to the first coding device 41 one packet at a time, and at the same time, the second parity (internal code parity) added by the second coding device is added. ) Is also input after a delay of 16 lines by the delay device 42 for internal code feedback.

【0035】

In the first coding device 41, while diagonally scanning and rearranging the original symbol matrix according to the first coding procedure, external code parity 14 columns × 16 rows are also generated and inserted diagonally, and 152 columns × 16 An outer code sequence of lines is formed. 144 columns x 16 rows consisting of the original symbol matrix of this outer code series and the parity part of the generated and inserted outer code are in 16 column units, and 9 blocks numbers 0 to 8 consisting of 16 columns x 16 rows respectively. It is divided into blocks, and each block is guided to a delayer whose delay amount is set to (block number x 16 lines). Since the delay amount of block number 0 is actually 0, only eight delayers 43-1, 43-2 ... Are shown in FIG. In this way, the nine blocks that appear at the delayer output at the same time after undergoing different delays for each block are the ones that contain one block from each of the nine external code sequences, and these nine blocks It is clear that the resulting symbol matrix will be the same as the 144 columns x 16 rows in Figure 3, which is completed after all nine external code sequences have been block interleaved.

【0036】

Then, the symbol matrix of 144 columns × 16 rows is input to the second coding device 44, and the internal code parity 8 columns × 16 rows by row direction calculation is added according to the second coding procedure, and 152 columns. × 16 lines of internal code series are formed.

【0037】

Further, the internal code parity of 8 columns × 16 rows is returned to the first coding device 41 after being delayed by 16 lines by the internal code feedback delayer 42 in order to generate the next external code.

【0038】

In this embodiment, for the last 152 symbols for one line, which is the length of one internal code, a synchronization frame having 76 symbols, which is half the length, as one unit is configured and transmitted. .. The structure of the synchronization frame of 76 symbols is, for example, a structure having a frame synchronization signal (SYNC) at the beginning thereof as shown in FIG.

【0039】

Note that the line-to-line relationship may be reversed from that of the above embodiment.

【0040】

Next, the above data forming apparatus will be described more specifically with reference to FIG.

【0041】

As shown in the figure, the information data multiplexing unit 1 packs compressed video signals, audio signals, sub-video signals such as subtitles, and other control signals used for synchronizing video signals and audio signals into small packets. And multiplex it so that it can be transmitted in one stream.

【0042】

The sector packet processing unit 2 inputs the output of the information data multiplexing unit 1 or the information file management data selected by the selector S1. The information file management data is control information management data relating to the entire compression style of the video signal, the stream number of the audio signal, the compression ratio, and the like. The sector packet processing unit 2 first sector-aligns the information file management data to one sector packet capacity (2048 bytes in this example), and generates a serialization base array for subsequent error correction coding. Here, as shown in FIG. 7, a base array of 128 bytes (or symbols) × 16 lines of sector packets is formed. When the sector packet processing unit 2 generates a sector packet (base) of management data, it then connects the selector S1 to the information data multiplexing unit 1 side to output an information data stream in which sub video signals and audio signals are multiplexed. It receives and forms a sector packet (base) array of 2048 bytes (128B x 16 lines) similar to the above. When the sector packet processing unit 2 arranges one sector packet, it sends a signal to the delay device 3 and the information data error detection code generation unit 4 in units of 128 bytes.

【0043】

The information data error detection code generation unit 4 generates an error detection code (IEC) for each sector.

【0044】

On the other hand, when the information data error detection code generator 4 generates one IEC, the ID generation counter 5 counts up by 1 to generate an address signal (ID) of a sector packet corresponding to the IEC, and a control signal related to the sector. (SLI = content identification signal for each sector packet, etc.) is included and sent to the ID error detection / correction code generator 6.

【0045】

The ID error detection and correction code generation unit 6 generates an error correction code IEC of ID + SLI (selector control signal). Here, the order of the ID and SLI is selected by the selector S2, and when the above IEC is generated, the external code (Po) that generates the first error correction code (Po) by the selector S3 is generated in 1-byte units. Po) It is sent to the generator 7 and the interleave circuit 8 in the block.

【0046】

On the other hand, the transmission timing of the information data is adjusted to the transmission timing of ID + SLI + IEC + EDC by the delay device 3, and the information data is also sent to the external code (Po) generation unit 7 and the interblock interleaving processing unit 8.

【0047】

The line number generation hexadecimal counter 9 performs an upcount operation in accordance with the timing at which the information data (128B) and the signal 1B such as the ID are sent to the external code (Po) generation unit 7. When the first 128B of the sector packet (base) is transmitted, the line number generation hexadecimal counter 9 is set to 0.

【0048】

The line number generation hexadecimal counter 9 transmits the value at that time as an inspection series number together with the information data, the ID signal, and the like to the external code (Po) generation unit 7 and the interblock interleaving circuit 8 together with the counting operation.

【0049】

The external code (Po) generation unit 7 is generated by the sent information data 128B, 1B of the ID signal, 1B from the line number generation hexadecimal counter 9, and the internal code (Pi) generation unit 10, and is used for internal code feedback. A 14-byte first error correction code is generated by 8B of the Pi signal delayed by 16 lines by the delay device 42. In one sector packet, 16 sequences are generated. The array of sector packets at this time is shown in FIG.

【0050】

The inter-block interleaving processing unit 8 is 144B, which is a combination of 128B × 16 lines of information data excluding Pi signals, 1B × 16 lines such as ID, 1B × 16 lines of line numbers, and 14B × 16 lines of external code Po. The sector packet data of × 16 lines is divided into blocks of 16B × 16 lines, and interleaving processing is performed in each block. Figure 9 shows the arrangement of typical original data.

【0051】

The data interleaved in the block is subjected to block interleaving processing by the delay circuit 11 having 9 types of delay amounts.

【0052】

The inter-block interleaving and block interleaving data are sent to the internal code (Pi) generation circuit 10 that generates the internal code (Pi), which is the second error correction code, and the internal code (Pi) is generated.

【0053】

In the sector packet of 152B × 16 lines, which is the sum of the data sent to the internal code generation circuit 10 and the internal code (Pi), the parallel data of 152B is converted into byte series data by the conversion addition unit 12, and each series (row). = Or one line is divided into a plurality of frames.) As a frame, a frame synchronization signal is added and sent to the modulation circuit 13.

【0054】

The modulation circuit 13 modulates this data into a signal suitable for transmission or recording processing, and transmits it by bit serial or records it on a medium such as an optical disk.

【0055】

Next, the data reproduction device according to the present invention will be described.

【0056】

FIG. 10 is a diagram showing the configuration of this data reproduction device, and FIGS. 11 and 12 are diagrams showing the timing of various signals in this device.

【0057】

First, a modulation signal transmitted or recorded on a recording medium is input to the reproduction device shown in FIG. When the reproduction device receives such a modulation signal (a), it sends it to the demodulation circuit 30 and detects the synchronization pattern in the synchronization signal detection circuit 14.

【0058】

In the detection of the synchronization pattern, a false synchronization signal is detected due to a sign error due to a defect or the like even in the information data. Therefore, as a protective measure, the synchronization window generator 15 has a synchronization signal detection window signal whose signal section is longer than that of the synchronization pattern. (c) is generated, and the reproduction synchronization signal generation unit 16 inputs the synchronization detection signal (b) and the synchronization signal detection window signal (c) via the AND circuit 17 to generate the reproduction synchronization signal (d). Then, by performing demodulation based on this reproduction synchronization signal (d), error synchronization is prevented.

【0059】

By the way, the relationship between these modulated signals (a), the synchronization detection signal (b), and the synchronization signal detection window signal (c) is as shown in FIG. 11. In the conversion processing method, if the synchronization signal detection window signal is separated from the synchronization signal by a certain distance or more, synchronization cannot be performed permanently. Therefore, in this embodiment, when synchronization cannot be performed for a certain period of time, the synchronization signal detection window signal is opened and only the first synchronization signal is unconditionally used as a synchronization signal. This is a window signal created because the (c ́) part in the synchronization signal detection window signal (c) in FIG. 11 is opened.

【0060】

The demodulation circuit 13 outputs an error correction code sequence based on the reproduction synchronization signal (d) generated as described above.

【0061】

The internal code error detection and correction processing unit 18 performs error detection and correction processing based on the second error correction code (internal code (Pi)) for the error correction code sequence output from the demodulation circuit 13.

【0062】

The data (e) subjected to the error detection and correction processing by the internal code (Pi) is sequentially sent to the sequence order compensation circuit 19. The internal code error detection / correction processing unit 18 outputs an internal code error flag (f) when the error correction code sequence is uncorrectable data. Further, after the error detection and correction processing by the internal code, the line number data (g) is sent to the line number check circuit 20.

【0063】

The line number check circuit 20 checks the line number data (g) when the correction processing of the error symbol is small in the above internal code error detection and correction processing, and the correction processing can be performed in the internal code error detection and correction processing. Even when the number of error symbols is large, if the ascending (or descending) relationship is confirmed in the two series before and after the series in the error detection and correction processing, the line number data (g) is checked and the internal code error is detected. In the correction process, the data (h) of the presettable hexadecimal counter 21 is checked except for the above two cases. The line number check circuit 20 uses the above data to inspect whether or not the data is correctly sent out in the sequence order, and if it is incorrect, sends a control signal (k) to the sequence order compensation circuit 19 to correct the incorrect sequence.

【0064】

The sequence order compensation circuit 19 uses n types of identification code addition order rules, divides the unit from the identification code determined to be correct and the rule order, and when the number of rows, which is the number of sequences in the unit, is small, a dummy sequence is used. It also has a function to add, remove the duplicated series when the number of series is large, and process the number of lines in the unit to n lines.

【0065】

When the presettable hexadecimal counter 21 detects the correct line number data, the data is preset.

【0066】

Due to the above signal (k), the output data (i) of the sequence order compensation circuit 19 has the correct number of sequences in the correct sequence order, and it is possible to make the best use of the subsequent error detection and correction processing by the external code. become. In the example of FIG. 12, the data of the 13th series in the output data (i) is replaced with the correct data again, and the number of series is also corrected to the correct relationship. As a result, the output data (i) from the sequence order compensation circuit 19 is sent to the delay circuit 22 that performs the block deinterleave processing together with the error flag (j) after the sequence number is also correct in the correct sequence order. The error flag (j) is a flag set for a data packet that cannot be corrected by the internal code.

【0067】

Next, the information data excluding the internal code (Pi) and the external code (Po) are deinterleaved in the block by the deinterleave processing unit 23 in the block, and are outside by the deinterleave processing unit 24 in the external code (Po) error detection and correction processing unit 24. Error detection and correction processing by code is performed. In the error detection and correction processing using the external code (Po), the error flag (j) that cannot be corrected by the internal code is used as the error location instruction signal, and the parity signal is used for error pattern generation to improve the correction capability. It is also used for erasure correction.

【0068】

The information data for which the error correction processing by the external code is completed is output to the decoder circuit (not shown) via the sector packet processing unit 25. The decoder circuit is output to a decoder circuit that decodes information data into a video signal or an audio signal.

【0069】

By the way, information data is received and processed in units of recording sectors, a data sector packet is formed by deinterleave processing, and is decoded into an original data sector packet. However, in a system that reproduces data recorded on a recording medium or the like, it is compressed. While the playback data rate of video data or the like changes, reading from the recording medium is performed by the complete operation. In this case, the disk etc. is constantly rotating, and when a certain amount is stored, the data read point is returned to the front using a buffer memory etc., and when there is free space in the memory again, the last data read before is continuous. It is necessary to read from the part. In this reproduction device, the continuity of such data is managed by the ID signal which is the address signal of the sector packet.

【0070】

First, the ID signal portion is extracted from the output data of the sequence order compensation circuit 19, sent to the ID signal error correction circuit 26 together with the uncorrectable error flag, and error correction processing is performed using the IEC parity signal. By this processing, since the ID signal is composed of only the recording sector and the product code is composed of (Pi) and (IEC), it is possible to have high correction capability.

【0071】

The ID signal detected here is output via the OUT-ID detection circuit 29 and is used for reading control from the recording medium.

【0072】

When the ID signal is not detected by this correction process, the ID control unit 28 uses the output of the ID counter 27 as a substitute for the line number. Unlike the line number, the ID counter 27 is a counter capable of counting more than the number of IDs of the recording medium, and when the correct ID signal is detected by the ID correction circuit 26, the data is preset. This relationship is shown in (i ́) (j ́) (m) (n) (o) in FIG. As a matter of course, the ID signal for the sector packet of the output data can also be corrected again with the IEC code after the correction process with the Pi and Po codes.

【0073】

[Effect of the invention]

As described above, in the present invention, since the second error correction code has a structure protected by the first error correction code, the error correction capability can be further strengthened. In addition, the complexity of the hardware that processes the extremely large product code and interleave length can be greatly reduced.

[Simple explanation of drawings]

[Figure 1]

It is a figure for demonstrating the generation of the outer code in one Example of this invention.

[Figure 2]

It is a figure for demonstrating the interblock interleaving in one Example of this invention.

[Fig. 3]

It is a figure for demonstrating the block interleaving in one Example of this invention.

[Fig. 4]

It is a figure which shows the basic structure of the data forming apparatus of this invention.

[Fig. 5]

It is a figure which shows the structure of the physical sector in one Example of this invention.

[Fig. 6]

It is a block diagram which shows the structure of the data forming apparatus which concerns on this invention.

[Fig. 7]

This is an example of data configuration after sector packet processing in the device of FIG.

[Fig. 8]

It is a configuration example of the data to which the line identification code is added in the device of FIG.

[Fig. 9]

It is a figure for demonstrating the interleaving process in the apparatus of FIG.

[Fig. 10]

It is a figure block diagram which shows the structure of the data reproduction apparatus which concerns on this invention.

[Fig. 11]

It is a figure which shows the timing of various signals in the apparatus of FIG.

[Fig. 12]

It is a figure which shows the timing of various signals in the apparatus of FIG.

[Fig. 13]

It is a figure which shows the structure of the conventional data forming apparatus.

[Explanation of symbols]

1 ......... Information data multiplexing unit 2 ......... Sector packet processing unit 3 ......... Delayer 4 ......... Information data error detection code generator 5 ......... ID generation counter 6 ......... ID error detection and correction code generator 7 ......... External code (Po) generator 8 ......... Interleave processing section in the block 9 ......... Line number generation hexadecimal counter 10 ......... Internal code (Pi) generator 11 ......... Delay circuit 12 ......... Conversion addition part 13 ......... Modulation circuit 14 ......... Synchronous signal detection circuit 15 ......... Synchronous window generator 16 ......... Playback synchronization signal generator 17 ......... and circuit 18 ......... Internal code error detection and correction processing unit 19 ......... Series order compensation circuit 20 ......... Line number Ekku circuit 21 ......... Presetable hexadecimal counter 22 ......... Delay circuit 23 ......... Deinterleaved processing unit in the block 24 ......... External code (Po) Error detection and correction processing unit 25 ......... Sector packet processing unit 41 ......... Internal code feedback delayer