Phase locked loop and frequency synthesizer using the same

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention requires high-speed frequency switching and out-of-band noise for a phase-locked loop and a frequency synthesizer using the same, particularly for an oscillation circuit of a communication device that requires a small local oscillation circuit such as a mobile communication terminal. It relates to a frequency synthesizer using a PLL (Phase Locked Loop) circuit and a PLL circuit suitable for a digital mobile communication terminal or the like that sufficiently suppresses phase noise and the like and requires stable oscillation.

【0002】

[Conventional technology]

As shown in Fig. 2, the basic configuration of a frequency synthesizer using a PLL circuit compares the phase of the output obtained by dividing the output of the voltage controlled oscillator (VCO) 5 by the programmable divider 4 with the reference signal fr. A phase comparator 1, a charge pump 2 that converts the phase comparison result into an injection current or a lead-in current, a loop filter 3 that determines a closed loop frequency band, and a voltage controlled oscillator whose oscillation frequency is controlled by the output of the loop filter 3. It consists of 5. The frequency synthesizer is configured by arbitrarily setting the number of divisions of the programmable frequency divider 4, and since high frequency resolution can be easily obtained, it is widely used as an internal oscillator of a portable wireless terminal.

【0003】

However, in the configuration of the frequency synthesizer shown in FIG. 2, when the phase pull-in is completed and the phase of the output of the voltage controlled oscillator 5 divided by the programmable divider and the phase of the reference signal fr are almost the same, the phase comparator 1 The output pulse of is zero. By the way, the charge pump 2 is composed of two current sources that give an injection current or a pull-in current, and two switches that are controlled by the output of the phase comparator. Therefore, in the state where the two phases match after the completion of phase pulling as described above, the output pulse of the phase comparator 1 becomes almost zero, so that the charge pump may not be able to react. In such a state, the phase between the frequency dividing output of the programmable frequency divider 4 and the reference signal fr is not stable and is observed as a phase fluctuation, resulting in phase noise in the low frequency region. Therefore, for example, the frequency synthesizer described above. When used in the transmission circuit of a mobile phone, problems such as deterioration of modulation accuracy occur.

【0004】

As a technique for avoiding this problem, as shown in FIG. 3, a method of generating a pulse signal synchronized with the input of either one of the phase comparators and adding them in a charge pump is published in Japanese Patent Application Laid-Open No. 5-206845. It is described in the issue. That is, the pulse circuit 6 surrounded by the dotted line in FIG. 3 is added, and the signal div-D and the output div-out delayed by the delay circuit 7 are the signal div-D and the output div-out of the programmable divider 4 by the NOT circuit 9. The NAND logic with the inverted signal is set as a signal up-add by the circuit 10-7, and is added 8 to the signal up of the phase comparer 1.

【0005】

The operation of the frequency synthesizer of FIG. 3 will be described with reference to the time chart of FIG. The case where the delay amount of the delay circuit 7 is two ways (at T1 (thick line) and at T2 (thin line)) is shown. Assuming that the frequency synthesizer converges and the injection current and the draw current in the charge pump 2 are almost the same, the period during which the current source on the injection current side in the charge pump 2 is on and the current source on the draw current side are on. The period is almost the same. When the delay amount of the delay circuit 7 is T1, the pulse up + up_add of a constant width pulse up_add corresponding to the delay amount T1 is added to the signal up in synchronization with the frequency division output div_out of the programmable divider 4. Since it is applied to the charge pump 2, the feedback loop consisting of the loop filter 3, the voltage controlled oscillator 5, and the programmable divider 4 cancels out the pulse up + up_add at one output of the phase comparator 1. The signal dn that reduces the frequency of an oscillator 3 is controlled to generate a signal equal to the pulse up + up_add. As a result, the frequency divider output div_out has a constant phase difference corresponding to the pulse width of the pulse up + up_add of a constant width with respect to the reference signal fr, that is, the output of the reference signal fr and the programmable divider 4 after convergence. div_out has a constant phase difference.

【0006】

On the other hand, the pulse width of the pulse up_add depends on the delay amount of the delay circuit 7. Therefore, the phase difference between the frequency-divided output div_out and the reference signal fr depends on the delay amount of the delay circuit 7, and when the delay amount is large, the phase difference is large (T2), and when the delay amount is small, the phase difference is small (T2). T1) When a PLL circuit whose phase difference depends on such a delay amount is used for the frequency synthesizer, the output phase of the frequency synthesizer with respect to the reference signal fr changes depending on the delay amount of the delay circuit 7. When the delay circuit 7 is made of a semiconductor element, the delay amount of the delay circuit 7 is often realized by, for example, a circuit element in which the inverters of the semiconductor element are vertically connected in an even number of stages. There is a problem that it fluctuates easily. As a result, the phase fluctuation corresponding to the fluctuation of the delay amount of the delay circuit 7 occurs in the frequency dividing output div_out and also appears in the output of the voltage controlled oscillator 5 which is the output of the frequency sizar. As described above, in the conventional frequency synthesizer, the point that phase noise is generated due to the delay amount fluctuation of the delay circuit 7 has not been taken into consideration.

【0007】

Further, as a method for solving the problem of the charge pump being unable to respond (dead zone), as shown in US Pat. No. 4,023116, a method of intentionally injecting an error pulse into the output of the phase comparator is known. The problem of so-called spurious generation with an unfavorable phase error with respect to the reference frequency arises.

【0008】

[Problems to be Solved by the Invention]

Therefore, an object of the present invention is that even if the delay amount of the delay circuit 7 fluctuates, the phase difference between the output div_out of the oscillator or the programmable divider 4 and the reference signal fr does not fluctuate, and the phase relationship is always constant. It is an object of the present invention to realize a PLL circuit, that is, a phase-locked loop, which holds the above, and to provide a frequency synthesizer in which phase noise is not generated due to a variation in the delay amount of the delay circuit 7 even if it is applied to a frequency synthesizer.

【0009】

[Means for solving problems]

In order to achieve the above object, the phase synchronization circuit of the present invention provides a constant phase difference between the phase of the signal from the voltage control oscillator or the frequency divider input to the phase comparator and the phase of the reference signal, and performs the above phase comparison. The pulse width corresponding to the constant phase difference in either the output of the device that controls the frequency of the voltage control oscillator in the direction of decreasing or the output of the voltage control oscillator in the direction of decreasing the frequency of the voltage control oscillator. The pulse of the above was added to obtain a circuit configuration in which the phase of the reference signal after convergence of the phase synchronization circuit and the output of the voltage control oscillator or frequency divider match. Further, a frequency synthesizer is configured by adding a means for varying the number of divisions to the frequency divider of the phase-locked loop.

【0010】

As a phase difference setting means for providing a constant phase difference between the output of the frequency divider input to the phase comparator and the phase of the reference signal, the output of the voltage controlled oscillator or the frequency divider is delayed and the phase comparator is used. The output of the delay circuit as one input, or the output of the voltage controlled oscillator or the frequency divider is directly used as one input of the phase comparator, and the reference signal is delayed to be the input of one of the phase comparators. It is composed of a delay circuit. When the output of the frequency divider is delayed, the signal obtained by inverting the polarity of the output of the frequency divider and the logic output of the output of the delay circuit are obtained, and the logic output is the output of the phase comparator. It is composed of a circuit that adds to the output controlled in the direction of lowering the frequency of the voltage controlled oscillator. Further, when delaying the output of the reference signal, a logic circuit that obtains a signal in which the polarity of the reference signal is inverted and a logic output of the output of the delay circuit, and the logic output are the outputs of the phase comparator. It is composed of a pulse generation circuit that adds to the output controlled in the direction of increasing the frequency of the voltage controlled oscillator.

【0011】

[Action]

The present invention has been made by paying attention to the fact that in the conventional PLL circuit (Fig. 2) in which the dead zone is a problem, the phase of the reference signal fr after convergence and the output div_out of the programmable divider 4 are in phase. Even if the pulse circuit 6 as shown in Fig. 2 is used, the phase of the reference signal fr after convergence and the output div-out of the frequency divider are matched, and the influence of the fluctuation of the delay time of the delay circuit is reduced. Excluded for the reasons mentioned above.

【0012】

The principle of the present invention will be described with reference to an embodiment configuration of the frequency synthesizer of the present invention shown in FIG. 1 and a time chart of a main part at the time of convergence shown in FIG. In the embodiment of FIG. 1, the signal div_D delayed by the delay circuit 7 is added to the phase comparison 1 instead of the direct output div_out of the minute cycle as compared with the conventional frequency synthesizer of FIG. The output dn-add of the NAND circuit of the signal whose polarity of the output div_out of the programmable divider 4 is inverted by the inverter 9 and the delayed signal div_D is the output of the phase comparator 1 and determines the frequency of the voltage controlled oscillator 5. It differs in that it is composed of a circuit that adds to the output dn that controls in the decreasing direction.

【0013】

In the circuit of FIG. 1, when the delay time of the delay circuit 7 fluctuates and the output div_D of the delay circuit changes, the reference signal fr applied to the phase comparison 1 is delayed by T1 (T2) with respect to the output div_D of the delay circuit. Therefore, the output up of the pulse width T1 (T2) that controls in the direction of increasing the frequency of the voltage controlled oscillator 5 is generated, but the output dn that controls in the direction of decreasing the frequency of the voltage controlled oscillator 5 is in phase with the output up. And since the output dn-add of the NAND circuit of the same width is added, the two currents of the charge pump are balanced and the PLL circuit converges. After convergence, the phases of the reference signal fr and the output div_out of the programmable divider 4 at the falling point t0 match regardless of the delay time T1 (T2) of the delay circuit 7. Therefore, the phase noise due to the fluctuation of the delay circuit 7 is eliminated.

【0014】

[Example]

FIG. 6 is a block diagram showing the configuration of the first embodiment of the frequency synthesizer according to the present invention. The configuration of this embodiment is substantially the same as the configuration of FIG.

【0015】

The output of the voltage controlled oscillator 5 is an integer (N) times the frequency of the reference signal fr, part of which is taken out as the output of the frequency synthesizer, and the other part is divided by an arbitrary frequency division N. Added to programmable divider 4. A part of the output div-out divided by the frequency divider 4 is delayed for a certain period of time by the delay circuit 7 in which the inverters 9-2 to 9-5 are connected in series. Here, let T be the amount of delay due to the inverters 9-2 to 9-5. Therefore, there is a phase difference of time T between the output div_out of the programmable divider 4 and the output div_D of the delay circuit 7. The other part of the output div-out is reversed in polarity by NOT circuit 9. The output div_D of the delay circuit 7 and the output of the NOT circuit 9 are converted into the NAND logical output dn-add by the NAND circuit 10-7, and the frequency which is one output of the phase comparator 1 is lowered by the AND circuit 8-1. It is added to the control signal dn that controls in the direction of making. A part of the output div-D of the delay circuit 7 is added to the phase comparator 1. The phase comparator 1 generates a control signal dn that controls the frequency in the decreasing direction and a control signal up that controls the frequency in the increasing direction according to the phase difference between the reference signal fr and the signal div-D. The control signal up is applied to the charge pump 2 via the AND circuit 8-2 to which "High" is added as one input. The loop filter 3 takes the output of the charge pump 2 as an input and determines the loop band of the entire PLL. The oscillation frequency of the voltage controlled oscillator 5 is controlled by the output of the loop filter 3.

【0016】

The pulse generation circuit 6 including the delay circuit 7, the NOT circuit 9, and the NAND circuit 10-7 generates a pulse having a constant pulse width corresponding to the delay time T of the delay circuit 7. Here, since the number of stages of the inverters 9-2 to 9-5 constituting the delay circuit 7 is different depending on the delay amount, the number of stages may be any number as long as it is an even number.

【0017】

The circuit configurations of the phase comparator 1, the charge pump 2 and the loop filter 2 are shown in FIGS. 7, 8 and 9, respectively. The phase comparator 1 is the same as a conventionally well-known circuit. As shown in FIG. 7, the reference signal fr is input from the INPUT1 terminal, and the signal div_D to be compared is input from the INPUT2 terminal. Since the following description is composed of a NAND circuit, the following description will be given using negative logic in which a low level signal (hereinafter abbreviated as Low) is valid. It consists of four latch circuits and a four-input NAND (negative product) circuit 12 for resetting them. These four latch circuits are set at Low to detect the input signal INPUT1 and are set to the first latch circuit composed of NAND10-1 and NAND11-1, and are set at Low to detect the input signal INPUT2. A second latch circuit consisting of 2, a third latch circuit consisting of NAND10-2 and NAND10-3 that are reset by the first latch circuit (at Low of NAND10-1), and a second latch circuit. This is the fourth latch circuit consisting of NAND10-4 and NAND10-5, which are reset at (NAND10-5 Low). The outputs of the above four latch circuits are input to the 4-input NAND circuit 12, and the output of the 4-input NAND circuit 12 and the NAND circuit 10-2 reset the first latch circuit and the second latch circuit. Then, the third latch circuit and the fourth latch circuit are connected so as to be set.

【0018】

As shown in FIG. 8, the charge pump 2 includes a current source 14 that determines the injection current Icp, a current source 13 that determines the lead-in current Icn, a switch 15-1 that turns on or off when the control signal is up, and a control signal. It consists of switches 15-2 that are turned on or off with a dn.

【0019】

As shown in FIG. 9, the loop filter 3 is composed of a series circuit of a capacitor 18 and a resistor 17 coupled in parallel with the capacitor 16. The configurations of the phase comparator 1, the charge pump 2, and the loop filter 3 are not limited to the configurations of the above-described embodiment, and other configurations may be used as long as they can realize the same function. For example, a delay circuit may be provided between the output of the NAND circuit 12 of the phase comparator 1 and the input of each latch circuit.

【0020】

FIG. 10 is a time chart for explaining the phase relationship of the main parts at the time of convergence in the first embodiment. There is a phase difference of T between the output div_out of the program divider 4 and the output div_D of the inverters 9-2 to 9-5 constituting the delay circuit 7. The output dn_add of the NAND circuit 10-7 of the signal obtained by inverting the output div_out of the program divider 4 by the inverter 9 and the signal div_D becomes Low only for a period corresponding to the delay amount T. Next, the output P02 of the NAND circuit 10-1 becomes High and the output up of the NAND circuit 11-1 becomes Low due to the falling transition (t0) of the reference signal fr input to INPUT1 of the phase comparator 1. On the other hand, the output P05 of the NAND circuit 10-6 becomes High and the output dn of the NAND circuit 11-2 becomes Low due to the falling transition (t1) of div_D input to INPUT2 of the phase comparator 1. When the output P05 of the NAND circuit 10-6 transitions to High, all the other three inputs of the NAND circuit 12 are already High at that time, so the output P04 of the NAND circuit 12 is synchronized with the rise of the output P05. Transitions to Low. Since the output P04 of the NAND circuit 12 is connected to the NAND circuits 11-1, 11-2, 10-3, 10-4, each output changes to High. Therefore, the outputs P01 and P07 change to Low, and the output P04 of the NAND circuit 12 transitions to High again. Also, the control signals up and dn are both High.

【0021】

As a result of the above, the control signal up becomes Low from the fall point t0 of the reference signal fr to the fall point t1 of div_D, and the signal dn becomes Low only at the moment of the fall of div_D. Furthermore, when the reference signal fr changes to High, the output P02 of the NAND circuit 10-1 changes to High, the output P01 of the NAND circuit 10-2 changes to Low, and when the signal div_D changes to High, the NAND circuit 10-6 The output P05 of the NAND circuit changes to High, and the output P06 of the NAND circuit 10-5 changes to Low, so that the original state is restored.

【0022】

Next, the logical product of the control signal dn and the output dn_add of the NAND circuit 10-7 is processed by AND8-2. Therefore, the output dn + dn_add of AND8-2 is low from the falling transition of the reference signal fr to the falling transition of the signal div_D and for a very short period for the NAND circuit 12 to reset each latch circuit. On the other hand, the control signal up is also input to the AND circuit 8-1. Since the other input of the AND circuit 8-1 is fixed to High, a signal delayed by the delay time of the AND 8-1 is output from the AND circuit 8-1. This is because it is necessary to use the AND circuit 8-2 to add the signal dn_add to the signal dn, so it is used for the purpose of matching the delay amount with the signal up, and it depends on the AND circuit 8-2. If the delay amount is almost negligible, the AND circuit 8-1 can be omitted.

【0023】

When the delay amount of the delay circuit 7 is T, a pulse dn_add having a constant width corresponding to the delay amount T is added to the dn signal and applied to the charge pump 2 in synchronization with the output div_out of the programmable divider 4. Therefore, the feedback loop including the loop filter 3, the voltage controlled oscillator 5, and the programmable divider 4 is controlled so as to cancel the pulse dn_add having the constant width. When the frequency synthesizer converges, the current source on the injection current side of the charge pump is on (Low period of the control signal up) and the current source on the lead current side is on (control signal dn + dn_add). The period of Low) is almost the same.

【0024】

As a result, the signal div_D whose output of the programmable divider 4 is delayed by the delay circuit 7 has a constant phase difference corresponding to the pulse width of the signal dn_add with respect to the reference signal fr. However, the phase relationship between the output div_D and the output div_out of the programmable divider 4 is the previous phase by the phase corresponding to the delay amount of the delay circuit 7, and therefore matches the reference signal fr. Therefore, even if the delay amount T of the delay circuit 7 is different, the reference signal fr and the output div_out of the programmable divider 4 are similarly matched. Due to the above operation, phase noise due to the delay amount fluctuation of the delay circuit 7 does not occur.

【0025】

FIG. 11 is a block diagram showing a configuration of a second embodiment of the frequency synthesizer according to the present invention. The configuration of this embodiment is the same as that of the first embodiment with respect to the phase comparator 1, AND circuit 8-1, 8-2, charge pump 2, loop filter 3, voltage controlled oscillator 5, and programmable divider 4. Is. The difference between the second embodiment and the first embodiment is that the reference signal fr input to one of the phase comparators 1 in the first embodiment constitutes the delay circuit 7 in the second embodiment. The point that the reference signal fr_D input to the inverters 9-2 to 9-5 and delayed further becomes the input of the phase comparator 1 and the output div_out of the programmable divider 4 are delayed in the first embodiment. Whereas the signal div_D was the other input of the phase comparator 1, in the second embodiment, the output div_out of the programmable divider 4 is the direct input of the phase comparator 1 and the first In the second embodiment, the output of the NAND circuit 10-7 is connected to the input of the AND circuit 8-2, whereas in the second embodiment, the input of the AND circuit 8-1 is three points.

【0026】

FIG. 12 shows a time chart at the time of convergence explaining the operation of the second embodiment. Similar to FIG. 5, FIG. 12 shows two types of delays in the delay circuit 7: T1 (thick line) and T2 (thin line).

【0027】

Since the output up_add of the pulse generation circuit 6 is generated by the reference signal fr and its delayed delay reference signal fr_D, it becomes Low only for a period corresponding to the phase difference between these two signals, and is signaled via the AND circuit 8-1. It is added to the up signal and becomes a pulse signal up + up_add with a constant width to control the charge pump 2. On the other hand, the output div_out of the programmable divider 4 and the delay reference signal fr_D are input to the phase comparator 1. When the values of the injection current and the pull-in current in the charge pump 3 are almost the same, the control is performed so that the signal dn that cancels the pulse signal up + up_add is generated, so that the output div_out of the programmable divider 4 stands. The falling phase converges to a phase point earlier than the rising phase of the delay reference signal fr_D. Therefore, the output div_out of the programmable divider 4 always has a phase that matches the reference signal fr even if the delay amount of the delay circuit 7 is different from that of T1 or T2. As a result, as in the first embodiment, even if the delay amount of the delay circuit 7 fluctuates, it is not observed as the phase noise of the frequency synthesizer, and good characteristics can be obtained.

【0028】

FIG. 13 is a block diagram showing a configuration of a wireless communication terminal device using a frequency synthesizer according to the present invention. The wireless communication terminal device is composed of a transmission circuit 21, a reception circuit 23, a demultiplexer 24, an antenna 25, a frequency synthesizer 22, and a control circuit 20 that controls them. The control circuit 20 controls the state of the wireless communication device based on the data received by the reception circuit 23, and instructs the frequency synthesizer of the frequency to oscillate. The frequency synthesizer 22 supplies the indicated oscillation frequency to the transmission circuit 21 and the reception circuit 23. The transmission circuit 21 generates a transmission wave in which the transmission signal from the control circuit 20 is modulated based on the oscillation frequency given by the frequency synthesizer 22, suppresses unnecessary frequency components by the demultiplexer 24, and then the antenna 25. Is sent from.

【0029】

Further, the signal received from the antenna 25 is input to the receiving circuit 23 after the unnecessary signal component is suppressed by the demultiplexer 24. The receiving circuit 23 demodulates the received signal using the signal from the frequency synthesizer 22, and outputs the decoding result to the control circuit 20. The control circuit 20 converts desired data into voice or an image from the transmitted / received signal and outputs the desired data.

【0030】

[Effect of the invention]

As described above, under the condition that the injection current and the pull-in current of the charge pump match, the two signals up and dn + dn_add that control the charge pump are the same in the same phase regardless of the delay amount of the delay circuit 7. It can be a width signal. Therefore, the phase noise deterioration of the frequency synthesizer does not occur due to the fluctuation of the delay amount of the delay circuit 7. In addition, the charge supplied from the charge pump to the loop filter becomes almost zero during the period when these two signals are generated at the same time, and spurious generation, which is a problem when the method shown in US Pat. No. 4,023116 is used, can be suppressed. Moreover, it is possible to operate the phase comparator in a distant phase with respect to the noise of the logic circuit generated when integrated on the semiconductor substrate, for example, the noise associated with the operation of the programmable divider 4. It is effective in further reducing phase noise.

[Simple explanation of drawings]

[Figure 1]

A block diagram showing a configuration of an embodiment of a frequency synthesizer according to the present invention. [Figure 2]

Block diagram showing the configuration of a conventional frequency synthesizer [Fig. 3]

Block diagram showing the configuration of other conventional frequency synthesizers [Fig. 4]

Time chart for explaining the operation of other conventional frequency synthesizers [Fig. 5]

A time chart for explaining the operation of an embodiment of a frequency synthesizer according to the present invention. [Fig. 6]

A block diagram showing a configuration of a first embodiment of a frequency synthesizer according to the present invention. [Fig. 7]

A logic circuit diagram showing the configuration of the phase comparator shown in FIG. [Fig. 8]

Circuit diagram showing the configuration of the charge pump shown in FIG. [Fig. 9]

A circuit diagram showing the configuration of the loop filter shown in FIG. [Fig. 10]

A time chart for explaining the operation of the first embodiment of the frequency synthesizer according to the present invention. [Fig. 11]

A block diagram showing a configuration of a second embodiment of a frequency synthesizer according to the present invention. [Fig. 12]

A time chart for explaining the operation of the second embodiment of the frequency synthesizer according to the present invention. [Fig. 13]

Block diagram of a wireless communication device using a frequency synthesizer according to the present invention [Explanation of symbols]

1 ... phase comparator, 2 ... charge pump, 3 ... loop filter, 4 ... programmable divider, 5 ... voltage controlled oscillator, 6 ... pulse circuit, 7 ... Delay circuit, 8 ... Adder circuit, 8-1,6-2 ... AND circuit, 9, ~ 9-5 ... Inverter, 10-1 ~ 10-7, 11-1 ~ 11-2, 12 ... NAND circuit, 13 ... lead current current source, 14 ... injection current current source, 15-1 ~ 15-2 ... switch, 16, 18 ... capacitor, 17 ... resistor Instrument, 20 ... Control circuit, 21 ... Transmit circuit, 22 ... Frequency synthesizer, 23 ... Receive, 24 ... Demultiplexer, 25 ... Antenna.