Level shifter

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a level shifter (logic level conversion circuit) used when connecting LSIs (large-scale integrated circuits) of different logic levels.

【0002】

[Conventional technology]

In recent years, the power consumption of LSIs has been rapidly reduced, and LSIs with low power supply voltages such as 3.3V 2.5V 1.5V have been developed from 5V (volt).

【0003】

Under these circumstances, the demand for level shifters for connecting LSIs with different logic levels is increasing.

【0004】

For example, 12 ~ 18V like flash memory_PPWhen using the high level logic level of, a conversion with a large level difference is required to obtain this by converting it from the logic level of 1.5V to 3.3V.

【0005】

Conventionally, the circuit shown in Fig. 5 has been used as this type of level shifter. V for input terminal 501 in the figure_CCPower system 0 and V_CCA two-level signal that changes between (for example, 3V) is input, and the output 502 is V._PPPower system 0 and V_PPThe output is converted to a two-level signal that varies between (eg 18V).

【0006】

The 503 is an inverter for inverting the input signal and giving the input inverting signal to the gate of the transistor N2.

【0007】

Transistors P1, P1', N1, N1'are transistors that form a latch circuit that captures the input signal level, and transistors N2, N2' are drive transistors.

【0008】

As shown in the figure, the transistor P1 has a bias power supply V at one end (source or drain)._PPThe other end is connected to one end of the transistor N1, and the other end of the transistor N1 is grounded. Similarly, the transistors P1'and N1'are also the power supply V._PPThey are connected in series between and ground, and their connection points 3 and the gates of transistors P1 and N1 are connected, and the connection points 2 of transistors P1 and N1 are connected to the gates of transistors P1'and N1'.

【0009】

The operation of the circuit of FIG. 5 will be described with reference to the waveform diagram of FIG. Now the input signal is V_CCIf so, then V at the gate of transistor N2'_CCIs applied and the transistor is on, so the potential at point 3 is almost zero. At this time, since the potential at point 3 is applied to the gates of transistors P1 and N1, both transistors are on. The potential at point 2 is almost V_PPIt has become.

【0010】

From this state, when the input signal changes to 0 at time t1, the transistor N2'is turned off and the transistor N2 is turned on, but the transistors P1 and N1 are still on.

【0011】

When the transistor N2 is turned on, the potential at point 2 is forcibly lowered to zero, so that the current flowing through the transistors P1 and N1 is reduced.

【0012】

Instead, since the potential at point 2 is applied to the gates of the transistors P1'and N1', the transistor begins to conduct and the potential at point 3 rises.

【0013】

At time t2, the potential at point 2 goes to zero and transistors P1 and N1 turn off. On the other hand, the transistors P1'and N1' are turned on and the potential at point 3 is V._PPWill be.

【0014】

Furthermore, the input signal is V at time t3._CCThen, the transistor N2'turns on again and tries to forcibly reduce the potential at point 3 to zero. As a result, the current flowing through the transistors P1'and N1'is reduced, and the potential at point 3 is lowered.

【0015】

Instead, the current flowing through transistors P1 and N1 increases, and the potential at point 2 rises. At time t4, the transistors P1'and N1' are completely off and the potential at point 3 becomes zero. On the other hand, the transistors P1 and N1 are completely on and the potential at point 2 is V._PPbecome.

【0016】

After time t5, the same operation as described above for t1 to t4 is repeated. Therefore, the input is from 0 to V_CCWhen changing to, the potential at point 2 is from 0 to V_PP, Turn the transistors Q1 and Q2 on and off, and output 502 to 0 and V._PPYou get an output that varies between.

【0017】

[Problems to be Solved by the Invention]

In the operation of the circuit described above with reference to FIG. 5, since the transistors N2 and N2'are transistors having a large drive capability, their node capacitance is large, and the channel widths of the transistors P1 and P1'are required to secure the charging speed. Must be increased to some extent.

【0018】

For example, the input signal is V_CCConsidering the time when it changes from 0 to 0, the potential at point 1 is from 0 to V._CCTransistor N2 conducts (on) and lowers the potential at point 2. At this time, since the potential from point 3 (near zero) is applied to the gate of P1, P1 is on and the power supply V_PP Transistor P1 Transistor N2 A large through current flows in the ground passage.

【0019】

In addition, the current of P1 increases the time required for the potential of point 2 to drop. This descent time is expressed as between the times t1 and t2 in FIG. 6, and during this descent time, the circuit in FIG. 5 is in a transient state, and the current flowing through the above-mentioned transistors P1 and N2. In addition, there is a current flowing through the transistors P1 and N1 and a current flowing through the transistors P1'and N1', and a large through current flows, so that there is a problem that power consumption increases.

【0020】

In view of the above points, it is an object of the present invention to eliminate a through current at the time of level shift and to provide a level shifter having low power consumption.

【0021】

[Means for solving problems]

The present invention is a power supply V_PPThe first P-type transistor P1'and the first N-type transistor N1' connected in series between the power supply and the ground, the second P-type transistor P1 and the second N-type transistor N1 connected in series between the power supply and the ground, and the first P-type transistor. A connection line connecting the connection point (a) of the transistor P1'and the first N-type transistor N1'to the gate of the second P-type transistor P1 and the gate of the second N-type transistor N1, the second P-type transistor P1 and the above. The connection point (b) of the second N-type transistor N1 is connected to the gate of the first P-type transistor P1'and the gate of the first N-type transistor N1', and is connected between the connection point (a) and the ground. , The third transistor N2 whose gate is connected to the input terminals 101, 301, 401, and the fourth transistor N2 whose gate is connected between the connection point (b) and the ground and whose gate is connected to the output of the input inverting circuit. In the level shifter provided with the above and the output signal is taken out from the connection point (b), the fifth and second P-type transistors P1'and P1 are connected in series with the first and second P-type transistors P1'and P1 to prevent a large through current at the time of level change. In addition to connecting the 6th transistors P2'and P2, the drive capability of the 1st P-type transistor P1'and the 5th transistor P2'is connected in series, and the 2nd P-type transistor P1 and the 6th transistor P2 are connected in series. Provided is a level shifter characterized in that small seventh and eighth transistors P3', P3 are connected in parallel.

【0022】

In the level shifter of the present invention, it is preferable to connect resistors R2'and R2 in series with the seventh and eighth transistors P3'and P3, respectively, or to give resistors to P3'and P3. Further, in the level shifter of the present invention, it is preferable to connect or eliminate the 7th and 8th transistors in series with the MIMO.

【0023】

[Action]

In the level shifter of the present invention, the fifth and sixth transistors P2'and P2 are connected in series with the first and second P-type transistors P1'and P1, respectively, in order to prevent a large through current flowing through those transistors when the level changes. Since they are connected, a low power consumption circuit can be realized without a large current flowing when the input logic level changes and the on / off states of the transistors P1'and P1 change.

【0024】

In addition, the transistor P3'is connected in parallel to the series connection of the transistors P1'and P2', and the transistor P3 is connected in parallel to the series connection of the transistors P1 and P2 so that this transistor is turned on when the level changes. Therefore, the potential of the above-mentioned connection point (a) or (b) can be changed to V in a short time._PPCan be changed from to 0.

【0025】

Since the series connection of transistors P1'and P2'and the series connection of transistors P1 and P2 have a large current drive capability, when both (for example, P1'and P2') are turned on, the above-mentioned connection point (a) or (b) ) Potential from 0 to V in a short time_PPCan be charged up to.

【0026】

[Example]

An example of the level shifter of the present invention will be described with reference to FIGS. 1 and 2.

【0027】

In the circuit of the figure, P1, N1, N2, P1', N1', N2', Q1, Q2 are the same transistors as the above-mentioned transistors with reference to FIG.

【0028】

In the circuit of FIG. 1, the newly added circuit parts are the transistors P3 and P3', the transistor P2 and the delay element D connected to the gate, and the transistor P2'and the delay element D'connected to the gate. .. The circuit of FIG. 1 is made of a semiconductor integrated circuit.

【0029】

At that time, a resistor R, an inverter, a P-type MOS transistor, or the like can be used as the delay element. Here, the W / L of the transistors P3 and P3'(where W is the channel width and L is the channel length) is selected to be smaller than the W / L of the other transistors P1, P2, P1', P2'.

【0030】

Therefore, since the transistors P3 and P3'have a small gate capacitance, they saturate in a short time and the voltage is V in a short time._PPIt works to reduce from to 0.

【0031】

Next, the operation of the circuit of FIG. 1 will be described with reference to FIG. At time t1, the input is V_CCTransistor N2'turns off when it changes from 0 to 0, and transistor N2 has a potential of point 1 from 0 to V._CCIt turns on because it changes to.

【0032】

The potential of point 2 is changed to V by turning on the transistor N2._PPAttempts to lower from to 0. At this time, since the potential at point 4 is still 0, the gate voltage of the transistor P1 is 0, and the transistor can be turned on. The gate potential of transistor P2 is still V_PPThe transistor is off because it remains as it is.

【0033】

Therefore, no current flows in the series circuit of the transistors P1 and P2, which have a large current drive capability. At this time, the power supply V_PPSince the current supply from to point 2 is only through the transistor P3, which has a small drive capacity, point 2 can be V in a short time._PPCan be lowered from to 0.

【0034】

When the potential at point 2 becomes 0, P1'turns on. At this time, the gate potential of P2'is still at 0 due to the action of the delay element, so the transistor P2'is still on, so the current drive capability is large. The potential of point 4 is changed from 0 to V in a short time by the series circuit of transistors P1'and P2'._PPCharge up to.

【0035】

Point 4 is charged up and the potential is V_PPAfter becoming, point 5 is also V via the delay element D'_PPAnd the gate voltage of transistor P2'is V_PPTherefore, the transistor P2'is turned off and the current flowing in the series circuit of the transistors P2'and P1'is zero.

【0036】

At this time, the transistor P3'is turned on because the 0 potential at point 2 is applied to the gate, so the potential at point 4 is V._PPIs kept in. Here, the transistor P3'functions to stabilize the latch operation, and is a transistor having a small W / L value at a level that hinders leakage current, noise, soft error, etc. of each MOS type transistor.

【0037】

Then at time t3 the input is from 0 to V_CCWhen it changes to, the transistor N2'turns on and tries to forcibly reduce the potential at point 4 to zero. At this time, the potential at point 1 becomes 0, so the transistor N2 is turned off.

【0038】

However, the potential at point 2 is still 0, so the gate voltage of transistor P1'is 0, so the transistor is on, but the gate potential of transistor P2'is still V._PPThe transistor is off because it remains.

【0039】

Therefore, no current flows in the series circuit of the transistors P1'and P2', which have a large current drive capability. Instead, the transistor P3'is on, so the power supply V_PPCurrent flows from to point 4, but the transistor P3'has a small drive capability, so the potential at point 4 is V in a short time._PPDescent from to 0.

【0040】

When the potential at point 4 becomes 0, the transistor P1 is turned on. At this time, the gate potential of the transistor P2 is still at 0 due to the action of the delay element, so the transistor P2 is still on. The potential of point 2 is changed from 0 to V in a short time by the series circuit of P1 and P2._PPCharge up to.

【0041】

Point 2 is charged up and the potential is V_PPAfter becoming, point 3 is also V via delay element D_PPAnd the gate voltage of transistor P2 is V_PPTherefore, the transistor P2 is turned off, and the current flowing in the series circuit of the transistors P2 and P1 becomes 0. At this time, the transistor P3 is turned on because the zero potential at point 4 is applied to its gate, and the potential at point 2 is V._PPIs kept in.

【0042】

By the above operation, 0 and V input to input 101_PP0 and V at point 2 for binary signals that vary between_PPA binary signal that changes between appears, and since this signal is applied to the gates of transistors Q1 and Q2, the output terminal 102 has 0 and V depending on the input signal._PPA binary signal that changes between is output.

【0043】

Comparing the circuit of the first embodiment of the present invention shown in FIG. 1 with the conventional circuit shown in FIG. 5, in the conventional circuit (FIG. 5), the potential at point 2 is V._PPWhen lowering from to 0, the potential of point 2 is changed to V while the extraction current by the transistor N2 and the injection current through the MIMO transistor P1 compete with each other._PPSince it was set to 0, a large through current flows, and since it takes time for this current to flow, the fall time has become a problem. However, according to the circuit of the present invention (Fig. 1), the point 2 potential V_PPWhen the voltage is lowered from to 0, no current flows through the series circuit of the transistors P1 and P2, only the current flows through the transistor P3, which has a small drive capacity. Therefore, a low power consumption and high-speed level shifter can be realized.

【0044】

In the circuit of FIG. 1, delay elements D and D'can be replaced by resistors R1 and R1'. Further, the transistors P3 and P3'can be composed of a resistor R2, a transistor P3, a resistor R2'and a transistor P3'. At that time, the transistors P3 and P3'can be made to have resistance.

【0045】

The circuit of the level shifter configured in this way is shown in FIG. Since the circuit operation of this level shifter is basically the same as the operation of the circuit of FIG. 1, detailed description is omitted.

【0046】

Comparing the circuit of FIG. 3 with the circuit of FIG. 1, the positions of the transistors P1 and P2 and the positions of the transistors P1'and P2'are interchanged. Since the positions of P1, P1'and P2, P2'can be exchanged in this way, it is possible to arrange them conveniently according to the circuit pattern when forming the semiconductor integrated circuit.

【0047】

In addition, the current drive capability of the transistors P3 and P3'can be at a level that can suppress noise and leakage current, so when forming a device that has a TFT'(thin film transistor) process, it should be formed with the TFT of MIMOS. Can be done.

【0048】

Next, still another embodiment of the present invention will be described with reference to FIG. In the figure, the circuits of P1, P2, N1, N2, P1 , P2 , N1 , N2 and the inverter 403 are shown in FIG. The description is omitted.

【0049】

The difference between the circuit of Fig. 4 and the circuit of Fig. 1 is that there are no transistors P3 and P3', and the potential of point 2 is inverter I.₁, I₂, I₃It is taken out from the output terminal 402 through the series circuit of, and the inverter I instead of the delay elements D, D'(Fig. 1).₂Output and I₃The output of is used.

【0050】

In this way, for example, in a level shifter that converts 1V (volt) logic to 3V logic, 3V logic can generally be used, so the output of the next-stage logic can be used instead of the delay elements D and D'.

【0051】

[Effect of the invention]

The level shifter of the present invention is useful for reducing power consumption because a large through current at the time of level shift can be eliminated by the above-described configuration.

【0052】

In particular, the program voltage of the flash memory is charged up in the chip and V_PPSince (about 12 to 20V) is produced, the effect is great considering the efficiency of the pump.

【0053】

Further, since the circuit state switching (latch) is latched only by the charging or discharging current of the transistor, high-speed operation can be performed.

【0054】

V on the input side_CC1Since the drive from the system is not due to the ratio circuit, V_CC> V_th(V_CCSystem bias power supply voltage V_CCIs the threshold V_thIf it is larger than), the circuit works. Therefore, it is possible to shift the level from the logical level at which CMOS operates.

【0055】

From the above, the level shifter of the present invention is highly effective in the future system-on-chip era in which circuit blocks of multiple power supplies are mixed.

[Simple explanation of drawings]

[Figure 1]

It is a circuit diagram of one example of the level shifter of this invention.

[Figure 2]

It is an operation waveform diagram of the circuit of FIG.

[Fig. 3]

It is a circuit diagram of another example of the level shifter of this invention.

[Fig. 4]

It is a circuit diagram of still another example of the level shifter of the present invention.

[Fig. 5]

It is a circuit diagram of a conventional level shifter.

[Fig. 6]

It is an operation waveform diagram of the circuit of FIG.

[Explanation of symbols]

101 input terminal 102 Output terminal 104 Bias power terminal 103 Inverter N2, N2'drive transistor P1 ~ P3, P1'~ P3' P-type transistor N1, N1 N-type transistor Q1, Q2 output stage transistor