Semiconductor switch
Abstract
(57) The summary purpose book invention realizes low insertion loss and the semiconductor switch of low distortion, though it is small size and a low-voltage drive. Composition The pinch off voltage of the 1st field effect transistor stage connected to a signal passage in series is set as low potential to the pinch off voltage of the 2nd field effect transistor stage to which it is connected between a signal passage and an earth potential. The 1st and 2nd field effect transistor stages are kept from operating by the same operating characteristic by this. As a result, ON operation only of the 1st field effect transistor connected to the signal passage in series can be carried out, without making the 2nd field effect transistor connected between the signal passage and the earth potential generate leakage power. Thereby, insertion loss of a semiconductor switch and distortion can be made small much more as compared with the former.
Term
No projected expiry on record.
- Priority and filed
- Published
- Today
11 claims: 7 independent, 4 dependent
- 1[Claims] 1. A first field effect transistor stage connected in series with a signal passage. It is characterized by having a second field-effect transistor stage connected between the signal path and the ground potential and having a pinch-off voltage set to a higher potential than the pinch-off voltage in the first field-effect transistor stage. Semiconductor switch. 【特許請求の範囲】 【請求項1】信号通路に対して直列接続された第1の電界効果トランジスタ段と、 上記信号通路と接地電位間に接続され、ピンチオフ電圧が上記第1の電界効果トランジスタ段におけるピンチオフ電圧に比して高い電位に設定されてなる第2の電界効果トランジスタ段とを具えることを特徴とする半導体スイツチ。
- 2A first field effect transistor stage connected in series to a first signal passage having a transmission path between a first terminal and a second terminal. A second field-effect transistor stage connected between the first signal passage and the ground potential and having a pinch-off voltage set to a higher potential than the pinch-off voltage in the first field-effect transistor stage. The pinch-off voltage is set to a higher potential than the pinch-off voltage in the first field-effect transistor stage, which is connected in series to the second signal path whose reception path is between the second terminal and the third terminal. The third field effect transistor stage, which is made up of A semiconductor switch characterized by including a fourth field effect transistor stage connected between the second signal passage and the ground potential. 【請求項2】第1の端子及び第2の端子間を送信路とする第1の信号通路に対して直列接続された第1の電界効果トランジスタ段と、 上記第1の信号通路と接地電位間に接続され、ピンチオフ電圧が上記第1の電界効果トランジスタ段におけるピンチオフ電圧に比して高い電位に設定されてなる第2の電界効果トランジスタ段と、 上記第2の端子及び第3の端子間を受信路とする第2の信号通路に対して直列接続され、ピンチオフ電圧が上記第1の電界効果トランジスタ段におけるピンチオフ電圧に比して高い電位に設定されてなる第3の電界効果トランジスタ段と、 上記第2の信号通路と接地電位間に接続された第4の電界効果トランジスタ段とを具えることを特徴とする半導体スイツチ。
- 3A first field-effect transistor stage connected in series with a signal passage. It is equipped with a second field effect transistor stage connected between the signal path and the ground potential. Pinch-off voltage V of the first field effect transistor stageP1Is the current amplitude I of the high frequency signal passing between the drain and source of the field effect transistor.RFSaturation current I flowing between and drain and sourceDSS Pinch-off voltage V whenPIDSS For the value of [Number 1]And the pinch-off voltage V of the second field effect transistor stage aboveP2Is the voltage amplitude V of the high frequency signal passing between the drain and source of the field effect transistor.RFAnd off-bias voltage VOFF OFF Given by [Number 2]A semiconductor switch that is characterized by satisfying. 【請求項3】信号通路に対して直列接続された第1の電界効果トランジスタ段と、 上記信号通路と接地電位間に接続された第2の電界効果トランジスタ段とを具え、 上記第1の電界効果トランジスタ段のピンチオフ電圧VP1は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電流振幅IRFとドレイン及びソース間を流れる飽和電流IDSS とが等しくなるときのピンチオフ電圧VPIDSS の値に対して、次式 【数1】 を満足し、かつ上記第2の電界効果トランジスタ段のピンチオフ電圧VP2は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電圧振幅VRFとオフバイアス電圧VOFF とによつて与えられる次式 【数2】 を満足することを特徴とする半導体スイツチ。
- 4A first field effect transistor stage connected in series to a first signal passage having a transmission path between a first terminal and a second terminal. A second field-effect transistor stage connected between the first signal path and the ground potential, A third field-effect transistor stage connected in series to a second signal passage whose reception path is between the second terminal and the third terminal. It is equipped with a fourth field effect transistor stage connected between the second signal path and the ground potential. Pinch-off voltage V of the first field effect transistor stageP1Is the current amplitude I of the high frequency signal passing between the drain and source of the field effect transistor.RFSaturation current I flowing between and drain and sourceDSS Pinch-off voltage V whenPIDSS For the value of [Number 3]And the pinch-off voltage V of the above 2nd and 3rd field effect transistor stagesP2Is the voltage amplitude V of the high frequency signal passing between the drain and source of the field effect transistor.RFAnd off-bias voltage VOFF OFF Given by [Number 4]A semiconductor switch that is characterized by satisfying. 【請求項4】第1の端子及び第2の端子間を送信路とする第1の信号通路に対して直列接続された第1の電界効果トランジスタ段と、 上記第1の信号通路と接地電位間に接続された第2の電界効果トランジスタ段と、 上記第2の端子及び第3の端子間を受信路とする第2の信号通路に対して直列接続された第3の電界効果トランジスタ段と、 上記第2の信号通路と接地電位間に接続された第4の電界効果トランジスタ段とを具え、 上記第1の電界効果トランジスタ段のピンチオフ電圧VP1は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電流振幅IRFとドレイン及びソース間を流れる飽和電流IDSS とが等しくなるときのピンチオフ電圧VPIDSS の値に対して、次式 【数3】 を満足し、かつ上記第2及び第3の電界効果トランジスタ段のピンチオフ電圧VP2は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電圧振幅VRFとオフバイアス電圧VOFF とによつて与えられる次式 【数4】 を満足することを特徴とする半導体スイツチ。
- 5A first field-effect transistor stage connected in series with a signal passage. It is equipped with a second field effect transistor stage connected between the signal path and the ground potential. Pinch-off voltage V of the first field effect transistor stageP1Is the current amplitude I of the high frequency signal passing between the drain and source of the field effect transistor.RFAnd the gate width Wg and the on-bias voltage VONGiven using [Number 5]And the pinch-off voltage V of the second field effect transistor stage aboveP2Is the voltage amplitude V of the high frequency signal passing between the drain and source of the field effect transistor.RFAnd off-bias voltage VOFF OFF Given by [Number 6]A semiconductor switch that is characterized by satisfying. 【請求項5】信号通路に対して直列接続された第1の電界効果トランジスタ段と、 上記信号通路と接地電位間に接続された第2の電界効果トランジスタ段とを具え、 上記第1の電界効果トランジスタ段のピンチオフ電圧VP1は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電流振幅IRFと、ゲート幅Wg と、オンバイアス電圧VONを用いて与えられる次式 【数5】 を満足し、かつ上記第2の電界効果トランジスタ段のピンチオフ電圧VP2は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電圧振幅VRFとオフバイアス電圧VOFF とによつて与えられる次式 【数6】 を満足することを特徴とする半導体スイツチ。
- 6A first field effect transistor stage connected in series to a first signal passage having a transmission path between the first terminal and the second terminal. A second field-effect transistor stage connected between the first signal path and the ground potential, A third field-effect transistor stage connected in series to a second signal passage whose reception path is between the second terminal and the third terminal. It is equipped with a fourth field effect transistor stage connected between the second signal path and the ground potential. Pinch-off voltage V of the first field effect transistor stageP1Is the current amplitude I of the high frequency signal passing between the drain and source of the field effect transistor.RFAnd the gate width Wg and the on-bias voltage VONGiven using [Number 7]And the pinch-off voltage V of the above 2nd and 3rd field effect transistor stagesP2Is the voltage amplitude V of the high frequency signal passing between the drain and source of the field effect transistor.RFAnd off-bias voltage VOFF OFF Given by [Number 8]A semiconductor switch that is characterized by satisfying. 【請求項6】第1の端子及び第2の端子間を送信路とする第1の信号通路に対して直列接続された第1の電界効果トランジスタ段と、 上記第1の信号通路と接地電位間に接続された第2の電界効果トランジスタ段と、 上記第2の端子及び第3の端子間を受信路とする第2の信号通路に対して直列接続された第3の電界効果トランジスタ段と、 上記第2の信号通路と接地電位間に接続された第4の電界効果トランジスタ段とを具え、 上記第1の電界効果トランジスタ段のピンチオフ電圧VP1は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電流振幅IRFと、ゲート幅Wg と、オンバイアス電圧VONを用いて与えられる次式 【数7】 を満足し、かつ上記第2及び第3の電界効果トランジスタ段のピンチオフ電圧VP2は、電界効果トランジスタのドレイン及びソース間を通過する高周波信号の電圧振幅VRFとオフバイアス電圧VOFF とによつて与えられる次式 【数8】 を満足することを特徴とする半導体スイツチ。
- 11The first, second, third, fourth, and fifth claims, wherein the field effect transistor stage is formed of a metal-semiconductor field effect transistor. Item 6. The semiconductor switch according to item 6. 【請求項11】上記電界効果トランジスタ段は、金属-半導体電界効果トランジスタによつて形成されることを特徴とする請求項1、請求項2、請求項3、請求項4、請求項5又は請求項6に記載の半導体スイツチ。
Independent claims7
160 paragraphs, as filed
Description: TECHNICAL FIELD [Detailed description of the invention]
【0001】
[table of contents]
The present invention will be described in the following order. Industrial application fields Conventional technology (Fig. 11) Problems to be solved by the invention Means for solving problems (Fig. 2 and Fig. 7) Action (Fig. 3 and Fig. 4) Examples (Figs. 1 to 10) (1) Principle of distortion generation (Fig. 1) (2) Configuration of switch circuit (Figs. 2 to 6) (3) SPDT switch circuit (Fig. 7) (4) Pinch-off voltage V<sub>P </sub>Settings (Figs. 8 to 10) (4-1) Saturation current I<sub>DSS </sub>Pinch-off voltage V obtained from<sub>P </sub>Settings (Figs. 8 to 10) (4-2) Pinch-off voltage V using gate width Wg<sub>P </sub>Settings (Figs. 8 to 10) (5) Other Examples Effect of the invention [0002]
[Industrial application field]
The present invention relates to a semiconductor switch, and can be applied to, for example, an antenna switch of a digital cellular telephone.
【0003】
[Conventional technology]
Currently, the mobile communication business such as car phones and mobile phones is developing significantly. Along with this, the shortage of communication lines is becoming serious in urban areas. For this reason, various mobile communication systems are about to be launched in each country. Many of these communication systems use the quasi-microwave band on the higher frequency side than the current mobile communication systems.
【0004】
In mobile terminals in these communication systems, semiconductor field effect transistors (FETs) are often used to process quasi-microwave signals. Especially when using the quasi-microwave band, MMIC (Monolithic Microwave IC) using gallium arsenide / field effect transistor that can realize various conditions required for mobile terminals (that is, small size, low voltage drive and low power consumption). Development is becoming important.
【0005】
One of the important key devices among microwave signal processing devices using these gallium arsenide / field effect transistors is the SPDT (Single Pole Dual Through) switch. This SPDT switch is shown in FIG. The SPDT switch 1 is composed of a transmission switch 2 and a reception switch 3. The same pinch-off voltage V is used for the shunt FETs 2A and 3A and the series FETs 2B and 3B that make up the two switches 2 and 3, respectively.<sub>P </sub>A field effect transistor with (= 0.5 [V]) is used.
【0006】
This transmitting side switch 2 switches whether to transmit the high frequency signal given from the transmitting circuit to the terminal P1 to the antenna terminal P2, and the other receiving side switch 3 transmits the high frequency signal received by the antenna to the antenna terminal P2. Is switched between transmitting to the receiving circuit via terminal P3. The power consumption of the SPDT (Single Pole Dual Through) switch configured by the field effect transistors in this way is essentially very small.
【0007】
[Problems to be Solved by the Invention]
However, in the case of a mobile communication mobile terminal, the insertion loss of the switch portion (that is, the shunt FET 2A and the series FET 2B) connecting the transmission terminal and the antenna in this way greatly affects the power consumption of the entire mobile terminal. Therefore, it is necessary to minimize the insertion loss of the receiving side switch 2. Also, since the transmitted microwave power can be quite large (for example, about 10 W), it is used for mobile communication mobile terminals that the linearity of the transmission characteristic of the receiving side switch 2 is compensated (that is, low distortion). It is especially important for the SPDT switch to be used.
【0008】
For this reason, a method of reducing distortion by connecting two-stage shunt FET2A connected to the shunt portion in series with respect to the signal path or by using a dual gate FET has been proposed.
【0009】
However, in the case of the former method (P.Bemkopf, M.Schindler, A.Bertrand, "A HIGH POWER K / Ka-BAND MONOLITHIC T / R SWITCH", IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium Digest, 1991, pp. 15-18), there are adverse effects such as an increase in device size due to an increase in the number of FETs and deterioration of characteristics due to an increase in the loss of the FET part, and the control voltage is also large at 0 / -10 [V], which is applicable to mobile communication terminals. It was inappropriate for this.
【0010】
Similarly, in the case of the latter method (MJ Schindler, TEKazior, "A High Power 2-18 GHz T / R Switch", 1990 IEEE MTT-S Digest, pp.453-456), the point of loss compared to the former case. On the other hand, there was a problem that the linearity was inferior. In addition, the insertion loss is increased compared to the case of single-gate FET, and the control voltage is 0 / -14 [V], -10 [V], -7 [V], which means that it is suitable for low voltage driving. I can't say.
【0011】
The present invention has been made in consideration of the above points, and an object of the present invention is to propose a semiconductor switch that can simultaneously realize both characteristics of low insertion loss and low distortion while being compact and low voltage drive. is there.
【0012】
[Means for solving problems]
In order to solve this problem, in the present invention, the first field effect transistor stage 10B connected in series to the signal passage (between P11 and P12) is connected to the signal passage (between P11 and P12) and the ground potential. And pinch-off voltage V<sub>PA</sub>Is the pinch-off voltage V in the first field effect transistor stage 10B.<sub>PB</sub>A semiconductor switch is formed by providing a second field effect transistor stage 10A which is set to a higher potential than the above.
【0013】
Further, in the present invention, the first field effect transistor stage 21B connected in series to the first signal passage having the transmission path between the first terminal P21 and the second terminal P22, and the first signal passage. Connected between and the ground potential, pinch-off voltage V<sub>PA</sub>Is the pinch-off voltage V in the first field effect transistor stage 21B.<sub>PB</sub>The second field effect transistor stage 21A, which is set to a higher potential than the above, is connected in series to the second signal passage whose reception path is between the second terminal P22 and the third terminal P23. Pinch-off voltage V<sub>PB</sub>Is the pinch-off voltage V in the first field effect transistor stage 21B.<sub>PB</sub>A semiconductor switch is provided by providing a third field-effect transistor stage 22B, which is set to a higher potential than the above, and a fourth field-effect transistor stage 22A, which is connected between the second signal path and the ground potential. Try to form.
【0014】
[Action]
Pinch-off voltage V of first field effect transistor stage 10B connected in series with the signal path<sub>PB</sub>The pinch-off voltage V of the second field effect transistor stage 10A connected between the signal path and the ground potential<sub>PA</sub>The potential is set to a lower potential so that the first and second field effect transistor stages 10B and 10A do not operate due to the same operating characteristics. As a result, only the first field-effect transistor stage 10B connected in series with the signal path is turned on without generating leakage power in the second field-effect transistor stage 10A connected between the signal path and the ground potential. be able to. As a result, the insertion loss due to the first field-effect transistor stages 10B can be reduced, and the distortion caused by the first and second field-effect transistor stages 10B and 10A can be further reduced.
【0015】
[Example]
An embodiment of the present invention will be described in detail below with reference to the drawings.
【0016】
(1) Principle of distortion generation First, the distortion generation mechanism of the switch circuit using FET will be described. There are two types of distortion: distortion that occurs when the FET is in the on state and distortion that occurs when the FET is in the off state.
【0017】
The former distortion is distortion due to current limitation. This is because the high frequency signal current that flows when the high frequency signal passes between the drain and source of the FET is the saturation current I.<sub>DSS </sub>Due to the inability to flow more, the saturation current I<sub>DSS </sub>The part where the current with the amplitude exceeding the above flows becomes distortion.
【0018】
On the other hand, the latter distortion is a distortion caused by the flow of a current that should not flow originally. This is because the high frequency signal voltage applied between the drain and source of the FET is the pinch-off voltage V.<sub>P </sub>Or breakdown voltage V<sub>BR</sub>This is due to the leakage power generated when the voltage exceeds V.<sub>P </sub>Also V<sub>BR</sub>The part where the voltage with the amplitude exceeding the above is applied (the shaded part in FIG. 1) is the distortion.
【0019】
Of these two types of distortion, the problem with switch circuits of communication terminals that are driven at low voltage, such as digital cellular telephones, is that the high-frequency signal voltage is the pinch-off voltage V.<sub>P </sub>It is a distortion when it exceeds. That is, the pinch-off voltage V<sub>P </sub>And DC gate bias V<sub>BIASS </sub>This is the case where the amplitude of the high frequency signal voltage is larger than the difference between. In this case, a leak current flows through the shunt FET, which should be in a non-conducting state, and distortion occurs in the signal current flowing through the antenna terminal P2.
【0020】
(2) Configuration of switch circuit In FIG. 2, 10 shows the switch circuit 10 used in this embodiment. This switch circuit 10 compares the pinch-off voltage VPB of the series FET 10B connected in series (ie, in series) to the signal line to the pinch-off voltage VPA of the switch FET 10A connected between the signal line and the ground potential (ie, in the state). It is characterized by setting it low.
【0021】
In the case of this embodiment, the former pinch-off voltage V<sub>PB</sub>Is set to -1.0 [V], and the latter pinch-off voltage V<sub>PA</sub>Is set to 0.5 [V]. Pinch-off voltage V like this<sub>PB</sub>And V<sub>PA</sub>By providing a potential difference between the two, it is possible to reduce the insertion loss and the distortion at the same time.
【0022】
The operating states of the FETs 10A and 10B at this time will be described with reference to FIG. When the switch of the switch circuit 10 is turned on (that is, when the series FET 10B is in the on state and the switch FET 10A is in the off state), the resistance between the drain and the source of the series FET 10B in the on state is the pinch-off voltage V.<sub>PB</sub>Is set low, so it is small. As a result, a relatively large signal current I from terminal P11 to terminal P12 (or from terminal P12 to terminal P11)<sub>dB</sub>Can flow, and the insertion loss can be kept small.
【0023】
On the other hand, the pinch-off voltage V of the series FET10A in the off state<sub>PA</sub>Is set high, so the DC gate bias voltage V<sub>BIASS </sub>(V<sub>OFF OFF </sub>) And pinch-off voltage V<sub>PA</sub>The potential difference with is set to a large value. As a result, even when a high-power high-frequency signal is input, the high-frequency signal voltage amplitude is the pinch-off voltage V of the FET.<sub>PA</sub>It does not exceed the above, and the distortion can be suppressed to a very small level.
【0024】
Next, the simulation results of the insertion loss characteristics when this switch circuit 10 is used are shown in FIGS. 4 to 6. This simulation uses the actually measured GaAs type JFET (Junction FET) data. Here, FIG. 4 shows the switch circuit 10 of the embodiment (that is, the pinch-off voltage V of the series FET 10B).<sub>PB</sub>-1.0 [V], pinch-off voltage V of shunt FET10A<sub>PA</sub>The simulation result of 0.5 [V]) is shown, and FIGS. 5 and 6 show the simulation result of the conventional switch circuit 1, respectively.
【0025】
Here, Fig. 5 shows the pinch-off voltage V.<sub>PA</sub>And V<sub>PB</sub>The simulation results are shown when both are 0.5 [V], and Fig. 6 shows the pinch-off voltage V.<sub>PA</sub>And V<sub>PB</sub>Shows the simulation results when both are -1.0 [V]. The width of all FET gates shall be 1 [mm], and the gate length shall be 0.5 [μm]. As can be seen from the figure, in the case of the switch circuit 10 of the embodiment, the insertion loss is small and the decrease in the characteristic curve is also small.
【0026】
For example, comparing the insertion loss at 1.5 [GHz], the switch circuit 10 of the embodiment has a pinch-off voltage V.<sub>PA</sub>And V<sub>PB</sub>It can be seen that it is about 0.15 [dB] superior to the case of the switch circuit 1 in which both are set to 0.5 [V]. On the other hand, in terms of insertion loss, the switch circuit 10 of the embodiment has a pinch-off voltage V.<sub>PA</sub>And V<sub>PB</sub>Although it is almost the same as the case of the switch circuit 1 in which both are set to -1.0 [V], the embodiment is still superior in terms of isolation.
【0027】
Also think about distortion. When the switch of the switch circuit is on, the gate width of the series FET10B in the on state is sufficiently large, so that distortion due to current limitation can be ignored. Therefore, the strain strength due to the voltage limitation generated in the shant FET 10A in the off state determines the strain strength of the entire switch. As mentioned earlier, distortion hardly occurs when the power supply voltage is relatively small.
【0028】
In fact, when the FETs constituting the switch circuit 10 are driven by a control voltage of 1 / -2 [V], distortion can be suppressed sufficiently small when the high frequency signal voltage is smaller than the difference between the DC gate bias and the pinch-off voltage. If the resistance value of the signal line to which the switch circuit 10 is connected is 50 [Ω], and the threshold voltage and pinch-off voltage of the FETs that make up the switch circuit 10 are equal, distortion can be suppressed to a minimum. High-frequency power can take a large value of 64.5 [mW]. On the other hand, in terms of insertion loss, the conventional switch circuit 1 (pinch-off voltage V of two FETs 1B and 1A), which is not much different from the switch circuit 10 of the embodiment.<sub>PB</sub>And V<sub>PA</sub>However, the maximum high-frequency power of -1.0 [V] is about 10 [mW].
【0029】
As described above, it can be seen that the switch circuit 10 is compact because it is composed of two FETs having a difference in pinch-off voltage, and is excellent in distortion characteristics and insertion loss. As a result, the gate width of the series FET 10B among the series FET 10B and the shant FET 10A can be reduced. Alternatively, the withstand voltage of the shant FET 10A can be reduced.
【0030】
(3) SPDT switch circuit Next, a case where the switch circuit 10 is applied to the SPDT switch circuit used as the antenna switch of the digital cellular telephone will be described. In FIG. 7, 20 shows an SPDT switch circuit using the switch circuit 10 as a whole.
【0031】
In this way, even when used as the SPDT switch circuit 20, the pinch-off voltage V of the series FETs 21B and 22B constituting the receiving side switch 21 and the transmitting side switch 22<sub>PB</sub>Pinch-off voltage V of the shunt FET 21A that constitutes the receiving side switch 21<sub>VA</sub>Set higher than the potential of. That is, the pinch-off voltage V of the series FETs 21B and 22B<sub>PB</sub>Is set to 0.5 [V], and the pinch-off voltage V of the shunt FET21A<sub>PA</sub>Is set to -1.0 [V].
【0032】
By the way, the pinch-off voltage V of the shunt FET 22A that constitutes the receiving side switch 22<sub>PA</sub>Is the pinch-off voltage V of the series FET22B<sub>PB</sub>It may be set to the same voltage as (that is, it may be set to 0.5 [V]), and the pinch-off voltage V of the series FET is similar to that of the shunt FET 21A constituting the transmitting side switch 21.<sub>PB</sub>The potential may be set lower than that of.
【0033】
The switching operation of this SPDT switch circuit 20 will be described. First, a case where a high-frequency signal modulated by an audio signal is transmitted from an antenna will be described. In this case, a high potential is applied to the gate of the series FET 21B constituting the transmission side switch 21 to control it in the on state, and a low potential is applied to the gate of the shear FET 21A to control it to the off state. At the same time, a low potential is applied to the gate of the series FET 22B constituting the receiving side switch 22 to control it in the off state, and a high potential is applied to the switch FET 22A to control it to the on state. As a result, the circuit on the receiving side becomes high impedance, and the high frequency signal transmitted from the transmitting circuit to the signal passage is transmitted to the antenna terminal side.
【0034】
Next, a case where the audio signal is demodulated from the high frequency signal received by the antenna will be described. In this case, contrary to the case of transmission, the series FET 22B of the receiving side switch 22 is controlled to be in the on state, and the screen FET 22A is controlled to be in the off state. At the same time, the series FET 21B of the transmission side switch 21 is controlled to the off state, and the switch FET 21A is controlled to the on state. As a result, the circuit on the transmitting side becomes high impedance, and the high frequency signal input from the antenna terminal is transmitted to the receiving circuit via the signal passage.
【0035】
In this way, since the SPDT switch circuit 20 is configured with the switch circuit 10 as the basic element, it is possible to realize low distortion, low voltage drive, and low insertion loss operating characteristics in spite of its small size, as in the case of the switch circuit 10. it can.
【0036】
(4) Pinch-off voltage V<sub>P </sub>settings of Here, the pinch-off voltage V of the series FETs 10B, 21B and 22B constituting the switch circuit 10 and the SPDT circuit 20 described above<sub>PB</sub>And pinch-off voltage V for shunt FETs 10A, 21A and 22A<sub>PA</sub>The setting method of is explained. Pinch-off voltage V<sub>P </sub>The setting method is the saturation current I flowing between the drain and source of the FET.<sub>DSS </sub>There is a setting method based on the above and a setting method based on the gate width Wg of the FET.
【0037】
(4-1) Saturation current I<sub>DSS </sub>Pinch-off voltage V obtained from<sub>P </sub>settings of First, for the switch circuit 10, pinch-off voltage V<sub>P </sub>The setting method of is explained. Pinch-off voltage V of series FET 10B constituting switch circuit 10<sub>PB</sub>And the pinch-off voltage V of the shunt FET10A<sub>PA</sub>Are the following equations [Number 9]
<img file="JPH07106937A_D0001.tif" />[Number 10]
<img file="JPH07106937A_D0002.tif" />It may be set to satisfy.
【0038】
By the way, V in Eq. (9)<sub>PIDSS </sub>Is the current amplitude I of the high frequency signal passing between the drain and the source<sub>RF</sub>And drain-source saturation current I<sub>DSS </sub>Is equal to (I<sub>RF</sub>= I<sub>DSS </sub>) When the pinch-off voltage. Also, V in equation (10)<sub>RF</sub>Is the voltage amplitude of the high frequency signal passing between the drain and source, V<sub>OFF OFF </sub>Is the off-bias voltage.
【0039】
Next, for the SPDT switch circuit 20, pinch-off voltage V<sub>P </sub>The setting method of is explained. In this case, the pinch-off voltage V of the series FET 21B that constitutes the transmitting side switch 21<sub>PB</sub>Is set based on Eq. (1), and the pinch-off voltage V of the switch FET 21A that constitutes the transmitting side switch 21 and the series FET 22B that constitutes the receiving side switch 22.<sub>PA</sub>And V<sub>PB</sub>Should be set based on Eq. (10).
【0040】
This is due to the following reasons. Generally FET saturation current I<sub>DSS </sub>Is the maximum value of the direct current that can be passed between the drain and the source at a certain gate bias. Also, when a high frequency signal is input between the drain and source, the current value of the high frequency signal is I.<sub>DSS </sub>Cannot be crossed. Therefore, the saturation current I<sub>DSS </sub>When a high-frequency signal having the above current amplitude is input between the drain and the source of the FET, a part of the high-frequency signal cannot be transmitted, resulting in large distortion. Therefore, the conditions for suppressing distortion with respect to high-frequency current are as follows. [Number 11]
<img file="JPH07106937A_D0003.tif" />Will be. From this equation, the condition of equation (9) can be obtained.
【0041】
Let me give you an actual example. Figure 8 shows the saturation current I of a GaAs type JFET with a gate width of 1 [mm].<sub>DSS </sub>It is a pinch-off voltage-dependent characteristic. Looking at this figure, the saturation current I<sub>DSS </sub>Is a pinch-off voltage V<sub>P </sub>It can be seen that the change is almost linear. This generally results in a saturation current I<sub>DSS </sub>Is [Number 12]
<img file="JPH07106937A_D0004.tif" />Can be expressed by. Here, A and B are device-specific constants, and Wg is the gate width of the FET.
【0042】
FIG. 9 shows the input voltage dependence of the third-order high-frequency distortion that occurs when a high-frequency signal passes through the on-state (Vg = 1 [V]) FET in the GaAs type JFET. As can be seen from this figure, the saturation current I<sub>DSS </sub>When a high-frequency signal with a current amplitude equal to the magnitude of is input, a magnitude of about -46 [dBm] is a sufficiently small level of distortion for a switch. Therefore, it can be said that the distortion can be suppressed sufficiently small when a high frequency signal having an amplitude equal to or less than the saturation current is input. That is, the condition for suppressing the distortion generated from the FET in the on state to be small is given by Eq. (11).
【0043】
Substituting Eq. (12) into Eq. (11), pinch-off voltage V<sub>P </sub>To summarize, [Number 13]
<img file="JPH07106937A_D0005.tif" />Will be. On the contrary, if the equation (13) is satisfied, the distortion generated from the FET in the on state can be suppressed sufficiently small. The condition of Eq. (13) is considered to be a modification of Eq. (9) when Eq. (12) is assumed.
【0044】
Next, consider the distortion generated by the FET in the off state. Figure 10 shows the input voltage dependence of the third-order high-frequency distortion generated by the FET in the off state. Looking at this figure, it can be seen that the distortion increases rapidly at a certain input voltage. High frequency voltage V between drain and source of FET in off state<sub>RF</sub>When is applied, the high frequency voltage V is applied between the drain and gate of the FET and between the gate and source.<sub>RF</sub>Half voltage (V<sub>RF</sub>/ 2) will be applied. As a result, this voltage (V)<sub>RF</sub>/ 2) is superimposed on the DC bias Vg (DC) in the off state.
【0045】
This high frequency voltage V<sub>RF</sub>The gate bias on which DC bias Vg (DC) is superimposed is the pinch-off voltage V.<sub>P </sub>When the above is achieved, the FET is no longer in the pinch-off state, and leakage power is generated between the drain and the source. This causes a large strain and is the cause of the rapid increase in the strain in FIG. Also, from this figure, in the case of an input of power or less that causes a sudden increase in distortion, the intercept point of the third harmonic distortion is calculated to be about 50 [dBm], so the input power is less than the power that causes a sudden increase in distortion. In the case of, it can be said that the distortion can be suppressed sufficiently small. This condition is nothing but Eq. (10).
【0046】
If the switch circuit 10 is configured so as to satisfy this condition, the distortion generated when the switch circuit 10 is turned on (that is, when the series FET 10B is turned on and the switch FET 10A is turned off) (the distortion generated in the series FET 10B) It can be seen that the sum of the distortion generated in the front FET 10A) can be suppressed sufficiently small.
【0047】
(4-2) Pinch-off voltage V using gate width Wg<sub>P </sub>settings of Next, for the switch circuit 10, pinch-off voltage V<sub>P </sub>The setting method of is explained. Pinch-off voltage V of series FET 10B constituting switch circuit 10<sub>PB</sub>And the pinch-off voltage V of the shunt FET10A<sub>PA</sub>Are the following equations [Number 14]
<img file="JPH07106937A_D0006.tif" />[Number 15]
<img file="JPH07106937A_D0007.tif" />It may be set to satisfy. Here, Eq. (15) is the same as Eq. (10). By the way, I in Eq. (6)<sub>RF</sub>Is the current amplitude (mA) of the high frequency signal passing between the drain and source, and Wg is the gate width (mm). Also V<sub>ON</sub>Is the on-bias voltage.
【0048】
The same setting may be performed for the SPDT switch circuit 20. That is, the pinch-off voltage V of the series FET 21B constituting the transmitting side switch 21<sub>PB</sub>Is set based on Eq. (6), and the pinch-off voltage V of the switch FET 21A that constitutes the transmitting side switch 21 and the series FET 22B that constitutes the receiving side switch 22.<sub>PA</sub>And V<sub>PB</sub>Should be set based on Eq. (15).
【0049】
This is due to the following reasons. Saturation current I of a GaAs type JFET with a gate width Wg of 1 [mm]<sub>DSS </sub>Saturation current I, as can be seen from Figure 8 showing the pinch-off voltage dependence of<sub>DSS </sub>Is a pinch-off voltage V<sub>P </sub>It changes almost linearly with respect to the saturation current I in general.<sub>DSS </sub>Is proportional to the gate width Wg and Vg -V<sub>P </sub>Is proportional to. Considering this, the saturation current I<sub>DSS </sub>Is [Number 16]
<img file="JPH07106937A_D0008.tif" />It can be expressed as.
【0050】
In addition, as can be seen from FIG. 9, which shows the input power-dependent characteristics of the third-order high-frequency strain generated when the high-frequency signal passes through the on-state (Vg = 1 [V]) FET, the saturation current I<sub>DSS </sub>It can be seen that when a high-frequency signal with a current amplitude equal to the magnitude of is input, a third harmonic distortion of about -46 [dBm] is generated. This magnitude of -46 [dBm] is a sufficiently small level of distortion for a switch. Therefore, it can be said that the distortion can be suppressed sufficiently small when a high frequency signal having an amplitude equal to or less than the saturation current is input. That is, the condition for suppressing the distortion generated from the FET in the on state is as follows. [Number 17]
<img file="JPH07106937A_D0009.tif" />Will be.
【0051】
Substituting Eq. (16) into Eq. (17), pinch-off voltage V<sub>P </sub>To summarize, the opposite of Eq. (6). On the contrary, if the equation (16) is satisfied, the distortion generated from the FET in the on state can be suppressed sufficiently small. Since the distortion generated from the FET in the off state is the same as that described in the previous section, the description thereof will be omitted.
【0052】
In any case, if the switch circuit 10 is configured so as to satisfy these conditions, the distortion (series FET10B) that occurs when the switch of the switch circuit 10 is turned on (that is, when the series FET10B is turned on and the switch FET10A is turned off). The sum of the distortion generated in the shunt FET10A and the distortion generated in the shear FET 10A) can be suppressed sufficiently small.
【0053】
(5) Other Examples In the above embodiment, in both the switch circuit 10 and the SPDT switch circuit 20, the FET at the position of the switch and the FET at the position of the series with respect to the signal line are each configured by a single-gate FET. However, the present invention is not limited to this, and can be widely applied when configured by a dual gate FET or a FET having three or more gates.
【0054】
Further, in the above-described embodiment, in the case of both the switch circuit 10 and the SPDT switch circuit 20, one stage of FET is connected at the position of the signal line and one stage of FET is connected at the position of the series. As described above, the present invention is not limited to this, and a plurality of stages of FETs may be connected to each of them. In this case, the distortion characteristics can be further improved as compared with the case where each is configured by connecting one stage.
【0055】
Further, in the above-described embodiment, the case where the FET connected to the series position and the FET connected to the position position with respect to the signal line are respectively configured by the JFET has been described, but the present invention is not limited to this. Instead, it may be configured by MESFET (Metal Semiconductor FET).
【0056】
Further, in the above-described embodiment, the case where each field-effect transistor is formed on a semi-insulating GaAs substrate has been described, but the present invention is not limited to this, and each field-effect transistor is formed on another compound semiconductor substrate. It can also be applied in some cases.
【0057】
Further, in the above-described embodiment, the case where the gate of each FET is driven by 1 / -2 [V] has been described, but the present invention is not limited to this, and the gate of each FET is controlled by a control voltage of another value. May be driven.
【0058】
Further, in the above-described embodiment, the antenna switching switch for the digital cellular telephone has been described, but the present invention is not limited to this, and the present invention is not limited to this, and is small and low in mobile communication mobile terminals such as cordless telephones and portable television receivers. It can be applied to various devices that are voltage-driven but require low insertion loss and low distortion characteristics.
【0059】
[Effect of the invention]
As described above, according to the present invention, the pinch-off voltage of the first field-effect transistor stage connected in series with the signal passage is changed to the pinch-off voltage of the second field-effect transistor stage connected between the signal passage and the ground potential. On the other hand, by setting a low potential and preventing the first and second field effect transistor stages from operating due to the same operating characteristics, the second field effect transistor connected between the signal path and the ground potential leaks. It is possible to easily realize a semiconductor switch capable of turning on only the first field-effect transistor connected in series with the signal path without generating electric power. As a result, the insertion loss and distortion of the semiconductor switch can be further reduced as compared with the conventional case.
[Simple explanation of drawings]
[Figure 1]
It is a characteristic curve diagram which shows the distortion generation principle of FET.
[Figure 2]
It is a connection diagram which shows one Example of the switch circuit by this invention.
[Fig. 3]
It is a characteristic curve diagram which provides the explanation of the difference of the current characteristic by the difference of a pinch-off voltage.
[Fig. 4]
It is a characteristic curve diagram which shows the insertion loss characteristic which occurs when the switch circuit of an Example is used.
[Fig. 5]
It is a characteristic curve diagram which shows the insertion loss characteristic which occurs when the conventional switch circuit is used.
[Fig. 6]
It is a characteristic curve diagram which shows the insertion loss characteristic which occurs when the conventional switch circuit is used.
[Fig. 7]
It is a connection diagram which shows the SPDT switch circuit in an Example.
[Fig. 8]
It is a characteristic curve diagram which shows the pinch-off voltage-dependent characteristic of a saturation current.
[Fig. 9]
It is a characteristic curve diagram which shows the input power dependence of the 3rd harmonic distortion of the FET in the ON state.
[Fig. 10]
It is a characteristic curve diagram which shows the input power dependence of the 3rd harmonic distortion of the FET in the off state.
[Fig. 11]
It is a connection diagram which shows the SPDT switch circuit used conventionally.
[Explanation of symbols]
1, 20 ...... SPDT switch circuit, 2, 21 ...... Input side switch, 3, 22 ...... Output side switch, 10 ...... Switch circuit, 2A , 3A, 10A ...... Shant FET, 2B, 3B, 10B ...... Series FET, V<sub>PA</sub>, V<sub>PB</sub>...... Pinch-off voltage.
29 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29
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Priority claims2
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| 26835093 | Japan | A | |
| JP19930268350 | – | – | – |
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Numbers
- Publication
- 7-106937
- Publication, DOCDB
- H07106937
- Publication, EPODOC
- JPH07106937
- Application
- 5268350
- Application, DOCDB
- 26835093
- Application, EPODOC
- JP19930268350
Titles3
- English
- SEMICONDUCTOR SWITCH
- Japanese
- 【発明の名称】半導体スイツチ
- English
- [Title of Invention] Semiconductor Switch
Classification
- IPC, 2
- H03K17 687
- H03K17 00