Duty factor correcting circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a duty correction circuit for a square wave signal having a duty ratio of around 50%.

【0002】

[Conventional technology]

When a square wave signal with a duty ratio of 50% is transferred between boards, devices, etc., waveform collapse occurs due to impedance mismatch, etc., so correction is performed to binarize the signal again on the receiving end side and maintain the duty ratio at 50%. A circuit is needed. Therefore, for example, a signal transmission / reception circuit requires a complicated configuration circuit as described in JP-A-2-131615.

【0003】

[Problems to be Solved by the Invention]

According to the conventional circuit that corrects to a square wave with a duty ratio of 50%, many parts such as an amplifier, a comparator, an integrator, a differential amplifier, and a gain control circuit are required, and feedback amplification is performed. In addition, since an integrator is used, it is necessary to have a time constant sufficiently large with respect to the period of the output signal, and a capacitor with a large value is required. Therefore, in the prior art, the circuit cannot be miniaturized and the cost cannot be reduced due to the complicated circuit and the large capacitor value, and the LSI cannot be used.

【0004】

An object of the present invention is to reduce the cost of downsizing the duty correction circuit, thereby enabling LSI.

【0005】

[Means for solving problems]

The above object is achieved by realizing the binarization of the signals of the first stage and the second stage with the same CMOS inverter and realizing the single power supply operation by using the resistor and the small capacity capacitor. Furthermore, by using a low-pass filter that removes high frequencies without using an integrator, the time constant of the filter can be made the same as the period of the output signal, so this is achieved by reducing the capacitor capacitance value and reducing the size.

【0006】

[Action]

The input signal is binarized by the first-stage CMOS inverter. Then, this output signal is input to a low-pass filter by the next resistor and capacitor, the high frequency component of the input signal is attenuated, and the output of the filter becomes a waveform close to a sine wave. Furthermore, since the center point of the AC component of the sine wave output is the threshold potential of the CMOS inverter in the next stage, only the AC component of the filter output is added to the input of the CMOS inverter in the next stage and the threshold potential is stabilized. The output signal is fed back and added.

【0007】

[Example]

Hereinafter, the present invention will be described with reference to an embodiment of the drawings. In Fig. 1, 1 is a CMOS inverter that amplifies the input signal and binarizes it, and 2 is the resistor R.₁And capacitor C₁A low-pass filter that removes high-frequency components from a signal consisting of, and 3 is a CMOS inverter that binarizes the output signal of the low-pass filter 2 again.

【0008】

FIG. 3 is a signal waveform diagram of points A, B, C, D, and E in the circuit of FIG. 1, and the circuit operation will be described with reference to this. The input signal A is a signal in which the duty ratio shifts due to waveform distortion during transmission, and this is input to the CMOS inverter 1 and binarized to become the output B. This output B is the resistor R₁And capacitor C₂Input to the low-pass filter 2 consisting of. This low-pass filter has a circuit constant set so that the original clock period of the input signal is the time constant, and the filter output C becomes close to a sine wave by attenuating and removing the high-frequency component of the clock frequency of the signal B. .. Next, CMOS inverter 3 has high resistance R for input and output.₂The input of the CMOS inverter 3 becomes the threshold potential of the CMOS inverter 3 by connecting with. Here, the output C of the filter 2 is the capacitor C.₂Removes the DC component and becomes the output D, and this signal D is input to the CMOS inverter 3. When the signal D with the DC component cut is input to the CMOS inverter 3 whose input is kept at the threshold potential, it is pulsed and the output signal E becomes a signal with a duty of 50%.

【0009】

The CMOS inverters 1 and 3 used here operate from a single power supply as shown in Fig. 2. In the transfer region, both P-type MOS21 and N-type MOS22 are saturated, and the center of the transfer, that is, the threshold V._DDSince / 2 almost matches the V level of Vout = Vin, the input can be stabilized to the threshold by biasing by applying feedback with high resistance from the output to the input. Moreover, since the threshold potentials of the P-type MOS21 and the N-type MOS22 have opposite temperature coefficients, the temperature coefficient of the threshold is very small in the entire CMOS, and therefore, the threshold potential E of the CMOS inverter 3 A square signal with a stable duty of 50% can be reproduced with little effect on the duty.

【0010】

Also, capacitor C₁Since the low-pass filter of is a time constant of the clock period of the input signal, this capacitor C₁, And C₂The higher the frequency with which the duty ratio collapses, the smaller the capacity is required. In addition, high accuracy is not required due to the usage conditions of the circuit, so it is easy to make an LSI together with CMOS.

【0011】

[Effect of the invention]

As described above, according to the present invention, the duty can be corrected by a simple CMOS inverter and a primary low-pass filter using a resistor and a capacitor, so that the circuit configuration can be miniaturized and the cost can be reduced.

【0012】

In addition, since it can be configured with a CMOS digital IC and a low-pass filter with a small capacity capacitor, it has the effect of enabling LSI.

[Simple explanation of drawings]

[Figure 1]

A circuit diagram of an embodiment of the present invention.

[Figure 2]

A detailed view of the CMOS inverter in Figure 1.

[Fig. 3]

Explanatory drawing of signal waveform at each point of FIG.

[Explanation of symbols]

1 ... CMOS inverter, 2 ... low pass filter, 3 ... CMOS inverter, 21 ... P type MOS, 22 ... N type MOS.