Memory management system for multiprocessor system

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a memory management method in a multiprocessor system, and more particularly to a memory management method in a multiprocessor system in which each arithmetic unit is provided with a virtual storage mechanism.

【0002】

[Conventional technology]

Conventionally, this type of memory management method will be described with reference to the drawings.

【0003】

FIG. 3 is a virtual storage space address map for explaining a conventional example. Figure 3 shows that the address is represented by 32 bits, and 64 megabytes of physical data is implemented in each of the 16 arithmetic units. In addition, each arithmetic unit has a communication function capable of exchanging information between arithmetic units.

【0004】

In this example, virtual storage space 0_X40000000 to 0_XWhen the virtual address of 7fffffff is accessed, it is fixedly assigned to the virtual storage space so that other arithmetic units can be accessed by the communication function. That is, virtual address 0_XVirtual address 0 from 40000000_xIn 43ffffff, arithmetic unit 10, address 0_xAddress 0 from 44000000_xUp to 47ffffff, the arithmetic unit 11 is accessed respectively, and the same applies below.

【0005】

Figure 4 shows the bit configuration of the virtual address. The virtual dress g represented by 32 bits represents the upper 2 empty bits, 4 bits representing the arithmetic unit number h, and the virtual address i in the arithmetic unit number h26. Consists of bits. If the arithmetic unit number h is not the number of the own arithmetic unit, the inter-arithmetic unit communication function is used to transmit the virtual address i to the arithmetic unit h.

【0006】

The arithmetic unit number h has a value from 0 to 15, the arithmetic unit 10 is the arithmetic unit number 0, the arithmetic unit 11 is the arithmetic unit number 1, and so on. In addition, the virtual address i of 26 bits is the number of bits required to represent 64 megabytes of the implemented physical record.

【0007】

In this way, the arithmetic unit allocated all 16 64 megabytes of physical memory to the virtual storage space.

【0008】

[Problems to be Solved by the Invention]

In the memory management method in the conventional multi-processor system described above, a specific area of the virtual storage space of each arithmetic unit is fixedly allocated so as to refer to the virtual storage space of the specific arithmetic unit. In the case of a large-scale multiprocessor system configuration in which an arithmetic unit is provided and each arithmetic unit has a large amount of physical memory space, there is a drawback that the area of the virtual storage space is insufficient.

【0009】

[Means for solving problems]

In the memory management method in the multi-processor system of the present invention, the virtual storage space and the physical memory space of each arithmetic device are divided into fixed-length sizes in each arithmetic device of the multi-processor system having a virtual storage mechanism, and the fixed length is obtained. A paging memory management means that associates the virtual storage space with the physical memory space and the virtual storage space of the virtual storage space with another arithmetic device by using a conversion table as a unit, and other operations. The remote memory registration means registered in the conversion table using the paging memory management means so as to allocate the virtual storage space of the device to the virtual storage space of its own arithmetic device, and the conversion table used in the paging memory management means. When registering a virtual storage space, it has a storage space protection means to be registered together with the attributes of the virtual storage space.

【0010】

[Example]

Next, examples of the present invention will be described. FIG. 1 is a block diagram showing an embodiment of the present invention, and is a multiprocessor system in which two arithmetic units 1 and 2 have virtual storage spaces a and c and physical storage spaces b and d. The virtual storage spaces a and b and the physical storage spaces b and d are divided into fixed-length sizes, and the virtual storage space a to the physical storage space b and the virtual storage space c to the physical are used in fixed-length units using a conversion table, respectively. The virtual storage space d can be obtained, and the virtual storage space c can also be obtained from the virtual storage space a.

【0011】

The method of obtaining the physical storage space d from the virtual storage space a with respect to the virtual storage space a in the calculation device 1 and the physical storage space d from the virtual storage space c in the calculation device 2 is the same as the known paging method, but the calculation device 1 It is possible to obtain the virtual storage space c from the virtual storage space a of the arithmetic unit 2. Further, the conversion table exists in the extended paging memory management means 3 and the extended paging memory management means 6.

【0012】

The paging memory management means 3, so that the virtual storage space c of the arithmetic unit 2 can be obtained from the virtual storage space a of the arithmetic unit 1 and the storage space a of the arithmetic unit 1 can be obtained from the virtual storage space c of the arithmetic unit 2. 6 and the remote memory registration means 4 and 7 for registering the virtual storage space of other arithmetic units in the conversion table in the paging memory management means 3 and 6, and the paging memory management means 3 and 6 and the virtual storage in the conversion table to be used. It includes storage space protection means 5 and 8 for registering the attributes of virtual storage spaces a and c when registering spaces a and c.

【0013】

Next, in this embodiment, a method of accessing the virtual storage space of another arithmetic apparatus will be specifically described.

【0014】

FIG. 2 shows the format of one page table entry of the conversion table provided in the extended paging memory management means 3 and 6 of FIG. 1, and has a 64-bit configuration. The page number PFN of the physical memory space stores the upper 20 bits of the address of the physical memory space of the self-performing device and the upper 20 bits of the address of the virtual storage space of the page number of the virtual storage space. The system shown in this embodiment for being represented by the high-order bits of the page number PFN of the physical memory space and the page number VFN of the virtual storage space has one entry for every 4 Kbytes.

【0015】

The paging table entry j is newly created when the self-arithmetic unit requests access to the virtual storage space of the self-performing device, and is to be referred to when the access exists. Switching between PFN and VFN whether the virtual storage space points to the physical storage space of the own arithmetic unit or the virtual address of another arithmetic unit when the virtual storage space of the own arithmetic unit is accessed by the own arithmetic unit. This is done by reading bit M. Furthermore, by setting the write permission bit W and the read permission bit R, it is determined whether or not to allow access when there is access from another arithmetic unit.

【0016】

If a certain arithmetic unit wants to access the virtual address of another arithmetic unit, first create a new page table entry j, and set bit M of the created page table entry j to 1 to access the other arithmetic unit. Write the upper 20 bits of the virtual address in the virtual memory blank page number to the VFN area, and write write permission bit W and read permission bit R. Since one page table entry can only manage up to 4 kbytes of area, create multiple page table entries if you want to access an area that exceeds 4 kbytes.

【0017】

Each arithmetic unit 1 and 2 first reads bit M when an access occurs to the actually created page table entry. When bit M is 0, it indicates the physical storage space of the own arithmetic unit, so the page number PFN of the physical storage space is read. When bit M is 1, the page number VFN of the virtual storage space and the arithmetic unit number PEID are read, and the page number VFN of the virtual storage space is transmitted to the arithmetic unit having the arithmetic unit number PEID using the inter-arithmetic unit communication function. ..

【0018】

Reads the paging number table entry of the virtual storage space, reads the write permission bit R in the read page entry, determines whether it is accessible, eliminates inadvertent memory access, and protects the memory area.

【0019】

[Effect of the invention]

According to the present invention, since the virtual storage space of another arithmetic unit is registered in the conversion table of its own arithmetic unit in fixed length units and assigned to the virtual storage space, the virtual storage space of the other arithmetic unit that does not need to be accessed is created by itself. It is no longer allocated to the virtual storage space of the arithmetic unit, and it is possible to avoid unnecessary use of the virtual storage space of the own arithmetic unit, and it is prepared to increase the physical storage space of each arithmetic unit and further increase the number of arithmetic units constituting the multi-processor system. It has the effect of being able to deal with.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows one Example of this invention.

[Figure 2]

It is a figure which shows the table which manages the virtual storage space in the Example shown in FIG.

[Fig. 3]

It is an address map of a virtual storage space for explaining a conventional example.

[Fig. 4]

It is a figure which shows the bit division of the virtual address in the conventional example.

[Explanation of symbols]

1, 2 Arithmetic logic unit 3, 6 Pazing memory management means 4, 7 Remote memory registration method 5, 8 Storage space protection measures 10 ~ 25 Fixed memory map of virtual address space for each arithmetic unit a, c, e virtual storage space b, d, f physical storage space g, i virtual address PFN physical storage paging number VFN virtual storage paging number h, PEID arithmetic unit number R Read permission bit W write permission bit Switching bit between M PFN and VFN