Memory access controller

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a device that controls memory access by a CPU, and more particularly to a memory access control device that automatically sets the number of weights at the time of memory access to an optimum value.

【0002】

[Conventional technology]

In a commercially available computer or word processor, RAM (random access memory) may be added to a specific memory address area for use. The access speed of this additional RAM differs for each RAM when the manufacturer or model changes and the type of device changes.

【0003】

On the other hand, in the personal computer or word processor, the number of weights that determine the timing of memory access by the CPU (central processing unit) is fixed by a circuit that controls memory access. As described above, in a device having a fixed number of weights, various inconveniences occur when the access speed of the additional RAM is different. If the RAM access speed is slow compared to the number of weights, operation errors such as RAM read / write errors occur. On the contrary, when the access speed of RAM is faster than the number of weights, it means that the device is not effectively using the access speed of RAM.

【0004】

Further, the change in the RAM access speed as described above also occurs due to a cause other than the change in the device type. For example, the RAM access speed may change due to changes in the operating environment of the device, such as when the place where the device is used changes and the temperature changes, and the number of weights and the memory access speed may not match. ..

【0005】

In the conventional device, when the access speed of RAM does not match the number of weights, the hardware or software of the memory access control device is changed to match the number of weights with the access speed of the memory.

【0006】

[Problems to be Solved by the Invention]

Adjusting the number of weights by changing the hardware or software of the memory access control device in the conventional device as described above is disadvantageous in terms of cost and time. On the other hand, the present invention is optimal in a memory access control device by allowing the CPU to automatically control the number of weights at the time of memory access in response to changes in the type of device or changes in the operating environment. The purpose is to make it easy to perform a memory access cycle.

【0007】

[Means for solving problems]

In order to achieve the above object, the present invention corresponds to a holding means for holding the number of weights and the number of weights held by the holding means in a CPU and a memory access control device including a memory accessed by the CPU. The timing generation circuit that generates the timing signal for CPU memory access, the means for checking the operation error at the time of memory access of the memory, and the number of weights held in the holding means according to the check result of this checking means. A memory access control device is configured by providing means for changing.

【0008】

[Action]

When the CPU is made to access the memory while changing the number of weights by the memory access control device configured as described above, it is possible to determine the number of weights that cause an operation error and the number of weights that do not cause an operation error at the time of memory access. By utilizing this, the earliest number of weights within a range in which an operation error at the time of memory access does not occur can be automatically set in the memory access control device. By setting the number of weights of the memory access control device in this way, it is possible to execute an optimum memory access cycle in response to a change in the type of device or a change in the operating environment.

【0009】

[Example]

Hereinafter, examples of the present invention will be described. In the drawings for explaining each embodiment, those having the same function are designated by the same reference numerals, and duplicate description will be omitted.

【0010】

[Example 1] Example 1 of the present invention will be described with reference to the drawings. Figure 1 shows the circuit that controls the memory access of the CPU. A plurality of memories 2 to which memory address areas are allocated are connected to the CPU 1 via the data bus 3 and the address bus 4. The figure shows only one memory 2. The illustrated memory 2 is RAM built into the device or additional RAM.

【0011】

From CPU1, a control signal for memory access is output from control line 5. This control signal is decoded by the decoding circuit 13 and introduced into the timing generation circuit 16 through the selector 14 and the decoding circuit 15. Further, the number of weights written in the register 12 is introduced into the timing generation circuit 16. The number of weights is written in the register 12 corresponding to the memory address area of each memory. This register 12 is a read / write register, and the number of weights is written by the write circuit 11. The method for determining the number of weights will be described later.

【0012】

The selector 14 reads out the number of weights corresponding to the memory address area of the memory 2 which is the target of access from the control signal passed through the decoding circuit 13. The timing generation circuit 16 generates various timing signals necessary for accessing the memory 2 from the control signal from the CPU 1 and the number of weights corresponding to the target memory 2. For example, the RAS signal, CAS signal, and WE signal are output to the memory 2, and the READY signal indicating that the access operation is completed is returned to the CPU1.

【0013】

In this way, the timing generation circuit 16 generates various timing signals for the memory 2 based on the number of weights written in the register 12, so that the number of weights is the optimum value corresponding to the access speed of the memory 2. Then, the optimum memory access cycle can be obtained. A check means 17 is provided in order to optimize the number of weights. The check means 17 is illustrated as a circuit capable of performing read / write / compare, but the check means 17 can also be realized by a program incorporated in the CPU 1. The check means 17 checks for an operation error when the memory 2 is accessed, and the CPU 1 rewrites the number of weights written in the register 12 through the write circuit 11 according to the check result.

【0014】

Next, the procedure for optimizing the number of weights in the register 12 will be described with reference to the flowchart of FIG. The operation of determining the number of weights described below is performed, for example, when an additional RAM is newly added, targeting the additional RAM. As another example, when the device is moved to a place where the operating environment is different, or when the power of the device is turned on, the total memory can be targeted and the weight number can be sequentially determined.

【0015】

An appropriate number of weights is written in the register 12 in advance from the CPU 1 through the write circuit 11 as an initial value. The number of weights is written in this register 12 in a form corresponding to the memory address area of each memory. In step S21, the CPU 1 writes specific data in the target memory 2. This write operation is performed by the timing signal generated by the timing generation circuit 16 using the number of weights for the target memory 2 written in advance in the register 12. At this time, data is also written to the check means 17.

【0016】

In step S22, the check means 17 compares the data output from the CPU 1 with the data written in the memory 2. As a result, if both data match, it is determined that there is no error in the operation of the memory 2, and the process proceeds to step S23. If they do not match, it is determined that there is an error in the operation of memory 2, and the process proceeds to step S27.

【0017】

If there is no error in the operation of memory 2, subtract 1 from the value of the number of weights in register 12 in step S23. Subsequently, in step S24, specific data is written to the target memory 2 in the same manner as in step S21. Since this writing operation is performed at a timing based on the number of weights set in step S23, the writing operation is performed at a timing earlier than the writing operation performed in step S21 before.

【0018】

In the following step S25, the operation error is checked in the same manner as in the previous step S22. If there is no error here, the process returns to step S23, and 1 is further subtracted from the number of weights in register 12. After that, the operation is carried out in the same manner, and the number of weights is gradually reduced unless a write operation error occurs in the memory 2. As a result, the timing of memory access is gradually accelerated. Then, when the number of weights becomes too small with respect to the access speed of the memory 2, an operation error occurs, an error is detected in step S25, and the process proceeds to step S26.

【0019】

In step S26, 1 is added to the number of weights to end the operation. As a result, the value of the number of weights immediately before the occurrence of the operation error by gradually reducing the number of weights, that is, the number of weights that can access the memory at the earliest timing when the operation error does not occur is written in the register 12. It means that it was included. Therefore, the number of weights for executing the optimum memory access cycle is obtained.

【0020】

Next, when it is determined in step S22 that there is an error, the process proceeds to step S27, and 1 is added to the register value. In the following step S28, specific data is written to the target memory 2 in the same manner as in step S21. Since this write operation is performed at a timing based on the number of weights set in step S27, the write operation is performed at a timing higher than the write operation previously performed in step S21.

【0021】

In the following step S29, the operation error is checked in the same manner as in the previous step S22. If there is still an error here, the process returns to step S23, and 1 is added to the number of weights in register 12. After that, the operation is carried out in the same manner, and the number of weights is gradually increased until the write operation error of the memory 2 is normally performed. As a result, the timing of memory access is gradually delayed.

【0022】

Then, when the number of weights becomes an appropriate value with respect to the access speed of the memory 2, the operation ends when the error is no longer detected in step S28. At this time, the value of the number of weights written in the register 12 is the number of weights that can access the memory at the earliest timing when no operation error occurs. Therefore, the value of the optimum number of weights for the access speed of the memory 2 is written in the register 12.

【0023】

When there are a plurality of target memories, the operation of determining the number of weights described above is sequentially performed for each memory. Then, after the operation described above is completed, the system returns to the normal system operation. At the time of memory access in this normal operation, the access timing is determined by the number of weights determined in the procedure described above, so that the optimum memory access cycle is executed.

【0024】

In the above description, it is assumed that the number of weights of an appropriate value is written in the register 12 in advance, but as this value, an arbitrary value from the earliest value to the latest value should be written. Can be done. As is clear from the above description, according to this embodiment, even when trying to operate memories having different access speeds, it is not necessary to change the hardware or software of the memory access control circuit, and it is automatic. The number of weights of the register is changed, and access is executed at the timing adapted to the access speed of the memory.

【0025】

[Example 2] In the first embodiment, the check means 17 that performs write / read / compare is used as a means for checking an operation error at the time of memory access of the memory 2. However, instead of this, memory data is used. It is also possible to use the parity check circuit of.

【0026】

This example will be described with reference to the figure as Example 2. FIG. 3 shows a circuit that controls the memory access of the CPU of this embodiment. In this figure, the difference from FIG. 1 of the first embodiment is that the operation error of the memory 2 is checked by the parity check circuit 18 of the memory 2. A parity error also occurs when the timing of memory 2 access by CPU 1 is faster than the memory 2 access speed and memory access cannot be performed normally. In this embodiment, this parity error is detected by the parity check circuit 18, and the number of weights of the register 12 is rewritten by the write circuit 11. Other points in Fig. 3 are the same as in Fig. 1.

【0027】

The operations of the second embodiment are performed in the order shown in the flowchart of FIG. The difference between FIG. 4 and FIG. 2 of the first embodiment is that the step numbers in the 20s are used in FIG. 2, whereas the step numbers in the 40s are used in FIG. Further, in FIG. 2, the data is compared in steps S22, 25, and 29, whereas in FIG. 4, the parity check is performed by the parity check circuit 18 in steps S42, 45, 49. There is.

【0028】

The operation of FIG. 4 is almost the same as that of FIG. 2, but when specific data is written to the target memory 2 in steps S41, 44, 48, the memory access timing is compared with the access speed of the target memory 2. If it is too early, an operation error will occur and a parity error will occur. In steps S42,45,49, the presence or absence of an operation error at the time of memory access is determined by checking this parity error. Steps S42, 45, 49 The following steps are the same as in FIG. 2 of the first embodiment, and in the present embodiment, the same operation as that of the first embodiment is performed, and the same effect is obtained.

【0029】

When an NMI (Nanmaskable Interrupt) routine is used for the parity check, the parts of steps S47 to 49 in FIG. 4 may be included in the NMI service routine program.

【0030】

[Effect of the invention]

According to the present invention, the optimal memory access cycle can be easily performed by making it possible for the CPU to automatically control the number of weights at the time of memory access to respond to changes in the type of device or changes in the operating environment. It can be made runnable.

[Simple explanation of drawings]

[Figure 1]

The circuit diagram of Example 1 of this invention.

[Figure 2]

The flowchart which shows the operation of the circuit of FIG.

[Fig. 3]

The circuit diagram of Example 2 of this invention.

[Fig. 4]

The flowchart which shows the operation of the circuit of FIG.

[Explanation of symbols]

1 ... CPU 2 ... memory 3 ... data bus 4 ... Address bus 5 ... control line 11 ... write circuit 12 ... register 13,15 ... Decoding circuit 14 ... Selector 16 ... Timing generation circuit 17 ... Checking means 18 ... Parity check circuit