Data pipeline device and data encoding method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a pipeline consisting of a processing stage and a storage element, and a data encoding method within the pipeline.

【0002】

[Conventional technology]

Improving the processing speed of digital data is an important aim in almost all analog and digital circuits. An example of a data processing circuit is a so-called "pipeline" circuit. In a typical pipeline circuit, data is received by the first processing station, the processing stage, and transferred to the next processing stage in a predetermined order. Each of the processing stages processes the data or simply acts as a data passage to transfer the data during the next clock cycle.

【0003】

By the way, conventional pipeline circuits are "rigid" and therefore, if a delay occurs in one processing stage, the entire pipeline circuit is to be stopped. And the entire pipeline circuit had to wait for the work of the delayed processing stage to finish. Due to the stoppage of the entire pipeline circuit, processing stages other than the processing stage being delayed cannot perform data processing operations beyond the processing work that does not require data transfer. Since many pipeline circuits have a plurality of stages that cannot perform processing operations at the same time, the operation of the entire pipeline is stopped in such a case. As a result, pipeline circuits tend to repeat data processing at each processing stage rather than processing different data at the same time. This wastes a great deal of time for each processing stage to wait for the processing of the other stages, wasting the potential processing power given to the pipeline circuitry. Ideally, every processing stage spends its own data processing time.

【0004】

Of the many digital television devices, such as digital high-definition television (HDTV), are expected to replace traditional analog technology, reducing data transfer rates by avoiding the transmission of redundant information. Has been done. Many techniques have been utilized to achieve this, one of which is well known as entropy coding. In such a device, the television image is converted into a series of symbols, which are reconstructed into an image by using an appropriate algorithm in the television receiver and displayed by the display device of the receiver. In order to transmit these symbols from the transmitter to the receiver side, a unique digital code for identification is assigned to each symbol.

【0005】

In entropy coding technology, digital codes of different lengths are associated with symbols, and the symbol that appears most frequently is represented by the code of the shortest length. Most of the symbols to be transmitted in this way are represented by short time-long codes compared to long codes that are short and not transmitted very often.

【0006】

In the television receiver, prior to the display, processing work to be performed one after another for the reconstruction of the television image is performed. For example, one of these processing operations is the decoding operation of entropy code data converted into a symbol string. This decoded data is written in the digital memory after undergoing a further processing stage. The data written in the memory in this way may be digital data that directly indicates the decoded picture, or may be one copy of the decoded data that should be further processed in order for the picture to be completely decoded. In any case, there is a pipeline processing stage, one of which is an entropy decoder, and the data that reaches the end of this pipeline is written to the digital memory.

【0007】

In such a pipeline circuit, there are at least two stages that stall the pipeline processing. For example, an entropy decoder requires various time lengths for decoding a symbol because the length of the digital code representing the symbol is different. Also, the digital memory may hold the pipeline data because it is not always possible to write the data received from the pipeline immediately. Memory devices are often a shared resource with other processes. Also, at least, data may have to be retrieved from the memory display for display or further processing.

【0008】

In a "rigid" pipeline circuit, when the entropy decoder cannot transfer the decoded symbol to the next processing stage, all subsequent pipeline stages must wait, and the digital memory is in front of it. I can't write data because I can't receive data from the stage. Similarly, if the digital memory device itself cannot write the received data because it is doing other processing, the entire pipeline must be shut down. In such a case, the entropy decoder cannot perform further processing once the symbol decoding is completed. After all, this symbol cannot be sent to the next stage in the pipeline.

【0009】

Another drawback of conventional pipeline circuits is that when a delay occurs in any of the processing stages, the signals corresponding to all the processing stages prior to that processing stage are transmitted and processed until the work of that processing stage is completed. It is necessary to stop. If the delayed processing stage is near the end of the pipeline circuit, this corresponding signal must be transmitted to almost all processing stages. Further, in a pipeline circuit including a considerably large number of processing stages, it is very difficult to make such a signal transmission at a desired speed. Furthermore, in a rigid pipeline circuit, a control signal for stopping these must be transmitted to a stage following the processing stage in which the delay has occurred.

【0010】

In many pipeline circuits, the type of data processed at each processing stage is single. In such a pipeline circuit, each processing stage receives the data from the previous processing stage as the correct type of data for the processing operation. Then, when the data is processed and then transferred to the next processing stage, the processing stage is also regarded as the correct type of data. In many cases it is advantageous to use a single method of encoding data in pipeline circuits where different types of data are introduced. For example, the data is divided into several "packets". Each of these packets contains information that describes the type of data contained in the other packets.

【0011】

[Summary of Invention]

The data processing pipeline according to the present invention includes a plurality of pipeline stages connected in cascade, and each stage has a data input and a data output end. The data output end of each processing stage is connected to the data input end of the next processing stage, and each processing stage has a storage unit for storing data and a signal indicating the validity of the data contained in the processing stage. This storage unit contains means to allow loading. Various embodiments in this regard include accepting circuits that generate a data accepting signal that is transferred from each processing stage to the next processing stage.

【0012】

In at least one embodiment, this acceptance signal is used to prohibit or enable loading of data and validity signals. The input data is loaded into the next processing stage when the acceptance signal transferred from one processing stage to the next processing stage is in the positive state. Similarly, when the acceptance signal transferred from one processing stage to the previous stage is in the positive state, the validity signal is loaded into that processing stage. The acceptance signal of each processing stage is set to indicate data acceptance readiness if that processing stage does not contain valid data or the next processing stage indicates that it is ready to accept data. In this way, data is transmitted to each processing stage indicating signal acceptance preparation.

【0013】

In a preferred embodiment, the data and the validity signal are loaded into each processing stage simultaneously. Further, in this embodiment, each processing stage has an auxiliary data storage unit. When a processing stage contains valid data, it predicts that the valid data can be transmitted to the next processing stage and indicates the preparation for loading new data to the previous processing stage. At this time, if the data cannot be transferred to the next processing stage, the new data supplied from the previous processing stage is loaded into the auxiliary data storage unit. It then notifies the previous processing stage that further loading of new data is no longer possible. Such a state continues until the original valid data is transferred to the next processing stage and the new data in the auxiliary storage unit is transferred to the main storage unit. At this time, the auxiliary storage unit can load data when such a condition occurs again.

【0014】

In at least one preferred embodiment, each processing stage also includes a storage unit that stores the acceptance signal transferred from the next processing stage. In this case, the transfer of the acceptance signal is limited to the nearest preceding processing stage. In at least one embodiment, the pipeline circuit has a multiphase clock and the loading of the main and auxiliary storage units is done in different phases.

【0015】

A given processing circuit is included in some or all of the processing stages of the pipeline. This processing circuit not only processes the data transferred from the previous processing stage, but also processes the validity signal and the acceptance signal. The processing circuit also generates or deletes data and accepts data and control signals from sources other than the pipeline circuit. In certain embodiments of the invention, the processing circuits in some or all of the processing stages process one or more inactive modes and process data or other signals that simply transfer the data to the next processing stage. Has an active mode.

【0016】

In this embodiment, when a predetermined processing stage has a data decoding circuit and the processing circuit of each processing stage has one of the activation patterns of input data and / or other signals supplied to the decoding circuit. Enter active mode. In another embodiment of the invention, each processing stage is connected to an additional bit line to transfer additional bits for grouping the data words into data blocks in addition to the data words. Each processing stage has a latch circuit for loading the current value and the previous value of the additional bit, and acts as a state processing circuit for processing and transferring data based on the change of the additional bit.

【0017】

Another feature of the invention is a method of encoding data into a string of data, where the data is blocked into data words, each word having a corresponding additional bit. Further, the area of the address bit is inserted into the first data word in the transferred block. This first data word follows the data to be processed by one or more processing stages activated by the pattern of address bits. This address area is preferably encoded using Huffman code.

【0018】

The data pipeline circuit according to the present invention has several features as follows. That is, 1. This pipeline circuit is "elastic", and the delays that occur in one processing stage have little effect on the other processing stages. Subsequent processing stages can continue processing operations, which means that there will be a gap in the data flow after the delayed processing stage. Similarly, the preceding processing stage continues to operate as much as possible, in which case the data flow gap can be eliminated.

【0019】

2. Control signals that tune the pipeline circuit are generated and these control signals are transmitted to the nearest adjacent processing stage. When the control signal flows in the same direction as the data flow, this adjacent processing stage is the processing stage immediately after. When the control signal flows in the direction opposite to the data flow, this control signal is transmitted to the immediately preceding processing stage.

【0020】

3. The data in the pipeline circuit can be encoded and various types of data can be processed. This coding includes data packets of various sizes, and it is not necessary to know the size of the packets in advance. 4. The overhead of describing the type of data can be as small as possible. 5. Each processing stage can be made aware of only the minimum number of types of data required for its required operation. However, it is possible to transfer all types of data to the next processing stage without recognizing the type of data. This allows communication between non-adjacent processing stages.

【0021】

To facilitate understanding of the invention and to show how the invention is practiced, it will be described below with reference to the accompanying drawings.

【0022】

[Example]

For the purpose of explaining the features used in the preferred embodiments of the present invention, FIG. 1 shows the six cycles of a pipeline circuit consisting of six processing stages in a very simplified manner. As further detailed below, preferred embodiments of the present invention include seven advantageous features not shown in FIG.

【0023】

In FIG. 1, each column of blocks or boxes shows each processing stage and one cycle labeled A through F. Each hatched box indicates a processing stage that holds valid data, which means data that should be processed in any one of the processing stages of the pipeline. After the processing work including simply transferring the data without processing is completed, the valid data is sent from the processing stage as valid output data.

【0024】

It should be noted that the actual pipeline circuit may contain more or less processing stages than 6 processing stages. The present invention can be applied to a pipeline circuit having any number of processing stages. Further, the data is processed in a plurality of processing stages, and the processing time differs for each processing stage, but this is not always necessary.

【0025】

In addition to the clock and data signals described below, the pipeline circuit transfers two control signals, an "valid" signal and an "accept" signal, to control the transfer of data in the pipeline circuit. It has become like. The active signal, shown as the upper side of the two lines connecting adjacent processing stages as shown, is transferred from each processing stage to a nearby device or other processing stage or another system in the forward or downstream direction. For example, the final pipeline processing stage transfers the data to a subordinate processing circuit. The "accept" signal is shown below the two lines connecting the adjacent processing stages, which are forwarded towards the preceding processing stage, i.e. upstream.

【0026】

Although not shown in FIG. 1, a data line consisting of a single line or a plurality of parallel lines constituting the data bus enters and exits each pipeline processing stage. Data is transferred across the data line between processing stages, as described in detail below. The first processing stage receives data and control signals from a preceding stage consisting of, for example, an image transmission system, a receiving circuit such as another pipeline circuit, or all or part of the data to be processed in the pipeline. Is generated by itself. As will be described later, the term "stage" means an arbitrary processing circuit, for example, it may be a circuit that simply transfers data, or it may be another pipeline circuit having a plurality of stages. This stage, or processing stage, then creates, modifies, and removes data.

【0027】

When the processing stage of the pipeline contains valid data to be transmitted to the next stage, the validity signal indicating the validity of the data need not be transferred to a stage other than the immediately following processing stage. Therefore, a two-line interface is provided between each processing stage. Further, a similar two-line interface is provided between the first stage and the preceding device, and between the last processing stage and the succeeding device.

【0028】

Each of these acceptance and active signals has high and low values, which are indicated as "H" and "L", respectively. The most common use of pipelines according to the invention is digital circuits, where high levels are shown, for example, as logic "1" and low levels are shown as logic "0". However, the present invention is not limited to digital circuits and can also be used in analog circuits. And the high level is a voltage higher than a certain threshold, and the lower level is indicated by a voltage equal to or lower than another threshold. In digital circuits, the present invention can be formed by circuits using CMOS or bipolar transistors.

【0029】

In the present invention, even in a digital circuit, a separate storage device and a wire for storing an active signal are not required. All that is required is that something that shows the validity of the data is stored with the data. For example, digital television image data representing a digital value defined in the international standard CCIR601 is not allowed to take a specific value. In this system, 8-bit binary numbers are used to represent picture sample values, but 0 and 255 values cannot be used.

【0030】

When such an image signal is processed in a pipeline circuit according to the invention, one of these values, eg 0, is used to indicate the ineffectiveness of the data at a particular stage. And in this case, any data that does not contain 0 can be considered valid. This example does not include another latch that stores the validity of the relevant data. And the validity of the data is stored with the data.

【0031】

In FIG. 1, the status of the validity signal is indicated by an arrow pointing to the right at each stage, the "H" or "L" on the upper line. The validity signal from stage A to stage B is L or low in this case. The validity signal from stage D to stage E is H or high. The state of the acceptance signal supplied to each stage is indicated as an "H" or "L" in the lower line, the left-pointing arrow. The acceptance signal from stage E to stage D is therefore high, and the acceptance signal from the device connected downstream of stage F is low.

【0032】

As long as the acceptance signal from the downstream processing stage to the processing stage adjacent to the upstream is high, data is transmitted during one cycle described later. If the acceptance signal is low between the two processing stages, no data is transferred between the two processing stages. The hatched box in FIG. 1 is assumed to contain valid output data, and the validity signal from that processing stage to the next processing stage is high. Figure 1 shows that processing stages B, D and E contain valid data. Processing stages A, C and F do not contain valid data. At the start, the validity signal to processing stage A is high, which means that the data supplied to this pipeline circuit is valid.

【0033】

At this time, the acceptance signal to the processing stage F is low, and therefore no data is output from the processing stage F regardless of whether the data is valid or not. Both valid data and invalid data are transmitted at the designated processing time. And invalid data is data that does not need to be preserved and is overwritten and removed from the pipeline circuit, while valid data is overlaid because it must be retained for use or processing in the next stage of equipment. Must not be written. In the pipeline circuit shown in FIG. 1, the processing stage E contains the valid data D1, the processing stage D contains the valid data D2, the processing stage B contains the valid data D3, and the device (not shown) connected to the upstream of the pipeline is the data. This data, including D4, is transferred to this pipeline for processing. The processing stages B, D and E include valid data together with the upstream equipment, and the validity signal supplied from these processing stages or equipment to the processing stage of each next stage is high. The validity signals from processing stages A, C and F, however, are low because these stages do not contain valid data. Now suppose that the equipment connected downstream of this pipeline is not ready to accept data from the pipeline circuit. This can be shown by setting the acceptance signal to the processing stage F to low. However, the processing stage F itself does not contain valid data and can therefore accept data from the previous processing stage E. Therefore, the acceptance signal from the processing stage F to the processing stage E takes a high value.

【0034】

Similarly, processing stage E does not contain valid data, and processing stage F can accept this data, so processing stage E accepts new data as long as valid data D1 is first transferred to processing stage F. Can be done. In other words, although the processing stage F cannot transfer the data to the next stage, all the other processing stages have no valid data to be overwritten or lost, so that the data can be accepted. At the end of cycle 1, the data shifts one step to the right. This condition is shown as cycle 2.

【0035】

In the example shown in FIG. 1, the device downstream of stage F is not yet ready to accept new data, so the acceptance signal to processing stage F is still low in cycle 2. Therefore, the processing stage F cannot accept new data because the valid data D1 may be overwritten and lost. Therefore, the acceptance signal from the processing stage F to the processing stage E is in the low state. Further, the acceptance signal from the processing stage E to the processing stage D is low because the processing stage E contains the valid data D. However, all stages of processing stages A to D can accept new data because they do not contain valid data or can shift the valid data to the downstream side, which causes the acceptance signal to be high. By doing so, this state is notified to the previous stage immediately before.

【0036】

The post-cycle 2 state of the pipeline circuit of FIG. 1 is illustrated in the cycle 3 column. For example, if the device downstream of processing stage F is not yet ready to accept new data, the acceptance signal to stage F remains low. Processing stages E and F are therefore blocked, but in cycle 3, processing stage D accepts valid data D3 and overlays it on the invalid data that was already in that processing stage. Since the processing stage D cannot transfer the data D3 in the cycle 3, it cannot accept new data and keeps the acceptance signal of the processing stage C low. However, processing stages A through C are ready to accept new data, which is indicated by setting the corresponding acceptance signal high. The data D4 is shifted from the processing stage A to the processing stage B.

【0037】

In cycle 4, the equipment downstream of processing stage F is ready to accept new data. In this case, the acceptance signal to the processing stage F becomes high, indicating that acceptance is ready. Processing stages C to F have valid data and these stages can accept new data because the data can be shifted downstream. Therefore, each of these stages outputs the acceptance signal as high.

【0038】

As long as the incoming signal to the final stage of the pipeline circuit, the processing stage F, is high, the pipeline circuit shown in FIG. 1 acts as a rigid pipeline and simply shifts the data downstream by one step in each cycle. Therefore, the data D1 contained in the processing stage F in the cycle 4 is shifted to the device in the next stage of the pipeline in the cycle 5 and sent out, and the other data is also shifted downstream by one step.

【0039】

Here, it is assumed that the acceptance signal to the processing stage F becomes low in cycle 5. This means that processing stages D to F cannot accept new data again, and the acceptance signal from these stages to the immediately preceding stage becomes low. Therefore, data D5 is shifted, but data D2, D3 and D4 cannot be shifted downstream. The state of the pipeline circuit after cycle 5 is shown as cycle 6 in FIG.

【0040】

The function of filling an empty processing stage next to the pipeline circuit of the embodiment according to the present invention is very effective. This is because the processing stages can be separated from each other. In other words, even if one processing stage is not ready to accept data, the entire pipeline does not have to stop and there is no need to wait for a delayed processing stage. In addition, when one processing stage cannot accept valid data, it forms a temporary "wall" in the pipeline, and the processing stages downstream of this "wall" continue to shift the valid data. And the stage to the left of the wall processing stage can accept data and transfer valid data downstream. In addition, even without that some of the processing stage of the pipeline accepts the temporary new data other processing stage is normally dynamic it is possible to continue the operation. In particular, the pipeline circuit according to the present invention can continue to accept data to stage A unless stage A contains valid data that is not transferred because it is not ready to accept data for the next stage. As shown in this example, data can be transmitted between stages and fed to the pipeline circuit even when one or more processing stages are blocked.

【0041】

In the embodiment according to the present invention shown in FIG. 1, the acceptance signal received from the next stage is not stored in each stage, and whenever the acceptance signal to the downstream stage becomes low, This low signal is forwarded upstream unless the adjacent stage contains valid data. For example, in FIG. 1, assuming that the acceptance signal to stage F is low in cycle 1, the low signal from stage F is transferred to stage D in cycle 2.

【0042】

When the data D3 is latched by the processing stage D in the cycle 3, the acceptance signal is transferred to the stage C 4 stages upstream. When the acceptance signal to stage F becomes high in cycle 4, this acceptance signal reaches stage C. In other words, the change in the received signal propagates upstream of the four stages. However, in the embodiment shown in FIG. 1, if the intermediate stage can accept new data, it is not necessary to propagate the acceptance signal all the way to the beginning of the pipeline (head stage).

【0043】

In the embodiment shown in FIG. 1, each processing stage requires separate input and output data latches to eliminate unintended overwriting of data transmission between stages. This pipeline is also expanded, although the pipeline circuit shown in Figure 1 can compress when the downstream processing stage is blocked and data cannot be transferred. It does not generate a stage that does not contain valid data between stages. Rather, compression capacity relies on the cycle during which valid data is not fed to the first processing stage.

【0044】

For example, in cycle 4, if the acceptance signal to stage F remains low and stages A and B are filled with valid data, this pipeline circuit will further compress as long as the valid data continues to be supplied to stage A. It cannot be done and valid input data is lost. The pipeline circuit shown in Fig. 1 reduces the risk of data loss due to compression operation as long as there is a stage that does not contain valid data.

【0045】

FIGS. 2 and 3 show another embodiment of the present invention, which includes a circuit capable of performing compression and decompression operations in a logical embodiment and limiting the propagation of the acceptance signal of the preceding preceding stage. Although the circuit that realizes this embodiment is described in detail below, FIGS. 2 and 3 show the operating principle. Input data and acceptance signals are shown in FIGS. 2 and 3 as in the embodiment of FIG. 1 for ease of comparison. Therefore, processing stages E, D and B contain valid data D1, D2 and D3, respectively. The acceptance signal to stage F is low and data D4 is fed to the first processing stage A. In Figures 2 and 3, three lines connecting the adjacent processing stage pavilions are shown. The top of these three lines is the bus data line, the middle line is the line to which the active signal is transferred, and the bottom line is the line to which the acceptance signal is transferred. As in the previous embodiment, the acceptance signal to the stage F is low except for cycle 4. Further additional data D5 is supplied to the pipeline circuit in cycle 4.

【0046】

In FIGS. 2 and 3, each processing stage is represented by a block divided into two, indicating that each stage contains primary and secondary data storage elements. In Figures 2 and 3, the primary data storage is shown by the right half of each stage, which is for illustration purposes only. As shown in FIGS. 2 and 3, data is transferred from the primary storage element of that stage to the secondary storage element of the next stage in a given cycle as long as the acceptance signal to one stage is high. Therefore, in cycle 2, the data D1, D2, and D3 are shifted to the right or forward of the figure by only one stage because the acceptance signal to the processing stage F is low but the acceptance signal to the other stages is high. Data D4 is supplied to the first processing stage A. Up to this point, the pipeline circuit of the embodiment shown in FIGS. 2 and 3 operates in the same manner as the pipeline circuit of the embodiment shown in FIG. However, although the acceptance signal to stage F is low, the acceptance signal from stage F to E is high. Due to the secondary storage element, it is not necessary to propagate the low acceptance signal further upstream beyond stage F, as described below. By keeping the acceptance signal to stage E high, stage F signals readiness to accept new data. Since the stage F cannot transfer the data D1 in the primary storage element downstream in the cycle 3 (the acceptance signal to the stage F is low), the stage E stores the data D2 in the secondary storage of the stage F. Transfer to the element. The acceptance signal from stage F to stage E is set low because both the primary and secondary storage elements of stage F contain valid data that cannot be transferred. This indicates that the low acceptance signal is propagated upstream by only one stage for cycle 2. By the way, this acceptance signal had to be propagated upstream to stage C in the embodiment of FIG.

【0047】

Since stages A to E can transfer such data, the acceptance signal from these stages to the immediately preceding stage is set high. Therefore, the data D3 and D4 are shifted to the right by one stage and in cycle 4, these data are loaded into the primary data storage elements of stage E and stage C, respectively. Although stage E contains valid data D3 in its primary storage element, its secondary storage element can be used to store other data without the risk of overwriting the valid data.

【0048】

As in the previous embodiment, it is assumed that the acceptance signal to stage F becomes high in cycle 4. This indicates that the next stage device to which this pipeline sends data is ready to accept the data. However, the processing stage F sets its acceptance signal to low, indicating to stage E that stage F is not ready to accept new data. Note that the acceptance signal in each cycle indicates what happens in the next cycle, that is, whether the data is transferred or the data should stay in that position. When transitioning from cycle 4 to 5, data D1 is transferred from stage F to the next stage device and data D2 is shifted from the secondary storage element of stage F to the primary storage element, while data D3 in stage E is stage F. Not transferred to. The data D4 and D5 are transferred to the next stage as usual because the acceptance signal of the next stage is high.

【0049】

Comparing the states of the pipeline circuits in cycles 4 and 5, the provision of the secondary storage element expands the pipeline circuits in FIGS. 2 and 3 and increases the degree of freedom of the data storage element to which valid data should be supplied. is there. For example, in cycle 4, data blocks D1, D2 and D3 form a "hard wall" because they are not transferred until the acceptance signal to stage F is high. Once this acceptance signal goes high, data D1 is sent from the pipeline circuit, data D2 is shifted to the primary storage element of stage F, and the secondary storage element of stage F accepts data D2 of the next stage device. It can accept new data when it is not possible and the pipeline circuit has to recompress. This is shown in cycle 6. That is, the data D3 is shifted to the secondary storage element of the stage F, and the data D4 is transferred from the stage D to the stage E as usual.

【0050】

4, 5, 6 and 7 (referred to as FIG. 4 as a whole) show examples of preferred pipeline circuits according to the present invention. The pipeline circuit of this embodiment utilizes the circuit configurations of FIGS. 2 and 3 by using two-phase clocks having phases φ0 and φ1 that do not overlap each other. Although a two-phase clock is preferred, it is also possible to drive an embodiment according to the invention using a clock with three or more phases.

【0051】

In FIG. 4, each processing stage is represented by a two-part box indicating the primary and secondary storage elements. Although each stage is coupled by an effectiveness signal and a data line, only the acceptance signal is shown in FIG. 4 for ease of illustration. The change of state in any of the clock phases of the received signal is indicated by using the up arrow to indicate the change from low to high and by using the down arrow to indicate the change from high to low. .. The transfer of data from one storage element to another is indicated by a large white arrow. The effectiveness signal from the primary or secondary storage element of a stage is high as long as the storage element contains valid data.

【0052】

In FIG. 4, each cycle is shown to include the entire period of clock phases φ0 and φ1. Data is transferred from the secondary storage element shown as the left box of each stage to the primary storage element shown as the right box of each stage during clock cycle φ1 as described in detail below. Data is transferred from the primary storage element of the stage to the secondary storage element of the next stage during the clock cycle φ0. In the circuit of FIG. 4, the primary and secondary storage elements of each stage are connected by an internal receiving line, and the receiving signal is transferred in the same manner as the receiving signal is transferred from the processing stage to the processing stage.

【0053】

As shown in FIG. 4, in the phase φ1 of the cycle 1, the data D1, D2 and D3 shifted to the secondary storage elements of the stages E, D and B are shifted to the primary storage elements of each stage. At phase φ1 of cycle 1, the pipeline circuit exhibits the same configuration as shown in cycle 1 of FIGS. 2 and 3. As before, the acceptance signal to stage F is assumed to be low. However, as shown in FIG. 4, while the acceptance signal to the primary storage element of stage F is low, the acceptance signal to the secondary storage element is set high because this storage element does not contain valid data. To.

【0054】

Since the secondary storage element of stage F does not contain valid data, the acceptance signal from the secondary storage element of stage F to the primary storage element of stage E is set high. As before, since the primary storage element of stage F can accept data, the data of all upstream primary and secondary storage elements can be shifted downstream without overwriting the valid data. The shift of data from one stage to the next occurs in the next phase φ0 of cycle 2. For example, the effective data D1 contained in the primary storage element of stage E is shifted to the secondary storage element of stage F, and the data D4 is supplied to this pipeline circuit, that is, the secondary storage element of stage A.

【0055】

In the phase φ0 of cycle 2, the primary storage element of stage F does not yet contain valid data, so the received signal from the primary storage element of stage F to the secondary storage element remains high. In phase φ1 of cycle 2, the data is shifted to the right, that is, the data is shifted from the secondary storage element to the primary storage element at each stage.

【0056】

However, if the valid data is loaded into the primary storage element of stage F and the acceptance signal from the device downstream to stage F is still low, then the valid data D1 is overwritten or disappears in stage F. Data cannot be shifted to the secondary storage element. Therefore, the acceptance signal from the primary storage element to the secondary storage element of stage F is low. However, the data D can still be shifted to the secondary storage element of stage F. This is because this secondary storage element does not contain valid data and its acceptance output is high.

【0057】

Although the data can be shifted in all the preceding stages in the phase φ1 of the cycle 3, the data D2 cannot be shifted to the primary storage element of the stage F. However, once the valid data is loaded into the secondary storage element of stage F, stage F cannot transfer this data and its acceptance output is set to low. Assuming the incoming signal to stage F is low, the data upstream of stage F shifts between stages and within stages at each clock phase until the next valid data block D3 reaches the primary storage element of stage E. Is continuously done. As shown, this state occurs during phase φ1 of cycle 4.

【0058】

Data D3 is loaded into the primary storage element of stage E during phase φ5 of cycle 5. Since this data cannot be further shifted, the acceptance signal of the output of the primary storage element of stage E is set to low as the acceptance signal of the output of the primary storage element of E. Upstream data can be shifted as usual. It is assumed that the device connected downstream of the pipeline circuit in cycle 5 of FIGS. 2 and 3 can accept the output data of the pipeline. This downstream device then sets the acceptance signal to stage F high while the phase of cycle 4 is between φ1. The primary storage element of stage F can then shift the data to the right and accept new data. When data D1 is output during phase φ1 of cycle 5, the primary storage element of stage F no longer contains the data to be retained. During the phase φ1 of cycle 5, the secondary storage element is shifted to the primary storage element in the stage F of the data D2. The secondary storage element of stage F can thus accept new data and sets the acceptance signal to the primary storage element of stage E to high. The transfer of data within a stage is the transfer of data from its secondary storage element to the primary storage element, where both storage elements contain the same data, however, the data in the secondary storage element may be overwritten. No data loss occurs. This is because this data is also in the primary storage element. This also applies to data transfer from the primary storage element of one stage to the secondary storage element of the next stage.

【0059】

The acceptance signal to the primary storage element of stage F becomes low in phase φ1 of cycle 5. This means that stage F cannot output data D2 out of the pipeline circuit. Therefore, the stage F sets the acceptance signal from the primary storage element to the secondary storage element low and prohibits overwriting on the valid data D2. However, the data D2 stored in the secondary storage element of stage F can be overwritten without data loss. Then, the data D3 is transferred to the secondary storage element of the stage F during the phase φ0 of the cycle 6. Data D4 and D5 can be shifted downstream as usual. Once the valid data D3 is stored in the stage F together with the data D2, the secondary storage element cannot accept new data as long as the acceptance signal to the primary storage element of the stage F is low, and the acceptance signal to the stage E. Set to low.

【0060】

When the incoming signal from a device downstream of the pipeline changes from low to high and vice versa, this change does not need to be propagated upstream in the pipeline, but within the same stage or within the preceding stage. It may be propagated to the preceding storage element. Then, this change propagates upstream by only one storage element block for each clock phase.

【0061】

As this example shows, the concept of "stage" in the pipeline structure shown in FIG. 4 is somewhat sensory. Data is transferred from the secondary storage element to the primary storage element in the stage in the same manner as data transfer between stages, such as data transfer from the primary storage element of the upstream stage to the secondary storage element of the downstream stage. Therefore, unlike that shown in FIG. 4, the processing stage of the pipeline circuit is considered to consist of a primary storage element in which secondary storage elements are vertically connected. The concept of this primary and secondary storage element is a matter of how to label. In FIG. 4, the primary storage element can be said to be an output storage element. This is because these storage elements output data from them to the next stage or device. Further, the secondary storage element can be said to be an input storage element of the same stage.

【0062】

In the description of the embodiments of the present invention shown in FIGS. 1 to 4, data transfer under the control of the acceptance signal and the valid signal is described. By the way, it should be understood that each processing stage may process the data before the data transfer between the internal storage elements or the data transfer to the next stage. With reference to FIG. 4 again, each processing stage is defined as part of a pipeline circuit that includes input and output storage elements and is defined as processing the data stored in that storage element.

【0063】

The equipment downstream from the processing stage F of the pipeline circuit does not have to be another type of hardware circuit and may be part of another similar pipeline circuit. As shown below, valid data not only when the downstream storage elements are all filled with valid data, but also when one or more clock phases are required to complete data processing, or in one or both of the storage elements. The processing stage of the pipeline circuit can set its acceptance signal to low when generating. Also, it is not always necessary for a stage to simply transfer an acceptance signal based on as soon as it contains valid data that its downstream storage element cannot transfer. Rather, the acceptance signal itself is modified within the stage or by a circuit outside the stage to control data transfer between adjacent storage elements. The active signal can also be processed in an analog manner.

【0064】

The advantage of the two-line interface (the line corresponding to each of the effectiveness and the received signal) is that the pipeline circuit can be controlled without having to propagate the control signal to the first stage. In the embodiment shown in FIG. 1, for example, in cycle 3, stage F notifies stage E that data cannot be accepted, stage E notifies stage D of this, and stage D notifies stage C of this. If there are other stages containing valid data, this acceptance signal will be propagated further upstream in the pipeline circuit. In the embodiment of FIG. 4, in the cycle 3, the low acceptance signal is not propagated upstream from the stage E and reaches the primary storage element thereof.

【0065】

As described below, this embodiment can achieve this flexibility without significantly increasing the area of the silicon substrate required by design. That is, each latch of the pipeline circuit used for data storage is formed by one transistor. This transistor is efficiently laid out on a silicon substrate. Two more latches and a small number of gates are added to process the acceptance and validity signals. These signals are latched by a data latch provided on each processing stage.

【0066】

FIG. 8 shows the hardware structure that realizes the processing stage shown in FIG. For example, 8-bit data is transferred along the pipeline. The two-line interface according to the present invention can be used for data buses of any size, but the width of the data bus can be changed from one stage to the next when necessary. Such an interface can also be used to process analog signals.

【0067】

This interface is preferably controlled by two phase non-overlapping clocks, but other normal timing circuits can also be used. These clock signals are shown as PH0 and PH1 in FIGS. 8-14. The input data whose line is shown for each clock signal in FIG. 8 is supplied to the pipeline circuit via the multi-bit data bus IN-DATA, and is supplied to the next pipeline stage or the receiving circuit via the output data bus OUT-DATA. Transferred to. The input data is first loaded into the continuous input latch LDIN in the manner described below. This latch constitutes the above-mentioned secondary storage element. In the embodiment of FIG. 8, the Q output of all latches follows its D input. That is, the latch is loaded when the clock input is high, that is, at the logical "1" level. Also, the Q output holds that value. In other words, the Q output is latched at the trailing edge of each clock signal. Each latch has one of the clock signals PH0 or PH1 as its clock (see FIG. 9). Alternatively, the case of the logical product of one of the clocks PH0 and PH1 and one logic signal is also conceivable. The apparatus according to the present invention may be provided with a latch that latches the rising edge of the clock signal, or another latch circuit may be used as long as an appropriate timing of latch operation is ensured.

【0068】

The output data from the input data latch LDIN is fed to any combination logic circuit B1. This combination logic circuit converts the output data from the input latch LDIN into intermediate data, and this intermediate data is loaded into the output data latch LDOUT. The output data latch LDOUT includes the primary storage element described above. The output from the output data latch LDOUT is supplied to any combinational logic circuit B2. Then, the data is transferred to the next downstream device as output data OUT-DATA. This downstream device is a processing stage in another pipeline or another device connected to this pipeline circuit.

【0069】

Each processing stage of the pipeline circuit includes an effective (evaluation) input latch LVIN, an effective output latch LVOUT, an accept input latch LAIN and an accept output latch LAOUT. Each of these four latches is preferably a simple single stage latch. The outputs of the latches LVIN, LVOUT, LAIN and LAOUT are QVIN, QVOUT, QAIN and QAOUT, respectively. The output signal QVIN from the effective input latch is transferred as an input to the effective output latch LVOUT or via an intermediate logic circuit for signal conversion.

【0070】

Similarly, the active output signal QVOUT of one processing stage is fed directly to the input of the active input latch QVIN of the next processing stage or transferred via an intermediate circuit or logic circuit that converts the active signal. This output QVIN is transferred to a logic gate (described later). The output of this logic gate is connected to the input of the receiving input latch LAIN. The output QAOUT of the receiving output latch LAOUT is supplied to a similar logic gate (described later) via another logic gate or the like.

【0071】

As shown in FIG. 8, the output valid signal QVOUT forms an OUT-VALID signal, which is received as an IN-VALID signal by the next stage processing stage or is connected to the next stage of the pipeline circuit. On the other hand, the existence of valid data is shown in order. The data acceptance preparation of the next stage processing stage is indicated to each stage as a signal OUT-ACCEPT, and this signal is preferably transferred as an input of the acceptance output latch LAOUT via a logic circuit described later. Similarly, the output QAOUT of the receiving output latch LAOUT is preferably supplied as an input to the receiving input latch LAIN via a logic circuit described later.

【0072】

The output signals QVIN and QVOUT from the effectiveness latches LVIN and LVOUT are combined with the acceptance signals QAOUT and OUT-ACCEPT, respectively, and become inputs to the acceptance latchs LAIN and LAOUT. In the circuit shown in FIG. 8, these input signals are formed as NAND logic of each effectiveness signal QVIN, QVOUT and the inverse logic of each received output signal QAOUT, OUT-ACCEPT. The normal logic gates NAND1 and NAND2 perform NAND operation, and the inverters INV1 and INV2 form the inversion logic of each received signal.

【0073】

As is well known in the field of digital circuit design, the output from a NAND gate is logic "1" when any or all of its input signals are in the logic "0" state. Therefore, the output from the NAND gate becomes logical "0" only when all of its inputs are in the logical "1" state. Also, as is well known, the output of a digital inverter such as INV1 is logical "1" when its input signal is "0", and its output is logical "0" when its input signal is logical "1". ".

【0074】

Therefore, the inputs of NAND gate D1 are QVIN and NOT (QAOUT). Here, "NOT" indicates logical negation. Using known techniques, the input of the receiving latch LAIN is decomposed as follows. That is, NAND (QVIN, NOT (QAOUT)) = NOT (QVIN) or QAOUT Will be.

【0075】

In other words, when the signal QVIN is "0" or the signal QAOUT is "1" or both QVIN and QAOUT are 0 and 1, the inverter INV1 and NAND gate NAND1 are logical "1". Gate NAND1 and inverter INV1 are formed by a single OR gate in which one input connects directly to the output of the QAOUT of the receiving latch LAOUT and the other input connects the output signal of the valid input latch LVIN to the inversion of the QVIN. To. As is well known in the field of digital circuits, as an effectiveness latch and an accepting latch, the latch has two outputs, Q and NOT (Q), ie Q and its logical inversion. If such a latch is selected, one input of the OR gate is directly connected to the output NOT (Q) of the effectiveness latch LVIN. The gate NAND1 and the inverter INV1 can be formed by using the usual well-known techniques. However, depending on the latch circuit used, it is more efficient to provide a gate NAND1 and an inverter INV1 using a latch without inverting output. These latches can be efficiently provided on the silicon substrate. Other known circuits can be used to generate the Q signal and / or its inversion.

【0076】

Data and Validity Latch LDIN, LDOUT and LVIN and LVOUT take their respective data inputs when their clock signals (PH0 on the input side and PH1 on the output side) and the output on the same side of the receiving latch are logical "1" Loading. Therefore, the output of the clock signal (PH0 and each receiving latch (LAIN in this case) for the input of the latch LDIN and LVIN) is used in the mode of logical product. At this time, both signals are of logic "1". Sometimes loaded.

【0077】

In CMOS circuit latch applications, the AND operation that controls loading via the CK pin or enable input is conventional by coupling the respective enable input signals (eg PH0 and QAIN for latch LVIN and LDIN). It can be easily formed by the method. This loading is the loading of a MOS transistor connected in series with the input line of the latch to the gate. Further, it is not necessary to use an AND gate that may cause a timing problem due to propagation delay in high-speed operation. Therefore, the AND gates shown only show the logic actions taken to generate the enable signals for the various latches.

【0078】

The data latch LDIN loads the input data only when both PH0 and QAIN are "1". Then, when one of these two signals becomes 0, this data is latched. Only one of the clock phase signals PH0 and PH1 is used for the input (and output) data and effectiveness latch clocks of the pipeline stage, and the other of these clock phase signals is directly of the receiving latch clock on the same side. Used for In other words, the receiving latch on one side (input or output) of the pipeline stage is preferably clocked out of phase with respect to the data latch and effectiveness latch on the same side. For example, PH1 is used to clock the receiving input latch, while PH0 is used to generate the CK with the clock signal for the data latch LDIN and the effectiveness latch LVIN.

【0079】

As an example of the effectiveness of the two lines according to the present invention and the operation of the pipeline circuit extended by the accepting circuit, there is initially no valid data at the input from the preceding pipeline or transmission device of the pipeline circuit to the pipeline circuit. And. In other words, the validity input signal IN-VALID to the illustrated processing stage does not change to "1" because the system was reset immediately before. Furthermore, since the system was just reset, some clock cycles occur and the circuit reaches a stable state. The validity input signal QVIN from the validation latch LVIN is therefore loaded as 0 in the next positive period of clock PH0. The input to the receiving input latch LAIN fed through gate NAND1 or other equivalent gate is therefore loaded with the clock signal as "1" in the next positive period of PH1. In other words, because the data in the data input latch LDIN is not valid, the processing stage signals that it is ready to accept the input data. This is because the processed data does not hold data that deserves protection. In this embodiment, the signal IN-ACCEPT is used to enable the data latch and effectiveness latch LDIN and LVIN. At this time, since the signal IN-ACCEPT is 1, these latches act as normal transmissive latches, and as soon as the clock signal PH0 becomes 1, all the IN-DATA bus-like data simply becomes. Loaded into the data latch LDIN. Of course, this invalid data is loaded into the next data latch LDOUT of the next processing stage as soon as the output QAOUT from the receiving latch becomes "1".

【0080】

In other words, it accepts or loads any data supplied in the next positive period of the clock signal unless the data latch contains valid data. On the other hand, such invalid data is not loaded into any processing stage where the acceptance signal from the corresponding acceptance latch is low or 0. In addition, the output signal from the effectiveness latch (which forms the effectiveness input signal for the next effectiveness latch) remains 0 as long as the signal IN-VALID (ie QVIN) to the corresponding effectiveness latch is low.

【0081】

This is indicated by the active signal IN-VALID rising to 1 when the input data to the data latch is valid. The output of the corresponding effectiveness latch rises to "1" at the next rising edge of the clock phase signal. For example, when the validity input signal QVIN of the LVIN becomes high at the rising edge next to the clock phase signal PH0, the validity input signal QVIN of the latch LVIN becomes 1.

【0082】

Here, it is assumed that the data input latch LDIN contains valid data. If the output latch LDOUT is ready to accept new data, its acceptance signal QAOUT is "1". In this case, in the next positive period of the clock signal PH1, both the data latch LDOUT and the validity latch LVOUT are enabled, and the data latch LDOUT loads the data at its input. This causes the other clock signal to occur before the next rising edge of PH0. This is because the clock signals do not overlap each other. At the next rising edge of PH0, the next data latch (LDIN) does not latch new input data from the preceding processing stage until the data output latch LDOUT safely latches the data supplied by the latch LDIN.

【0083】

A similar sequence is made by a pair of adjacent data latches (within one stage or between adjacent stages) that can accept data. This is because these latches operate on the clock of every other phase. A data latch that cannot accept new data because it contains valid data that cannot be transferred downstream lowers the output accept signal (QA output of the accept latch LA) and its data latch LDIN or LDOUT is not loaded. In other words, as long as the receiving signal (output of the receiving latch) on the input or output side of a certain processing stage or a certain stage is low, the corresponding data latch is not loaded.

【0084】

FIG. 8 shows a state of reset included in a preferred embodiment of the present invention. In the illustrated example, the reset signal NOTRESET0 is fed to the inverting reset input R of the effectiveness output latch LVOUT (in which case the inverting is indicated by a small circle). As is well known, this means that the effectiveness latch LVOUT outputs "0" whenever the reset signal NOTRESET0 becomes "0". The advantage of resetting the latch when the reset signal is low, or 0, is that stopping transmission will reset the latch. Therefore, when valid transmission begins, they are all "(NULL)", that is, in the reset state, and the reset signal is high. Therefore, the reset signal NOTRESET0 must be high in order to act as a digital on / off switch and activate the pipeline circuit.

【0085】

It should be noted here that it is not necessary to reset all the latches in the pipeline circuit that hold the valid data. In Figure 8, the effectiveness input latch LVIN is not directly reset by the reset signal NOTRESET0 but is indirectly reset. Here, it is assumed that the reset signal NOTRESET0 drops to 0. Then, the effectiveness output signal QVOUT also drops to 0 regardless of the previous state, and the input to the receiving output latch LAOUT (gate NAND2) becomes high. The acceptance signal QAOUT becomes "1". This 1 signal QAOUT is transferred as 1 to the input of the accept input latch LAIN regardless of the state of the valid input signal QVIN. The acceptance signal QAIN then rises to "1" at the next rising edge of the clock signal PH1. On the other hand, if the validity signal IN-VALID is correctly reset to 0, the output of the validity latch LVIN becomes 0 at the rising edge next to the clock signal PH0. This is as if the effectiveness latch LVIN was reset directly.

【0086】

In the illustrated example, it is only necessary to reset the effectiveness latch on only one side of each processing stage (including the final processing stage) in order to reset all the effectiveness latches. In fact, in various applications it is not necessary to reset all effective latches. If the reset signal NOTRESET0 is guaranteed to be low for more than one complete cycle of both clocks PH0 and PH1, "automatic reset" (propagation of the reset signal upstream) is the upstream processing stage. It occurs for the effectiveness latch of. In fact, if the reset signal is kept low for as many clock phase cycles as there are processing stages, then only the effectiveness output latch of the final processing stage needs to be reset directly.

【0087】

9 and 10 (collectively referred to as FIG. 9) show the relationship between the non-overlapping clock signals PH0 and PH1, the effect of the reset signal, and the effectiveness signal between the two sides of the pipeline circuit shown in FIG. It is a timing diagram showing the retention and transmission of data for different arrangements of received signals. In the example shown in the timing chart of FIG. 9, it is assumed that the outputs from the data latch LDIN and LDOUT are transferred without further processing by the intervening logic blocks B1 and B2. It should be understood that this is for illustration purposes only and that any form of logic circuit may be provided between the data latches of successive processing stages or between the outputs and inputs of a single processing stage. Values actually shown as input data, such as the HEX data word aa or 04, are merely examples. As mentioned above, the input data bus may be of any size and may be analog as long as the data latch or other storage device can accept or latch or store bits or whole of the input word.

【0088】

Preferred data structure-token In the simple application shown in FIG. 8, each stage processes all input data. This is because there is no control circuit that prohibits the input data from passing through the combination logic blocks B1, B2, and the like. To give greater flexibility, this example includes a data structure that uses "tokens" to distribute the data throughout the system. Each token consists of consecutive binary bits, which are divided into blocks of one or more token words and of three types: address bits (A), data bits (D) and additional bits (E). It has become either. As an example, assuming that data is transferred as a word over an 8-bit bus with a 1-bit additional bitline, an example of a four-word token for transmission is as follows.

【0089】

First word: EAAADDDDD Second word: EDDDDDDDD Third word: EDDDDDDDD Fourth word: EDDDDDDDD It should be understood here that the additional bit E is used as an additional bit for each data word and that the address area is allowed to have various lengths and is preferably transferred immediately after the additional bit of the first word.

【0090】

Therefore, the token consists of one or more words of (binary) digital data. These words are transmitted in a procedure and preferably in parallel. Most of these transmission methods are not essential and serial data transmission is possible using known techniques. As shown in the example, each token preferably initially has an address area (a string of A bits) indicating the type of data contained in the token. In many applications, a single word or part of a word is sufficient to transmit an address area, but in the present invention it is sufficient for a processing stage that receives and decodes the entire address area. This is not essential as long as the corresponding processing stage includes a logic circuit that can store a portion that represents a portion of the long address area.

【0091】

It should be noted that no wires or registers are needed to carry this address area. This address area is transmitted by using data bits. As described below, the processing stage is not slowed down unless it is intended to be activated by this address region. This processing stage can transfer tokens without delay.

【0092】

The rest of the data after the address area in the token is not suppressed by using the token. These data bits D take in any value and the meaning given to these bits is not important here. The number of data bits D added after the address area can be as long or short as necessary, and it is possible that the number of data words in different tokens will vary widely. The address area and additional bits are used to transmit the control signal to the processing stage. The number of words in the data field (column of D bits) can be changed arbitrarily depending on the information in the data field. Therefore, the following description is about how to use the address and the additional bit.

【0093】

Tokens are a data structure that is especially useful when many circuit blocks are connected to each other in a relatively simple structure. The simplest structure is, for example, a pipeline processing step as shown in FIG. However, this token is not only used for pipeline structures. Here, it is assumed that each block means a complete pipeline stage. In the pipeline circuit of Figure 1, data flows from left to right in the figure. Then, the input data is supplied to the processing stage A. This stage A can transform the input data and transmit the transformed or untransformed data to stage B. This transformation or modulation can be complex, and the number of data flowing into each stage as a whole may not be equal to the number flowing out.

【0094】

On the other hand, it is desirable that the processing stage A can transmit information even though these stages are not directly connected to the processing stage C but are connected via the stage B. One advantage of tokens is that they can carry out such communication. Any processing stage that does not recognize the token will transfer it to the next block unchanged. According to this example, additional bits are transmitted in each token along with the address and data area, so the processing stage can transfer the token (which can be of any length) without its address coding. According to this example, a token with a high additional bit (logical 1) is followed by a dependent word that is part of the same token. This word has an additional bit, which indicates that there are additional token words in the token. When a processing stage receives a token word containing an additional bit of low, it is known that the stage is the final word of the token. The next word is presumed to be the first word of the new token.

【0095】

It should be noted that although a pipeline stage with a simple structure is particularly useful, this token can also be applied to processing circuits with a more complex structure. An example of such a more complicated processing circuit is shown below. According to this embodiment, it is not always necessary to indicate the last word of a given token by setting the additional bit "0" using the state of the additional bit. A desirable variant is to show the first word of the token rather than the last word by removing the additional bits and appropriately modifying the coding hardware. The advantage of using additional bits to indicate the last word of the token rather than the first word is that it is useful in transforming the behavior of the circuit block as soon as the token has additional bits. An example of this is a token that activates a processing stage that processes a video quantization value stored in a quantization table (usually a memory device). For example, this quantization table contains 64 8-bit binary numbers.

【0096】

QUANT-TABLE is supplied to this quantization stage to load a new quantization table into the quantization stage of the pipeline circuit. In this case, the token consists of, for example, 65 token words. The token word begins with the code "QUANT-TABLE", which is followed by 64 words, which are the integer values of the quantization table. When encoding video data, it is necessary to transmit such a quantization table. To do this, QUANT-TABLE tokens are fed to the quantization stage without additional words. Upon receipt of this token, when the first word of the additional bit is low, the quantization stage can read its quantization table and form a QUANT-TABLE token containing 64 quantization table values. be able to. When the additional bit (which was low) of the first word changes and becomes high, the token continues to be in the high state of the additional bit, and the additional bit of low on the 64 quantization table values indicates the end of the new token. This state continues until it is released. This is a normal response and is processed and coded in bit style.

【0097】

In this example, the quantization stage loads a new quantization table into its own memory or reads the table as soon as it has an additional bit set with the first word of the QUANT-TABLE token. The choice as soon as the additional bits are used to indicate the first or last word of the token depends on the system in which the pipeline circuit is used. In any case, according to the present invention, both options are possible.

【0098】

Another option for preferred additional bits is to include a length count at the beginning of the token. For example, such a configuration is valid if the token is very long. For example, assuming a typical token length is 1000 words, the token requires 1000 additional bits to include all the additional bits when using the additional bit configuration. However, encoding the token length in binary format requires only 10 bits.

【0099】

Although we may use long tokens, experience has shown that most of the time we use short tokens. Here, a preferable additional bit configuration is advantageous. If the token has a single word length, a single bit is needed to indicate this. However, the count configuration requires the same 10 bits. The disadvantages of the length count configuration are as follows.

【0100】

(1) Inefficient for short tokens: (2) There is a maximum length limit for tokens (1023 words cannot be counted for 10 bits): (3) What the token length must be known before counting (it needs to be known at the beginning of the token): (4) Each block of the circuit that handles tokens must have word-counting hardware: and (5) If the count is disturbed (due to a data transmission error, etc.), it is not clear as soon as recovery can be achieved.

【0101】

The advantages of the additional bit configuration according to the present invention are as follows. (1) The processing stage of the pipeline does not need to include a circuit that decodes all tokens, and unrecognized tokens are transferred correctly just by considering the additional bits: (2) The coding of the additional bits is the same for all tokens: (3) There is no limit on the length of tokens: (4) Efficient additional bit configuration for short tokens (with respect to the token length): and (5) Error recovery is done naturally.

【0102】

If the additional bits are disturbed, one random token is formed. This is the case when the additional bit is disturbed from "1" to "0". Also, when the additional bit is disturbed from "0" to "1", the token is extinguished. In addition, token issues are localized. Therefore, the correct operation is automatically performed after this. The length of the address area can also change. This is a great advantage. This is because it allows you to push very common tokens into a very small number of words. This is very important in video data pipeline circuits. This is because this ensures that all processing stages continue to operate in all bands.

【0103】

According to this embodiment, addresses are selected to make the length of the address area variable, and short addresses following random data are never confused with long addresses. The preferred technique for coding the address region (which also acts as the code that activates the desired pipeline processing stage) is the well-known technique first described by Huffman and is referred to as the "Huffman code". .. Huffman coding technology is well known in the field of digital design, but the following examples provide an overall background.

【0104】

The Huffman code consists of multiple words consisting of a sequence of symbols. (Symbols are usually binary digits in digital devices such as the present invention.) This codeword has various lengths, and the special property of Huffman codeword is that longer codewords form shorter codewords. Is chosen so that it does not start with. According to the present invention, the address area of the token is preferably chosen to use a known (but not necessarily) Huffman coding technique.

【0105】

Also, according to this embodiment, the address area starts in the MSB of the first word of the token. (Here the MSB designation is optional and this configuration can be modified to include the various MSB designations.) The address area continues in the lower contiguous bits. If the address of a token needs to be greater than one token, the least significant bit of one word in the address area follows the most significant bit of the next word, the MSB. The minimum length of the address area is 1 bit.

【0106】

A known hardware configuration is used to generate the token used in this example. Such a hardware configuration is a microprogram state machine, and of course, a device such as a known microprocessor can also be used. The basic advantage of token construction by this example is adaptability to unexpected needs. For example, if a new token were introduced, this would only affect the processing stages of a very small number of pipelines. That is, the most likely cases are as follows. That is, when two processing stages or blocks are affected, one block first generates a token and the newly transformed block processes this new token. That is, there is no need to deform the processing stages of other pipelines. Moreover, these other processing stages can handle new tokens without any design changes. This is because their circuit does not recognize the token and allows the token to pass through without any transformation.

【0107】

It is a clear advantage that it has no effect on the existing processing stages in this embodiment. That is, a design improvement in the chipset can have no effect on some chips. This is advantageous from both the user's point of view and the chip maker's point of view. Also, even if all chips need to be redesigned, it is still quite advantageous in terms of shorter time to market than before. This is because the same circuit design can be reused. Such a situation is likely to occur as the degree of integration increases and the number of chips in the system drop increases.

【0108】

Now consider the case where the set of tokens needs to be a two-word address. Even in such a case, it is not necessary to modify the conventional design. The token decoder in the processing stage of the pipeline tries to decrypt the first word of the token, and the processing stage does not recognize the token. Then, the processing stage transfers this using the additional bit without adding any processing to the token. And this processing stage also does not decode the second word (even if it contains an address bit). This is because this processing stage "assumes" that the second word is part of the token's data area that it did not recognize. Often the processing stage of the pipeline or the combined circuit blocks transform the token. This is usually a variant of the token's data domain, which is not always required. In addition, many datawords in the token are often transformed by removing certain datawords or adding new datawords. Also, in some cases, the token may be completely removed from the token column.

【0109】

In most applications, the processing stage of the pipeline is activated by several tokens to decrypt them. Then, the processing stage passes the other tokens without recognizing them and without any modification. Often only one token is decrypted. This is a data token word. In many applications, the behavior of a processing stage depends on its past behavioral results. The "state" of a processing stage depends on the previous state. In other words, the processing stage depends on the stored state information. In other words, the processing stage must retain information about its history before one or more clock cycles. Therefore, the present invention is effective when used in a pipeline including a processing stage of such a "state machine", and is also useful when the data path latch is a simple pipeline latch.

【0110】

The applicability of the two-line interface according to this example in a circuit containing such a "state machine" is a significant advantage of this example. Especially when the data path is controlled by a state machine, the two-line interface technology described above is used to ensure that the steps associated with the data being controlled in the device's "current state" pipeline remain. ..

【0111】

FIG. 11 is a simplified block diagram of an example circuit included in the pipeline processing stage for decoding the token address area. This block diagram shows a pipeline processing stage with the characteristics of a "state machine". Each word of the token has an additional bit, which is high when there are still words in the token and low when this is the last word in the token. If this is the last word of the token, the next valid data word is the start of a new token, so its address must be decrypted. The decision whether to decrypt or decode the token address of a given word is made by knowing the value of the previous additional bit.

【0112】

For simplicity, this two-line interface (including the accept signal and effectiveness signal and latch) is not shown and all details that make up the circuit reset are omitted. As before, 8-bit datawords are used for excitation. This excited pipeline processing stage delays data bits and additional bits by one pipeline stage. This processing stage decodes the DATA token, and when the first word of the DATA token appears in the output of the circuit, the signal "DATA-ADDR" is generated and set to high. The latch LDIN and LAOUT delay the data bits, each of which is repeated eight times for the eight data bits used in this example (corresponding to the 8-input and 8-output latches). Similarly, the additional bits are delayed by the additional bit latches LEIN and LEOUT.

【0113】

In this example, a latch LEPREV is provided to store the state immediately before the additional bit. The value of the additional bit is loaded into the latch LEIN and loaded into the latch LEOUT at the next rising edge of the clock phase signal PH1. The latch LEOUT thus contains the value of the current additional bit, however, this is only during the second half of the two-phase clock. However, the latch LEPREV loads the value of this additional bit at the next rising edge of the clock signal PH0. The value of this additional bit is the same as the signal that enables the additional bit input latch LEIN. The output QEPREV of LEPREV holds the value of the additional bit during the previous clock phase PH0.

【0114】

The 5-bit data word output and non-inverting output MD "2" from the inverted Q output of the latch LDIN are combined with the previous value QEPREV of the additional bits by the logic gates NAND1, NAND2 and NOR1. The operation of these gates is well known in the field of digital circuits. Here, the display of N-MD "m" indicates the logical inversion of bit m of the intermediate data word MD "7: 0". Using known Boolean algebra techniques, the following is shown. That is, the output signal SA (NOR1 output) from the logic block has the previous value of the additional bit 0 (QREV = 0), and the output of the non-inverting output Q of the latch LDIN (original input word) 000001xx. That is, the five high-order bits MD "7-MD" 3 "bits are all" 0 ", the bit MD" 2 "is" 1 ", and the 1st and 0th bits are arbitrary values. It becomes high (1) when taking.

【0115】

Therefore, there are four data words with SA and the output of the address signal latch LADDR supplied as input high (there are four substitutions of "xx"), in other words, this processing stage is 4 When one of the two possible tokens was supplied, and the previous value of the additional bit was 0, that is, the last data word was the last word in the previous column of tokens, that is, the current token Generate an activation signal (DATA-ADDR = 1) when it is the first word of this time.

【0116】

When the signal QPREV from the latch LEPREV is low, the value at the output end of the latch LDIN is the first word of the new token. Gates NAND1, NAND2 and NOR1 decrypt the DATA token (000001xx). This address decoding signal SA, however, is delayed by the latch LADDR, and the signal DATA-ADDR has the same timing as the output data OUT-DATA and OUT-EXTN.

【0117】

Figure 12 shows another example of the state-dependent pipeline processing stage, which produces the signal LAST-OUT-EXTN, which indicates the previous value of the output add-on bit OUT-EXTN. One of the two enable signals fed to the CK input of the current add-bit latch and the previous add-bit latch LEOUT and LEPREV is extracted from gate AND1. These latches load new values when the data is valid and accepted. That is, when the outputs of the effectiveness latch LVOUT and the acceptance latch LAOUT are both high. In this way they retain valid additional bits and do not load suspicious values with invalid data.

【0118】

In the circuit shown in FIG. 12, the two-line enable / accept logic includes gates OR1 and OR2, which receive an input signal consisting of a downstream accept signal and an inverted output of the effectiveness latches LVIN and LVOUT. Such a configuration shows that the gates NAND1 / 2 and INV1 / 2 in FIG. 8 can be replaced if the latch has an inverted output. This circuit shows a simple example of a "state-dependent" pipeline processing stage, but since it depends on the state of only a single bit, the following can be said in this example. That is, all latches holding state information are updated only when they are actually transferred between the pipeline processing stages, that is, when the data is valid and accepted by the next stage. Of course, we must ensure that such latches are reset correctly.

【0119】

The tokens formed and used by this embodiment have some advantages over the coding techniques of data transmission over conventional pipelines. The first is that the tokens mentioned above allow address regions of various lengths (Huffman coding can be used) to enable efficient supply of common tokens.

【0120】

The second point is that the token length coding correctly processes the end of the token (ie the beginning of the next token), even if the token is not recognized by the decoder in the processing stage of the given pipeline. That is. (This process also includes simple transmission.) The third point is that the processing rules and hardware structure of unrecognized tokens (that is, they are passed through untransformed) can be exchanged between processing stages with 1 and distant downstream processing stages that are not adjacent to each other. Is to do. This increases the expandability and efficient applicability of pipeline circuits. This is because future changes are possible without the need for major design changes to existing pipeline stages. This token is particularly useful when used with the two-line interface described above and below.

【0121】

13 and 14 (hereinafter collectively referred to as FIG. 13) are block diagrams of a pipeline processing stage having the following functions. If we process this stage or a given token (known as the DATA token in this example), we duplicate each word of this token, with the exception of the first case, which includes the address area of the DATA token. On the other hand, if this stage processes other types of tokens, this processing stage deletes each word. The effect is that only DATA tokens appear in the output and each word in these tokens is repeated twice.

【0122】

Each part of the circuit shown here is the same as that of the simple structure shown in Figures 8, 11 and 12. This example shows the following advantages: That is, even more complex pipeline circuits can enjoy the same benefits of flexibility. This is because the same two-line interface is used with little change.

【0123】

The data duplication stage shown in Figure 13 is just one example of the various types of operations that the pipeline processing stage can perform. This "duplication stage", however, refers to a processing stage that forms a "bottleneck", and the pipeline circuits according to this embodiment pack together.

【0124】

The above-mentioned "bottleneck" stage can be a processing stage that requires a relatively long operating time and generates more data than the received data. This example shows that the two-line accept / effective interface can be applied very easily in various applications. The replication stage in FIG. 13 contains two latches REIN and REOUT. These latches latch the states of the additional bits at the input end and the output end of the processing stage, respectively, as in the example shown in FIG. As shown in FIG. 13, the input add-on latch LEIN is clocked in synchronization with the input data latch LDIN and the validity signal IN-VALID.

【0125】

The various latches included in the replication stage are shown in the table below in combination with their outputs for ease of understanding. Latch Output Labels Latch Output LDIN MID_DATA LDOUT OUT_DATA LEIN QIN LEOUT OUT EXTN LAIN QAIN LAOUT QAOUT LI1 QI1 LO1 QO1 LI2 QI2 LO2 QO2 = DATA_TOKEN LI3 QI3 LO3 QO3 = NOT DPULICATE In the replication stage, the output from the data latch LDIN forms intermediate data, which is referred to as MID-DATA. This intermediate data word is loaded into the data output latch LDOUT only when the intermediate acceptance signal (indicated as MID-ACCEPT in FIG. 13) is set high.

【0126】

In FIG. 13, the circuitry shown below the acceptance latches LAIN and LAOUT shows the circuitry added to the pipeline structure to generate the various internal control signals used to repeat the data. These circuits include a DATA-TOKEN signal indicating that the circuit is currently processing a valid data token and a NOT-DUPLICATE signal used for data replication control. Now, when the circuit is processing a data token, the NOT-DUPLICATE signal described above changes between the high and low states so that each word in the token is repeated once (not more than once). If the circuit is not processing a valid data token, the signal NOT-DUPLICATE is kept high, meaning that the token word is not replicated.

【0127】

In FIG. 13, the upper 6 bits of the 8-bit intermediate data word and the output signal QI1 from the latch LI1 form the inputs of the logic gates NOR1, NOR2, and NAND18. The output signal from gate NAND18 is labeled S1. Using known Boolean algebra, it can be shown that the signal S1 is "0" only in the following cases. That is, the output signal QI1 is "1" and the MID-DATA word has a structure of "000001xx". That is, in such a structure, the upper 5 bits are all "0", the bits MID-DATA "2" are "1", and the bits of MID-DATA "1" and MID-DATA "0" have arbitrary values. Have. The signal S1 thus acts as a token identification signal and is low only when the signal MID-DATA has a predetermined structure and the output of the latch LI1 is 1. The characteristics of the latch LI1 and its output QI1 are described below.

【0128】

Latch LO1 serves to latch the final value of the intermediate additional bit (labeled "MID-EXTN" and signal S4). Then, this latch LO1 loads this value into the latch LI1 at the next rising edge of the clock phase PH0. The output of the latch LI1 is bit QI1, which is one of the inputs to the token decoding logic group that forms the signal S1. The above-mentioned signal S1 becomes 0 only when the signal QI1 is 1 (and the signal MID-DATA has a predetermined structure). Therefore, the signal S1 becomes "0" when the last additional bit indicating that the previous token has ended is in the "0" state. Therefore, the MID-DATA word is the first data word for the new token.

【0129】

Latch LO2 and LI2 together with Nandgate NAND20 and NAND22 form a storage means for the signal DATA-TOKEN. Under normal conditions, the signal QI1 at the input end of NAND20 and the signal S1 at the input end of NAND22 are both logic "1". Boolean algebra shows that: That is, in this state, these Nandgates act as inverters. That is, the signal QI2 from the output of the latch LI2 is inverted at NAND20 and then inverted again by NAND22 to form the signal S2. In this case, the signal S has the same value as QI2 because two logic inversions are made in this passage.

【0130】

Also, the signal DATA-TOKEN at the output end of latch LO2 forms the input of latch LI2. As a result, the signal DATA-TOKEN remains in that state (either "0" or "1") as long as both QI1 and S1 remain high. This is correct though the clock signals PH0 and PH1 are clocking latches LI2 and LI2, respectively. The value of DATA-TOKEN can change only when one or both of the signals QI1 and S1 are 0.

【0131】

As described above, the signal QI1 becomes 0 when the previous additional bit was 0. Therefore, the signal QI1 is 0 whenever the value of MID-DATA is the first word of the token, that is, it includes the address area of the token. In this state, the signal S1 is either "0" or "1". As mentioned above, if the MID-DATA word has a given structure indicating a "DATA" token in this example, the signal S1 is "0". If the MID-DATA word has any other structure, i.e. indicates that the token is not a DATA token but another token, then S1 is "1".

【0132】

When QI1 is 0 and S1 is 1 indicating that it is a token other than a data token, the output of NAND20 is 1, as is well known in the field of digital circuits. ". Nandgate NAND22 inverts this and signal S2 is therefore 0. As a result, this value of "0" is loaded into the latch LO2 at the start of the next clock phase PH1 and the DATA-TOKEN signal becomes "0", indicating that the circuit is not processing the data token.

【0133】

If QI1 is "0" and S0 is "0" to indicate that it is a data token, then the signal S2 is "1" (the value of the other input from the output of NAND20 to NAND22). Regardless of). As a result, the value of "1" is loaded into the latch LO2 at the start of the next clock phase PH1, and the DATA-TOKEN signal becomes "1", indicating that the circuit is processing the data token.

【0134】

The NOT-DUPLICATE signal (output signal QO3) is similarly loaded into latch LI3 at the next rising edge of clock PH0. The output signal QI3 from the latch LI3 is combined with the output signal QI2 of the gate NAND24 to form the signal S3. As before, according to Boolean algebra, signal S3 is "0" only when both signals QI2 and QI3 have a value of "1". If the signal QI2 becomes "0", that is, the DATA-TOKEN signal becomes "0", the signal S3 becomes "1". In other words, if there is no valid data token (QI2 = 0) or the data word is not duplicated (QI3 = 0), the signal S3 will be high.

【0135】

Here, it is assumed that the data token signal remains high for one or more clocks. The output signal QO3 is 0 and 1 because the NOT-DUPLCATE signal (QO3) is returned to the latch LI3 and inverted by the gate NAND24 (because the other input QI2 is kept high). Change between. However, if there is no valid data token, the signal QI2 is 0 and the signal S3 and output QO3 are kept high until the DETA-TOKEN signal becomes 1 again.

【0136】

The output QO3 (NOT-DUPLICATE signal) is also fed back, and the logic gates NAND16 and INV16 (forming an and gate) set the output to "1" only when the signals QA1 and QO3 both take a value of "1". Combined with the output QA1 from the receiving latch LAIN. In FIG. 13, the outputs of gate NAND16 and gate INV16 from the and gate form the accept signal IN-ACCEPT used in the two-wire interface structure.

【0137】

The acceptance signal IN-ACCEPT is also used as an enable to the latch LDIN, LEIN and LVIN. As a result, the NOT-DUPLICATE signal is low and the accept signal IN-ACCEPT is also low, all three of which are disabled and retain the values stored in their output. NOT-DUPLICATE signal goes high and accept signal LAIN output goes high The processing stage will not accept new data until the above requirements are met.

【0138】

As long as there is a valid data token (as long as the DATA-TOKEN signal QO2 is 1), the signal QO3 will move back and forth between the high and low states, so the input latch will be activated for clock phases PH0 and PH1. Data can be accepted every complete cycle of both. Of course, it is indicated by the high OUT-ACCEPT signal. The conditions for data acceptance readiness for the next processing stage must also be met. Therefore, the output latch LDOUT supplies the same data word on the output bus OUT-DATA during at least two clock cycles. The OUT-VALED signal is 1 only when a valid data token exists (QO2 is high) and the validity signal QVOUT is high.

【0139】

The signal QEIN, which is an additional bit corresponding to MID-DATA, is combined with the signal S3 in the logic gate groups INV10 and NAND10 forming the signal S4. During one data token, each data word MID-DATA is repeated by loading it into the latch LDOUT twice. Between these firsts, the signal S4 is set to "1" by the action of NAND10. The signal S4 is loaded into the latch LEOUT and MID-DATA is loaded into the LDOUT to form OUT-DATA 7: 0 and at the same time form OUTEXTN.

【0140】

So, first, when a MID-DATA is loaded into LEOUT, the corresponding OUTEXTN is set high. On the other hand, in the following states, OUTEXTN becomes the same as the signal QEIN. Now consider the state between the last words of the token when the QEIN is known to be low. On the first feedback, when MID-DATA is loaded into LDOUT, OUTEXTN will be "1" and on the next feedback, OUTEXTN will be "0", indicating the true end of the token.

【0141】

The output signal QVIN from the effective latch LVIN is combined with the signal QI3 at the gate groups INV12 and NAND12 to generate the signal S5. Using well-known Boolean algebra, it can be seen that the signal S5 is high when the validity signal QVIN is high or when the signal QI3 is low (indicating that the data is duplicate). The signal S5 is loaded into the effectiveness output latch LVOUT at the same time that MID-DATA is loaded into LDOUT and the intermediate additional bit (signal S4) is loaded into LEOUT. The signal S5 is also combined with the signal QO2 (the data token signal and the logic gates NAND30 and INV30 to generate the output validity signal OUT-VALID. As mentioned above, when the valid token is present and the validity signal QVOUT is high. OUT-VALID is high only for.

【0142】

The MID-ACCEPT signal is combined with signal S5 by logic gates NAND26 and INV26, which perform the well-known AND function, to generate signal S6, which has two enable to latches LO1, LO2 and LO3. Used as one. When the signal MID-ACCEPT is high and the validity signal QVIN is high or the token is a duplicate (QI3 is 0), the signal S6 is 1. If MID-ACCEPT is high, valid input data is supplied to the input of the processing stage, or latch LO1 to LO3 is enabled when the clock signal PH1 is high when the latched data is replica. Will be done.

【0143】

As is clear from the above, the processing stages shown in FIGS. 13 and 14 receive and transmit data between the processing stages under the control of the effectiveness signal and the acceptance signal as in the above embodiment. is there. However, as an exception, the output signal on the input side of the acceptance latch LAIN is combined with the changing duplicate signal and the data word is output twice before the new word is accepted.

【0144】

Of course, various logic gates such as NAND16 and INV16 can be replaced by equal logic circuits (in this case a single and gate). Similarly, for example, if the latches LEIN and LVIN have inverting outputs, the inverters INV10 and INV12 are not needed. The corresponding inputs of gates NAND10 and NAND12 are then directly connected to the inverted outputs of these latches. As long as an appropriate logical operation is performed, the processing stages operate with the same correspondence. Data words and additional bits are still duplicated.

【0145】

It should be noted here that the duplication function performed by the illustrated processing stage is unless the first data word of the token has a "1" in its third bit and the five most significant bits have a "0". It is not executed. (Of course, the desired pattern can be easily changed by selecting another logic gate and selecting the connection relationship of gates NOR1, NOR2 and NAND18.) Further, as shown in FIG. 13, the OUT-VALID signal remains low throughout the token unless the first data word has the structure described above. As a result, all tokens other than one token to be duplicated are removed from the token column. This is because the devices connected to the output terminals OUTDATA, OUTEXTN and OUTVALID do not recognize these token words as valid data.

【0146】

As before, the effectiveness latches LVIN and LVOUT in the processing stage are reset by a single signal NOT-RESET0 and then reset by a single reset input R of the downstream latch LVOUT by a reset signal propagated further upstream. The upstream effectiveness latch is then lowered in the next clock cycle.

【0147】

In the example shown in FIG. 13, replication of the data in the data token is an example of a circuit that processes the acceptance and validity signals, and more data than the input data is generated in the pipeline processing stage. .. Similarly, the example shown in FIG. 13 removes all non-data tokens, which is shown as an example of a circuit that processes a valid signal to remove data from the data sequence. However, in many typical applications the pipeline processing stage simply passes through unrecognized tokens without deformation and processes other processing stages if necessary.

【0148】

Both FIGS. 15 and 16 show an example of the timing chart of the data duplication circuit shown in FIGS. 13 and 14. As before, the timing chart shows the relationship between the two phase clocks, the various internal and external control signals, and the correspondence between data synchronization and duplication between the input and output sides of the processing stage.

[Simple explanation of drawings]

[Figure 1]

It is a figure which shows the state in 6 cycles of the pipeline circuit which consists of 6 processing stages under the different combination of two internal control signals.

[Figure 2]

Each processing stage shows a pipeline with auxiliary data storage means, and further shows aspects in which the processing stages can be "compressed" and "decompressed" in response to delays in the pipeline circuit.

[Fig. 3]

Each processing stage shows a pipeline with auxiliary data storage means, and further shows aspects in which the processing stages can be "compressed" and "decompressed" in response to delays in the pipeline circuit.

[Fig. 4]

The control of data transmission between processing stages in a preferred embodiment of a pipeline circuit using a two-line interface and a polyphase clock is shown.

[Fig. 5]

The control of data transmission between processing stages in a preferred embodiment of a pipeline circuit using a two-line interface and a polyphase clock is shown.

[Fig. 6]

The control of data transmission between processing stages in a preferred embodiment of a pipeline circuit using a two-line interface and a polyphase clock is shown.

[Fig. 7]

The control of data transmission between processing stages in a preferred embodiment of a pipeline circuit using a two-line interface and a polyphase clock is shown.

[Fig. 8]

It is a block diagram which shows the basic example of the pipeline circuit using 2 line transmission control by this invention, the processing stage of 2 continuous pipelines, and 2 line transmission control.

[Fig. 9]

It is a timing chart which shows the relationship between the timing signal, the input and output data, and the internal control signal used in the pipeline processing stage shown in FIG.

[Fig. 10]

It is a timing chart which shows the relationship between the timing signal, the input and output data, and the internal control signal used in the pipeline processing stage shown in FIG.

[Fig. 11]

It is a block diagram which shows the example of the processing stage of the pipeline circuit which holds the state under the control of an additional bit in the pipeline circuit by this invention.

[Fig. 12]

It is a block diagram of the pipeline processing stage which decodes a stage activation data word.

[Fig. 13]

It is a block diagram which shows the usage of the two-line transmission control by this invention in a "data duplication" pipeline processing stage.

[Fig. 14]

It is a block diagram which shows the usage of the two-line transmission control by this invention in a "data duplication" pipeline processing stage.

[Fig. 15]

FIG. 5 is a timing chart showing a two-phase clock, a two-line transmission control signal, other internal data, and a control signal used in the examples shown in FIGS. 13 and 14.

[Fig. 16]

FIG. 5 is a timing chart showing a two-phase clock, a two-line transmission control signal, other internal data, and a control signal used in the examples shown in FIGS. 13 and 14.