Arithmetic processing method and microcomputer

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to an arithmetic processing method for performing a predetermined arithmetic processing by executing a series of instructions constituting a program and a microcomputer, for example, a one-chip type microcomputer having a CPU (central processing unit) and a memory built-in. Regarding technologies that are effective when applied to computers (single-chip microcomputers).

【0002】

[Conventional technology]

A single-chip microcomputer has a CPU and other necessary peripheral circuits contained in a single semiconductor substrate, and has a built-in program ROM (read-only memory) that holds its operating program. On the other hand, the multi-chip microcomputer does not have a built-in ROM for storing the operation program, and the necessary operation program is obtained from an external memory (ROM) arranged outside the multi-chip microcomputer. ..

【0003】

In such a single-chip microcomputer, the instructions stored in the main memory such as the program ROM are read directly into the CPU. Therefore, as the program size increases, the main storage device stores the instructions. You need to increase the capacity. However, it leads to an increase in the occupied area of the main storage device in the semiconductor chip and further an increase in cost.

【0004】

Further, as a conventional technique, for example, as described in Japanese Patent Application Laid-Open No. 55-131848, a program is compressed and stored in an auxiliary storage device, and when the program is loaded into the main storage device, the original program is stored. There is a method of extending to size.

【0005】

[Problems to be Solved by the Invention]

However, according to the technique described in Japanese Patent Application Laid-Open No. 55-131848, although the storage capacity of the auxiliary storage device can be apparently increased by reducing the program size in the auxiliary storage device, the program is installed in the main storage device. Since it is expanded to its original size when loaded, the memory usage of the main storage device cannot be particularly reduced. In a microcomputer embedded system, it is particularly important to reduce the ROM size and RAM size and reduce the memory usage to reduce the cost of the entire system.

【0006】

An object of the present invention is to provide a technique for reducing the capacity of the main storage device.

【0007】

Another object of the present invention is to provide a technique for suppressing a decrease in program execution speed as much as possible when the used capacity of the main storage device is reduced in such a way.

【0008】

The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.

【0009】

[Means for solving problems]

A brief description of typical inventions disclosed in the present application is as follows.

【0010】

That is, when the program is compressed and stored in the storage means, the instruction code is reproduced by fetching the compressed program data in the storage means and decompressing the fetched program data, and the obtained instruction code is used. Decode. When this instruction code is an instruction that involves changing the program execution order, the jump destination address whose instruction execution order should be changed is converted into the jump destination address in the compressed program, and this is set in the program counter. Further, when only the main instructions constituting the program are compressed, it is not necessary to decompress all the fetched data. Therefore, it is determined whether or not decompression is necessary each time the data is fetched. The decompression process can be performed according to the determination result.

【0011】

Then, when the microcomputer is configured to perform a predetermined arithmetic process by decoding and executing a series of instructions constituting the program, including a program counter for designating an instruction address, the compressed program is processed. A storage means for storing data, a decompression means for obtaining an instruction code by decompressing the compression program data fetched from the storage means, and a decode decoder for decompressing the instruction code are provided. Further, when the extended instruction code is accompanied by a change in the program execution order, an address conversion means for converting the jump destination address whose instruction order should be changed to the jump destination address in the compression program, and the converted jump destination. A program counter setting means for setting the destination address in the program counter is provided. At this time, it is possible to provide a means for determining whether or not decompression is necessary each time the data is fetched, and perform decompression processing according to the determination result.

【0012】

Further, in a specific embodiment, a conversion rule table for decompressing the data fetched from the storage means to the pre-compressed format is provided, and the instruction is decompressed to the pre-compressed format by searching the conversion rule table. In addition, an address conversion table for converting the jump destination address to the address in the compression program is provided, and by searching this address conversion table, the jump destination address in the compression program can be obtained. Can be configured.

【0013】

[Action]

According to the above-mentioned means, it is possible to fetch an instruction from a storage means that stores a program in a compressed state and execute the instruction by decompressing the fetched instruction to a format before compression. Achieve a reduction in memory usage. In addition, finding the jump destination address using the conversion table suppresses the decrease in program execution speed.

【0014】

[Example]

Here, first, the technique examined by the inventor of the present application will be described.

【0015】

As a technique for reducing the program size, there is a technique using a data compression algorithm represented by the Huffman coding algorithm. A program compressed using such an existing data compression algorithm is placed in a main memory such as a program ROM, while the CPU is provided with a means for decompressing the compressed program to decompress the program. The inventor of the present application has examined a technique for reducing the memory usage of the main storage device by executing the program while performing the program. As a result, the address allocation of the program before compression and the address allocation of the program after compression are different. Therefore, in a branch instruction such as a JMP (jump) instruction, the operation of jumping to the jump destination address of the program before compression is compressed. It turned out that it is necessary to execute the branch instruction after changing to the operation of jumping to the later jump destination address. In other words, it was found that it is necessary to obtain the address after program compression from the address before program compression. To obtain the address after program compression from the address before program compression, create a correspondence table for all addresses in advance, and when address translation is required, refer to the correspondence table and the corresponding jump destination. It is conceivable to ask for an address. However, creating an address correspondence table for all addresses requires a huge storage area for storing such a correspondence table, and rather increases the memory usage of the main storage device. Also, as another method, a method of calculating the address before program compression to the address after program compression according to some algorithm can be considered, but it is a process while executing the program. , It was found that there is a risk of slowing down the program execution speed. The present invention was born from the above study.

【0016】

FIG. 2 shows a single-chip microcomputer 1 according to an embodiment of the present invention. This single-chip microcomputer 1 is not particularly limited, but has a CPU (central processing unit) 3, a ROM (read-only memory) 5, a RAM (random access memory) 7, a timer 9, and a serial communication interface (SCI). 11, A / D converter 13, interrupt controller 15, and functional blocks such as 1st to 9th ports 21 to 29 are included, and they are configured by being commonly connected to the internal address bus 31 and the internal bus 33, and are known. It is formed on one semiconductor substrate such as single crystal silicon by the semiconductor integrated circuit manufacturing technology of.

【0017】

The main storage devices of the single-chip microcomputer 1 in this embodiment are the above RAM 7 and ROM 5, and the RAM 7 is used as a work area of the CPU 3 or a temporary storage area of data. ROM5 is not particularly limited, but holds the operating program of CPU3 in a compressed state. As shown in FIG. 6, in this ROM 5, in addition to the compressed program (referred to as a compressed program) 500, predetermined table formation information is stored, so that the address conversion table 314 and the conversion rule table are stored. 303 is formed. Although not particularly limited, this ROM5 is an EPROM (electrically programmable read-only memory) in which information can be written from outside the microcomputer by an EPROM writer.

【0018】

Here, the operation program is stored in the ROM 5 in a compressed state, the program data is fetched by the CPU3, and the data is decompressed before it is executed. In other words, the program is executed with the program on ROM5 still compressed. That is, the operation of decompressing the instructions in a batch before shifting to the execution stage is not performed, and the compressed program data fetched in 1-byte units is sequentially decompressed. In this embodiment, the memory usage of the main storage device including the ROM 5 is reduced by storing the operation program in the ROM 5 in such a compressed state.

【0019】

Further, for example, a large number of bonding pads are arranged as electrode pads on the peripheral edge of the semiconductor substrate, and for example, the winding pads P10 to P17 and P20 to connected to the input / output terminals of the first to ninth ports 21 to 29. P24, P30 ~ P37, P40 ~ P47, P50 ~ P57, P60 ~ P63, P70 ~ P77, P80 ~ P87, P90 ~ P97, connected to the input of clock generator 17 and connected to an oscillator not shown or an external clock Bonding pads XTAL, EXTAL, etc. are placed.

【0020】

The single-chip microprocessor 1 as a chip or pellet thus constructed is die-bonded to the mount portion of the package in the assembly process, and the bonding pad is wire-bonded to the lead terminal of the package and then sealed.

【0021】

The single-chip microcomputer shown in Fig. 2 is designed to interface with the outside through various ports. The function of the port can be specified by setting the operation mode, and the operation mode that outputs the address signal to the outside to access the external memory and peripheral devices is also supported.

【0022】

Here, typical operation modes of the single-chip microcomputer 1 are a single-chip mode and an extended mode. The single-chip mode is an operation mode in which the operation of outputting an address signal to the outside and accessing it is completely prohibited, or an operation mode in which the internal bus is not opened to the outside. In such an operation mode, the CPU 3 sequentially reads the operation program from the built-in ROM 5. At this time, almost all ports are made available to the user for timer 9 and SCI 11. Extended mode is an operation mode that allocates a specific port for address output and data input / output to make external memory and other peripheral devices accessible, and the address map of the internal circuit module according to the type of extended mode to be set. In addition, the input / output signal assignment at the port is changed. For example, when the extended mode is set, the address space allocated to the built-in ROM5 is set to the external memory space, the module selection signal for ROM5 is set to a non-selection level at all, and it cannot be used in terms of software or hardware, as if it were. Treated as if ROM5 does not exist. At this time, the operating program of CPU3 is read exclusively from the external ROM.

【0023】

Such an operation mode setting is performed according to a combination of signal levels supplied from the control number input pads CP1 to CP3 for instructing the operation mode of the CPU3. For example, the operation mode is set by latching the signals supplied from the control number input pads CP1 to CP3 at a predetermined timing to a mode control register (not shown) at the time of reset.

【0024】

In addition, the single-chip microcomputer 1 has a test mode for improving the efficiency of testing by making it easy to determine a defective part from the outside during device testing, and a signal input to a predetermined terminal. When the test mode is set by a combination of levels, the internal bus is directly opened to the outside through a predetermined port.

【0025】

Figure 1 shows a configuration example of CPU3.

【0026】

The arithmetic and logical operation unit (ALU) 107 is a hardware unit for performing numerical operations and logical operations necessary for data. Numerical operations include addition, subtraction, multiplication, division, etc., and logical operations include OR and AND operations, which are executed based on a binary addition circuit. Such an ALU 107 is coupled with a flag flip-flop 108 for holding various states that occur during the calculation. In addition, a register 105 for temporarily holding data for calculation by ALU107, an accumulator 104 for storing one input of the calculation or the calculation result thereof, a general-purpose register 112 for holding various data, Stack pointer 113 indicating the top of the stack area for saving the contents of various registers when executing a subroutine, program counter 114 indicating the instruction address to be executed next, address latch 115 for temporarily holding the output address, A data buffer 117 or the like for enabling data exchange with the outside of the CPU 3 is connected to each other by an internal bus 103. 116 is an address buffer for enabling the output of addresses.

【0027】

Reference numeral 108 denotes an decompression unit, which is connected to the internal bus 103 and stores the compressed program data of the execution format in a compressed state. The compressed program data fetched from ROM 5 (see FIG. 2) is stored before compression. It has the function of extending to the form. That is, the decompression unit 108, for example, pressure 8 bits having a data length converting step of converting the compressed program data reduced, the program data before compression, such as 16 bits. The stretching means in the present invention is formed by the stretching portion 108. An instruction register 109 for holding an instruction code obtained by being extended by the extension unit 108 is arranged in the subsequent stage of the extension unit 108, and further, the instruction register 109 is decoded by decoding the instruction register 109. An instruction decoder 110 for decoding an instruction is arranged. This decoding result is input to the control unit 111 arranged in the subsequent stage. The control unit 111 sends appropriate control signals to the inside and outside of the CPU 3 and executes the necessary operation specified by the instruction decoded by the instruction decoder 110 in several steps. ..

【0028】

FIG. 3 shows the main functional blocks of the extension unit 108 and the control unit 111.

【0029】

The decompression unit 108 is not particularly limited, but determines whether or not the compression program data fetched from ROM 5 is the decompression target, and the fetched compression program data according to the determination result. Selectively select the fetched data and the instruction searched by the conversion rule table search means 302 according to the determination result of the conversion rule table search means 302 for decompressing to the format before compression and the instruction discrimination means 301. It includes a selection means 304 for transmitting to the instruction register 109 of the subsequent stage. Here, the conversion rule table search means 302 searches the conversion rule table 302 and decompresses the compressed program data by reading the corresponding instruction code.

【0030】

Although the control unit 111 is not particularly limited, the instruction discriminating means 311 for discriminating whether or not it is a branch instruction from the decoded output of the instruction decoder 110 and the instruction discriminating means 311 indicate that the control unit 111 is a branch instruction. When it is determined, the address conversion table search means 313 for searching the address conversion table 314 and converting the jump destination address into the address in the compression program and the converted address are set in the program counter 114 (see FIG. 1). It includes a program counter setting means 315 for controlling the operation, and an execution control means 312 for controlling the operation of the ALU 109, various registers, and the like according to the decoding output of the instruction decoder 110.

【0031】

In this specification, the branch instruction should be understood as a general term for instructions that need to change the instruction execution order, such as a subroutine jump instruction and an interrupt processing instruction. The jump destination address means the instruction address to be executed next by changing the instruction execution order. That is, when the CPU3 executes a series of instructions that do not need to change the instruction execution order, the value of the program counter 114 is incremented each time the CPU3 executes one instruction, and the instruction address to be executed next. Is the value of. On the other hand, when CPU3 executes an instruction whose instruction execution order needs to be changed, the value of the program counter 114 is not incremented as described above, but is executed next by changing the instruction execution order. It is set to the value of the address (destination address) of the instruction to be output.

【0032】

Next, the operation program stored in the ROM 5 will be described in detail.

【0033】

Figure 7 shows the flow of processing from assembling the source program to writing the ROM.

【0034】

Although not particularly limited, the relocatable object 703 is obtained by converting the source program 701 written in assembly language into machine language by the assembler 702. Figure 10 shows the correspondence between the source program and the machine language instruction. The linkage editor 704 fetches multiple relocatable objects 703 and creates an execution object 705. Relocatable objects consist of an external symbol table, text, and a rearranged join table. The external symbol table contains all the external symbol names referenced from within that module and, conversely, all the symbol names defined within that module and referenced from other modules. Then, the obtained execution object is compressed by the compression tool 706 to obtain a post-compression execution object (compression program) 707. At this time, the address translation table data 708 for forming the address translation table 314 (see FIG. 3) and the translation rule table data 709 for forming the translation rule table 303 (see FIG. 3) are generated. The post-compressed execution object 707, the address translation table data 708, and the translation rule table data 709 thus obtained are written to ROM 5 (see FIG. 2) by the EPROM writer 710.

【0035】

FIG. 8 shows the flow of the compression process by the compression tool 706.

【0036】

In this embodiment, although not particularly limited, in order to match that the instruction fetch is performed in byte units, the multi-byte string data having a high frequency of occurrence is simply compressed by 1 byte, and the data having a low frequency of occurrence is so. By arranging a predetermined prefix immediately before the data without performing any compression processing, it is distinguished from the above-mentioned compressed expression. Such compression processing will be described in detail below.

【0037】

As shown in Figure 8, all the data in the execution object is read (801) and the frequency of occurrence of the data is checked (802). The frequency of occurrence is not particularly limited, but is obtained by checking the program data in units of a plurality of bytes, for example, 2 or 3 bytes from the beginning of the execution object. Figure 5 shows an example of how often the data contained in the execution object appears. In this example, the byte string data appears most frequently, and the byte string data, the byte string data, the byte string data, the byte string data, and the byte string data decrease in frequency in that order. Then, 1-byte codes are assigned in descending order of frequency of appearance, for example, 00 01 02 ... (803). That is, 00 is assigned to the byte string data that appears most frequently, and 01 is assigned to the data that appears next most frequently. Is assigned, and so on, the codes are assigned in descending order of frequency of occurrence. By assigning the 1-byte code in this way, the conversion rule table 303 is formed. That is, a correspondence table between the 1-byte instruction and the corresponding machine language code is formed. Then, by referring to the conversion rule table 303, program compression is performed as follows.

【0038】

That is, it is determined whether or not to end the compression processing for all of the execution objects (805), and if it is determined not to end in this determination, the conversion rule table 303 formed in step 804 above. Therefore, the program data is compressed by converting the program data into the corresponding 1-byte code (806). At this time, from the program data to be processed, it is possible to determine whether or not the jump destination address is included in the program data, in other words, whether or not the data related to the compression processing target corresponds to the branch instruction. (807). Therefore, in such a determination, when it is determined that the jump destination address has appeared, the corresponding post-compressed address (jump destination address in the compression program) is obtained (808), and thereby the address translation table 314 is displayed. Data 708 to form is obtained. Such conversion of the jump destination address is performed because the address allocation of the program before compression and the address allocation of the program after compression are different. Therefore, for example, in a branch instruction such as a JMP (jump) instruction, before compression is performed. This is because if the operation of jumping to the jump destination address of the program is not changed to the operation of jumping to the jump destination address after compression, the instruction execution routine by the branch instruction will be abnormal.

【0039】

Then, unless it is determined that the uncompressed instruction does not exist in the determination in step 805, in other words, the processing in steps 806 to 809 is repeated until the processing for all the instructions constituting the operation program is completed. Is done.

【0040】

Further, as described above, in this embodiment, the byte string data having a low frequency of appearance is not targeted for compression, the 1-byte compression expression as described above is not performed, and the original byte string data is arranged as it is. Then, in order to distinguish such uncompressed byte string data from the compressed data, a prefix such as ff is placed immediately before the uncompressed byte string data. By arranging the prefix ff in this way, it can be seen that the following 1-byte code is uncompressed data. In the instruction discriminating means 301 of FIG. 3, it is possible to discriminate whether or not the extension is necessary by checking whether or not the prefix ff has been fetched. That is, when the prefix ff is detected, the instruction following it is uncompressed data and is not compressed, so it is excluded from the decompression process.

【0041】

According to the machine language data shown in FIG. 10, the program images before and after compression are shown in FIG. For example, uncompressed 3-byte string data 04 00 8C has the highest frequency of occurrence, and 1-byte code 00 is assigned to it, followed by 2-byte string data 1d ff, which has the next highest frequency of occurrence. If conversion rule table 302 is formed by assigning 1-byte code 02 to 2-byte string data 0e 80, which is assigned 01 and then appears most frequently, the table is referred to during compression processing. By doing so, the 3-byte string data 04 00 8C is converted to 1-byte code 00, the 2-byte string data 1dff is converted to 1-byte code 01, and the 2-byte string data 0e 80 is converted to 02. .. In this way, the program data can be reduced by allocating 2 bytes or more of data to the 1-byte code.

【0042】

In the compressed data in FIG. 4, the 1-byte code placed immediately after the prefix ff can be seen to be uncompressed data due to the presence of the prefix ff. That is, "10 20" and "30 10 00" are not included in the compression target because they appear infrequently.

【0043】

Next, the instruction execution in the present embodiment microcomputer incorporating the compression program formed as described above, the address conversion table 314, and the conversion rule table 303 (see FIG. 6) is stored according to the flowchart of FIG. It will be described in detail.

【0044】

First, the compressed program data is fetched from the ROM 5 in 1-byte units (901), and the instruction determination means 301 determines whether or not the data is the target of the decompression process (902). This determination is basically made possible by whether or not the fetched 1-byte data has the prefix ff indicating the uncompressed state. If the prefix ff is not detected, the fetched 1-byte data is subject to decompression, and the conversion rule table search means 302 searches the conversion rule table 303 to obtain the corresponding instruction code. It is written to instruction register 109 (904). For example, if the fetched data is 00, the instruction code corresponding to it is 04008c according to the conversion rule table, so it is written to the instruction register 109 in byte units, and this instruction is further executed. The code is decoded by the instruction decoder 110 (905). On the other hand, the prefix ff When is fetched, the instruction fetched next is in the uncompressed state, so that the instruction is written to the instruction register 109 without searching the conversion rule table 303 (903). ), It is decoded by the instruction decoder 110 (905).

【0045】

Next, the instruction discriminating means 311 in the control unit 111 determines whether or not the instruction decoded by the instruction decoder 110 is a branch instruction (906). For example, as shown in FIG. 10, when the instruction discriminating means 311 detects that the jump instruction JMP to the label L: (address 0100), the address translation table search means 313 causes the address search table 314 to move. It is searched and the corresponding branch destination address is sought (908). The branch destination address obtained here is the branch destination address in the compression program data stored in ROM5. Then, the branch destination address is set in the program counter 114 by the program counter setting means 315, jumps to the branch destination address in the compression program (909), and returns to the reading of the compression program in step 901. If it is determined that the instruction is not a branch instruction in the determination in step 906, the instruction is executed by performing control according to the instruction.

【0046】

According to the above embodiment, the following effects can be obtained.

【0047】

(1) Stores an execution format program in a compressed state It is configured to fetch compressed program data in 1-byte units from ROM5, decompress it to the format before compression, and then decode and execute it. Therefore, it is possible to reduce the memory usage of the main storage device including the ROM 5. For example, in a general microcomputer application program, the jump destination label that appears in the machine language program is about once every 20 bytes, and the total program size is about several tens of Kbytes to several hundreds Kbytes. Therefore, the compression rate of the application program is 50%, the conversion rule for forming the conversion rule table 303 is 3 bytes x 200, and the size of the address conversion table 314 is 4 bytes x (program size) x (1). / 20) Then, the 10 Kbyte application program is reduced to 7.6 Kbytes after compression, and the 60 Kbyte application program is reduced to 43.6 Kbytes after compression. Therefore, the memory usage of the main storage device including ROM5 is reduced. Can be significantly reduced.

【0048】

(2) When executing a compressed program, the address allocation of the program before compression and the address allocation of the program after compression are different. Therefore, for example, in a branch instruction such as a JMP (jump) instruction, the program before compression The operation to jump to the jump destination address of is changed to the operation to jump to the jump destination address after compression, and then the branch instruction must be executed. For example, the address after program compression is obtained from the address before program compression. In addition, it is conceivable to create a correspondence table for all addresses in advance and obtain the corresponding jump destination address by referring to the correspondence table when address conversion is required. However, according to the above embodiment, An address conversion table 314 showing the relationship between the branch destination address in the precompression program and the branch destination address in the compression program is formed in ROM5, and the branch destination address is converted by searching for it. The size of the conversion table is about 4 bytes x (program size) x (1/20), and as described above, the memory usage increases compared to the case of creating an address correspondence table for all addresses. Can be suppressed. Also, in the case of a method that calculates the address before program compression to the address after program compression according to some algorithm, the processing is performed while the program is being executed, so the program execution speed is reduced. However, in the case of the above embodiment, since the branch destination address is converted by searching the address conversion table 314, it is possible to suppress a decrease in the program execution speed.

【0049】

The invention made by the present inventor has been specifically described above based on examples, but it goes without saying that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

【0050】

For example, in the above embodiment, the ROM 5 and the RAM 7 may be arranged outside the single-chip microcomputer 1.

【0051】

In the above embodiment, EPROM is applied as ROM5, but EEPROM (electrical eraseable and programmable read-only memory) capable of electrically erasing stored information, and user's It is also possible to apply a mask ROM capable of writing information by selectively injecting ions into a predetermined memory cell transistor using a unique photomask based on the required specifications.

【0052】

In the above embodiment, the case where the assembly language is used has been described, but other programming languages can be used.

【0053】

In the above embodiment, in the compression program data stored in ROM5, the infrequently appearing instructions are not compressed, but all the instructions may be compressed regardless of the appearance frequency. .. Further, in the above embodiment, the appearance frequency is obtained in units of a plurality of byte string data and compressed by converting to a 1-byte code in descending order of appearance frequency. However, the appearance frequency is obtained in instruction units and the appearance frequency is determined. It may be converted into a 1-byte code in descending order.

【0054】

The translation rule table 303 and the address translation table 314 may be formed in RAM 7.

【0055】

In the above description, the case where the invention made by the present inventor is mainly applied to the single-chip microcomputer which is the field of use as the background thereof has been described, but the present invention is not limited thereto, and the built-in program ROM 5 is used. It can be applied to arithmetic processing in general-purpose single-chip microcomputers that do not have, and also in various data processing devices.

【0056】

The present invention can be applied at least on the condition that a predetermined arithmetic process is performed by sequentially decoding and executing a series of instructions constituting the program.

【0057】

[Effect of the invention]

A brief description of the effects obtained by representative of the inventions disclosed in the present application is as follows.

【0058】

That is, the memory usage of the main storage device is calculated by fetching the compressed program data from the storage means that stores the program in the compressed state, decompressing it to the format before compression, decoding it, and executing it. The reduction can be achieved, and further, the size of the semiconductor chip can be reduced and the cost can be reduced. Further, by converting the jump destination address into the jump destination address in the compression program according to the above-mentioned decoding output and setting the converted jump destination address in the program counter, the branch instruction can be executed accurately. Moreover, by performing the conversion of the branch destination address in the conversion table, it is possible to suppress a decrease in the calculation processing speed.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of the CPU in the single chip microcomputer which is one Example of this invention.

[Figure 2]

It is an overall block diagram of the single chip microprocessor which is one Example of this invention.

[Fig. 3]

It is a functional block diagram of the extension part and control part included in the CPU.

[Fig. 4]

It is explanatory drawing for comparing the memory image of a program before and after compression.

[Fig. 5]

It is explanatory drawing of the appearance frequency of the instruction which constitutes a program.

[Fig. 6]

It is explanatory drawing of the storage contents of ROM included in the said single-chip microcomputer.

[Fig. 7]

It is a flowchart of the process from assembling the source program to writing to ROM.

[Fig. 8]

It is a flowchart of the compression process included in the process from assembling the source program to writing to ROM.

[Fig. 9]

It is a flowchart of instruction execution in the said single-chip microcomputer.

[Fig. 10]

It is explanatory drawing of the correspondence relation | correspondence between a source program and a machine language instruction.

[Explanation of symbols]

3 CPU 5 ROM 7 RAM 103 internal bus 104 accumulator 105 temporary register 106 flag flip flop 107 ALU 108 Extension 109 instruction register 110 instruction decoder 111 Control unit 112 General-purpose register 113 Stack pointer 114 Program counter 115 address latch 116 Address buffer 117 Data buffer 301 Instruction discrimination means 302 Conversion rule table search method 303 Conversion rule table 304 Choice 311 Command discrimination means 312 Execution control means 313 Address translation table search method 314 Address translation table 315 Program counter setting means 500 compression program