Photoelectric conversion device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a photoelectric conversion device used as a copier, a facsimile, a video camera recorder, an AE sensor of a camera, and an AF sensor.

【0002】

[Explanation of background technology]

In recent years, electronic technology has advanced to a high degree, and even in the field of solid-state image sensors as photoelectric conversion devices, high definition and high image quality have been rapidly realized. By the way, it is very rare that the output signal from the solid-state image sensor is used as it is, and after several stages of signal processing, for example, a TV signal or the like is created.

【0003】

PROBLEM TO BE SOLVED: To solve a technical problem

Therefore, when the number of pixels is increased for high definition, a huge amount of calculation and processing are required in signal processing, and high image quality may be rate-determined by signal processing.

【0004】

[Means for solving problems]

An object of the present invention is to provide a solid-state image sensor that outputs a signal obtained by multiplying each signal by a coefficient in order to incorporate a signal processing function into the solid-state image sensor.

【0005】

The above-mentioned object is achieved by a photoelectric conversion device including a plurality of photoelectric conversion elements, wherein an amplifier capable of controlling a gain from the outside is provided at an output terminal of each photoelectric conversion element.

【0006】

[Example]

(Example 1) FIG. 1 shows a first embodiment according to the present invention. In this embodiment, bipolar photoelectric conversion elements are arranged one-dimensionally as photoelectric conversion elements, and each base region is a MIMO transistor M.₁₁~ M₁₄It is connected via.

【0007】

Further, amplifiers A1 to A4 are independently connected to the emitter output line of each photoelectric conversion element.

【0008】

The operation of this embodiment will be briefly described with reference to the timing chart of FIG.

【0009】

First, time t₁ In φ_R When a low level pulse is applied to, the MIMO transistor M₁₁~ M₁₄Turns on, and bipolar transistor B₁ ~ B₄ Is connected in common and V_BRIt is reset to voltage. Then φ_R By rising to the Middle level, the MIMO transistor M₁₁~ M₁₄Turns off and the reset operation ends (clamp reset).

【0010】

Then time t₂ In φ_VC1 When the pulse rises, the NMOS transistor M₂₁~ M₂₄Turns on, and bipolar transistor B₁ ~ B₄ All emitter terminals are V_VCReset to voltage and then time t₃ In φ_R When the pulse rises to the High level, the bipolar transistor B₁ ~ B₄ Base potential is capacitance C₁ ~ C₄ It is lifted through, and the base and emitter are in a forward bias state, the bipolar transistors perform emitter follower operation all at once, the holes on the base are recombined, and the base potential is V._VC+ V_BESettle in the vicinity (transient reset operation). Time t when the transient reset operation ends₄ In φ_R The pulse drops to the Middle level, so the capacitance C₁ ~ C₄ The base potential of each bipolar transistor also drops, and the base-emitter is in a reverse bias state. From this state, the accumulation operation of the optical carrier is started.

【0011】

After the predetermined accumulation time has elapsed, the time t₃ In φ_T And φ_R When the pulse of is raised to the High level, the NMOS transistor M₃₁~ M₃₄Bipolar transistor B as soon as₁ ~ B₄ The base potential of is raised, the bias between the base and the emitter becomes a forward bias state, and the optical carriers accumulated on the base are output from the emitter terminal. At this time, if a predetermined voltage is applied from the power supply 2 to the control terminals of the amplifiers A1 to A4, each amplifier can have a desired gain.

【0012】

The output of amplifiers A1 to A4 is C_T1~ C_T4Read out at time t₆ In φ_T When the pulse drops to the low level, the NMOS transistor M₃₁~ M₃₄Turns off and each capacity C_T1~ C_T4Voltage is retained.

【0013】

Then time t₇ In φ_RES Apply a high level pulse to the NMOS transistor M_RSIs turned on, the output line 4 is reset, and then the scanning circuit 1 is operated, and C_T1Output terminal V via output buffer 3 in order from the above signal_{out out} By transferring to, the series of operations is completed.

【0014】

By the way, suitable circuit examples of amplifiers A1 to A4 and their DC characteristic diagrams are shown in FIGS. 3 and 4.

【0015】

FIG. 3 shows an inverting amplifier using an NPN transistor, and the gain is controlled by the gate voltage of the NMOS transistor provided at the emitter terminal.

【0016】

Figure 4 shows the DC characteristic calculation results of this inverting amplifier.

【0017】

Input voltage V on the horizontal axis_IN, Output voltage V on the vertical axis_{out out} And gain control voltage V_C Is a graph of the parameters. As you can see from the figure, V_C The larger the value, the larger the gain and the smaller the circuit scale, which is suitable for this embodiment. Needless to say, other types of amplifiers may be used.

【0018】

(Example 2) FIG. 5 shows a second embodiment according to the present invention. This embodiment is an improvement of the first embodiment, the power supply device 2 is omitted, and the gain control voltage of the amplifiers A1 to A4 is input serially from the V-GAIN terminal. ..

【0019】

For example, during the storage period, the scanning circuit 1 is operated, the NMOS transistor M51 is turned on, the gain control voltage of the amplifier A1 is written from the V-GAIN terminal, then the pulse of L1 is set to the low level, and M51 is set. Turn it off and hold the written voltage. This operation is performed sequentially from amplifiers A1 to A4, and after the operation is completed, φ_R When the pulse is set to High level, each photoelectric conversion element performs a read operation, and the voltage obtained by multiplying each output value by the gain is C._T1~ C_T4Is read out.

【0020】

Operations other than the above can be performed in exactly the same manner as in the first embodiment.

【0021】

Therefore, a significant space saving can be realized as compared with providing a power supply for each amplifier.

【0022】

In the above operation description, the gain control voltage of the amplifiers A1 to A4 is written during the accumulation period, but other periods may be used, for example, C._T1~ C_T4This may be done during the sequential transfer of the charges. In this case, the gain control voltage written to the amplifiers A1 to A4 will be used in the next photoelectric conversion operation.

【0023】

(Example 3) FIG. 6 shows a third embodiment according to the present invention. This embodiment is developed in a two-dimensional photoelectric conversion device of the second embodiment, and a vertical scanning circuit 5 is provided in order to sequentially perform the resetting of the photoelectric conversion element and the signal reading operation in line units. , The basic operation is exactly the same as in the second embodiment.

【0024】

(Example 4) FIG. 7 shows a fourth embodiment of the present invention. In the first to third embodiments, the photoelectric conversion unit is an example in which a bipolar amplification element having a base and collector junction as a photodiode is used, but in this embodiment, MOS is used. The parts similar to the conventional ones are given the same number and the description thereof will be omitted. In No. 11, a photodiode is connected to the gate of the MOS, while the resistance of the MOS amplifier is a variable resistance as shown in 10. The variable resistor of 10 has a double structure of the MOS gate, and as shown in 12, one 13 of the lower gate is connected to the power supply and the other 14 of the upper gate is applied with a voltage pulse. It has become like.

【0025】

The potential of the floating gate changes according to the amplitude of the voltage pulse, so that the MOS shown in 10 acts as a variable resistor. Also in the case of this experiment, the optical signal generated by the photodiode is converted into a value obtained by multiplying the amplifier gain determined by the above 10 variable resistors, and this modulated signal is sequentially read by the shift register via the read capacitance.

【0026】

Although FIG. 7 shows an example of a one-dimensional sensor, it goes without saying that the present invention is not limited to one-dimensional and can be used as a two-dimensional sensor.

【0027】

(Example 5) FIG. 8 shows a fifth embodiment of the present invention. In Sij (ij = 1 to 4), as shown in 11, the base separation PBSO12 and the base potential control capacitance 13 are composed of bipolar 15.

【0028】

Cell S₁₁S₂₁Is output to vertical line 16, while cell S₁₂S₂₂Is output to vertical line 17. The selection of each line is pulse φ_PR1 , Φ_PR2 Is done by.

【0029】

First, φ_PR1 High pulse is applied to S₁₁And S₁₂A cell is selected and each output goes up and down at the same time._ijIt is read to the gate of (i, j = 1, 2).

【0030】

Each amplifier gain is adjusted from the voltage sources wired above and below through the wiring of 18, 19, 20, and 21, and the amplifier outlet is φ._PT1 Set the pulse to a high level and S₁₁To the light output of a₁₁Output to capacity 22 with the amplifier gain of₁₂To the light output of a₁₂Output with amplifier gain applied to capacity 23, S₁₁To the light output of a₂₁Output with amp gain applied to capacity 24, while S₂₁To the light output of a₂₂The output to which the amplifier gain of is applied is read out to the capacity 25.

【0031】

Next φ_PR1 To D-level, φ_PR2 At high level, cell S₂₁, S₂₂Is selected and a as before_ijIt is read to the gate of the amplifier (ij = 1 ~ 2').

【0032】

φ_PT2 To high level S₁₁A to the optical output of the cell₁₁Output with amp gain applied to capacity 26, S₁₂A to the optical output of the cell₁₂Output with amp gain applied to capacity 27, S₂₁A to the optical output of the cell₂₁Output with amp gain applied to capacity 28, S₂₂A to the optical output of the cell₂₂The output to which the amplifier gain is applied is read out to the capacity 29.

【0033】

The signals read to the capacities 22, 23, 26 and 27 are added via the capacities 30, 31, 32 and 33 and are added from the amplifier 38, while the signals read to the capacities 24, 25, 28 and 29 are the capacities 34 and 35. It is output from the amplifier 39 added via 36 and 37.

【0034】

The outputs of 38 and 39 are subtracted by the differential amplifier 40. Therefore, the gain may be a mixture of plus and minus, and has the advantage that the Fourier transform output of the image is read out at high speed.

【0035】

[Effect of the invention]

According to the present invention, signal processing in which an arbitrary coefficient is applied to each signal can be satisfactorily performed.

[Simple explanation of drawings]

[Figure 1]

It is a circuit block diagram of the photoelectric conversion apparatus according to Example 1 of this invention.

[Figure 2]

It is a timing chart for demonstrating the operation of the photoelectric conversion apparatus according to Example 1.

[Fig. 3]

It is a circuit diagram of the amplifier used in this invention.

[Fig. 4]

It is a graph which shows the characteristic of the amplifier shown in FIG.

[Fig. 5]

It is a circuit block diagram of the photoelectric conversion apparatus according to Example 2 of this invention.

[Fig. 6]

It is a circuit block diagram of the photoelectric conversion apparatus according to Example 3 of this invention.

[Fig. 7]

It is a circuit block diagram of the photoelectric conversion apparatus according to Example 4 of this invention.

[Fig. 8]

It is a circuit block diagram of the photoelectric conversion apparatus according to Example 5 of this invention.