Driving method for solid-state image pickup element

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a driving method of a solid-state image sensor, and more particularly to a driving method when reading signal charges from each sensor unit to a vertical transfer unit in a solid-state image sensor having an overflow drain (OFD) structure.

【0002】

[Conventional technology]

FIG. 7 is an overall configuration diagram showing a typical configuration example of the interline transfer type CCD solid-state image sensor. In FIG. 7, a large number of photosensors (sensor units) 21 that are two-dimensionally arranged in a matrix and perform photoelectric conversion, and signals that are arranged in each vertical column of these photosensors 21 and read through a read gate 22. The imaging unit 24 is composed of a vertical transfer register (vertical transfer unit) 23 that transfers charges in the vertical direction. The vertical transfer register 23 is transfer-driven by, for example, the four-phase vertical transfer clocks φV1 to φV4.

【0003】

The signal charge read out to the vertical transfer register 23 is transferred to the horizontal transfer register 25 in order for each portion corresponding to one scanning line. The signal charge for one scanning line segment is sequentially transferred in the horizontal direction by the horizontal transfer register 25 and supplied to the charge detection unit 26. The horizontal transfer register 25 is transfer-driven by, for example, two-phase horizontal transfer clocks φH1 and φH2. The charge detection unit 26 is composed of, for example, a floating diffusion amplifier, detects the signal charge transferred by the horizontal transfer register 25, converts it into a signal voltage Vout, and outputs it.

【0004】

In this type of CCD solid-state image sensor, when the gate electrode of the read gate 22 is also used as the transfer electrode of the first phase (φV1) and the third phase (φV3) of the vertical transfer register 23, FIG. As shown in the timing chart of, among the 4-phase vertical transfer clocks φV1 to φV4, the vertical transfer clocks φV1 and φV3 are ternary level (V)._L, V_H, V_T). And the highest voltage pulse V_TIs used as a read pulse for reading the signal charge from the photosensor 21 to the vertical transfer register 23. By applying this read pulse to the gate electrode of the read gate 22, the signal charge accumulated in the photo sensor 21 is read to the vertical transfer register 23 via the read gate 22.

【0005】

[Problems to be Solved by the Invention]

However, in the CCD solid-state image sensor having the above configuration, the voltage V of the read pulse is obtained because the vertical transfer clocks φV1 and φV3 take a ternary level._TMust be set to a high level, and normally the read pulse voltage V without degrading the anti-blooming characteristics._TSince it is difficult to reduce the power consumption, there is a problem that the power consumption becomes high. In particular, in a CCD solid-state image sensor having insufficient anti-blooming characteristics, under conditions for ensuring anti-blooming characteristics, the voltage V of the read pulse is required to sufficiently read out the signal charge accumulated in the photosensor 21._TMust be set high, resulting in higher power consumption.

【0006】

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the voltage of the read pulse for reading the signal charge from the photosensor to the vertical transfer register without deteriorating the anti-blooming characteristics. An object of the present invention is to provide a method for driving a solid-state image sensor that enables a low voltage of a device.

【0007】

[Means for solving problems]

In order to achieve the above object, the driving method of the solid-state image sensor according to the present invention includes a large number of sensor units that are two-dimensionally arranged in a matrix to perform photoelectric conversion, and the sensors arranged for each vertical row of these sensor units. In a solid-state image sensor provided with an image pickup unit having a vertical transfer unit that vertically transfers the signal charge read from the unit, the potential of the sensor unit is reduced when the signal charge is read from the sensor unit to the vertical transfer unit. It is characterized by reading and driving the signal charge.

【0008】

[Action]

In a solid-state image sensor having an OFD structure, when the signal charge is read from the sensor unit to the vertical transfer unit, the clock voltage applied to the P well that functions as an overflow barrier is set to a low level in synchronization with the signal charge read pulse. .. As a result, the potential of the overflow barrier becomes shallow due to the modulation, and the potential of the sensor unit also becomes shallow accordingly. As a result, the potential difference between the sensor unit and the vertical transfer unit becomes large, and the electric field from the sensor unit to the vertical transfer unit becomes strong. Therefore, even if the read pulse voltage is lower than before, the signal charge is sufficiently read out. Is possible.

【0009】

[Example]

Hereinafter, examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional structural view of the periphery of the sensor portion in a CCD solid-state image sensor having a vertical OFD (overflow drain) structure, and in the figure, the same parts as those in FIG. 7 are designated by the same reference numerals. In FIG. 1, the photosensor 21 that performs photoelectric conversion is a P formed shallowly on the surface side of the N-type silicon substrate 1.⁺A hole storage layer 2 composed of type impurities and N formed under the hole storage layer 2.⁺It is composed of a signal charge storage layer 3 made of type impurities. Also, P adjacent to the hole storage layer 2⁺⁺A channel stop region 4 composed of type impurities is formed.

【0010】

The vertical transfer register 23 is an N formed on the surface side of the substrate.⁺A signal charge transfer region 5 composed of type impurities and a silicon oxide film SiO above it.₂It is composed of a transfer electrode 6 formed via an insulating layer (not shown) composed of the same. P between the photo sensor 21 and the vertical transfer register 23⁺Impurity region 7 is formed and this P⁺The mold impurity region 7 acts as a read gate 22. As the gate electrode of the read gate 22, for example, the transfer electrode 6 of the first phase (φV1) and the third phase (φV3) of the vertical transfer register 23 is also used. Further, a P well 8 as an overflow barrier is formed in the intermediate region of the N-type silicon substrate 1, and a vertical overflow drain structure that sweeps away the signal charge accumulated in the photo sensor 21 via the P well 8 to the substrate side. Is taken.

【0011】

FIG. 2 is a timing chart of the vertical transfer clocks φV1 to φV4 for driving the vertical transfer register 23 in four phases and the clock voltage φOFB applied to the P well 8 functioning as an overflow barrier (OFB). Of the four-phase vertical transfer clocks φV1 to φV4, the vertical transfer clocks φV1 and φV3 have the transfer electrodes 6 of the first phase and the third phase also serving as the gate electrodes of the read gate 22 as described above. , V_L, V_H, V_TTakes the ternary level of, and the voltage V_L, V_HIs the transfer pulse for vertical transfer, and the highest voltage V_TIs a read pulse for reading the signal charge from the photosensor 21 to the vertical transfer register 23.

【0012】

The channel potential in the cross section of FIG. 1 at the time of charge accumulation is shown in FIG. 3 (A), and the potential in the depth direction of the sensor unit 21 is shown in FIG. 3 (B). In this charge storage state, the incident light is photoelectrically converted into a charge and stored in the signal charge storage layer 3 of the photosensor 21. The accumulated signal charge is transferred to the vertical transfer register 23 via the read gate 22 because the potential of the read gate 22 becomes deeper when the read pulses of the vertical transfer clocks φV1 and φV3 are applied to the transfer electrode 6. Read out.

【0013】

The present invention is characterized by a driving method at the time of reading out this signal charge. That is, the clock voltage φOFB applied to the P well 8 is set to a low level in synchronization with the read pulses of the vertical transfer clocks φV1 and φV3. The channel potential in the cross section of FIG. 1 at the time of reading the charge is shown in FIG. 4 (A), and the potential in the depth direction of the sensor unit 21 is shown in FIG. 4 (B). As is clear from FIG. 4, by setting the clock voltage φOFB applied to the P well 8 to a low level when reading the signal charge, the potential of the overflow barrier (P well 8) becomes shallow due to the modulation, and as a result, the photosensor The potential of 21 also becomes shallow.

【0014】

In this way, when the signal charge is read from the photo sensor 21 to the vertical transfer register 23, the signal charge is read out while making the potential of the photo sensor 21 shallow, so that the signal charge is read between the photo sensor 21 and the vertical transfer register 23. The potential difference becomes larger than before. If this potential difference is large, the electric field from the photosensor 21 to the vertical transfer register 23 becomes strong, so the voltage V of the read pulse_THowever, even if it is lower than the conventional value, the signal charge can be sufficiently read out.

【0015】

According to this, the read pulse V is obtained without deteriorating the anti-blooming characteristics._TSince the voltage of the device can be lowered, the voltage of the device can be lowered. In FIG. 4, the broken line indicates the voltage V of the read pulse when reading the signal charge without making the potential of the photosensor 21 shallow._TShows the case where is lowered. In this case, since the potential of the read gate 22 becomes shallower than the potential of the photo sensor 21, the signal charge from the photo sensor 21 is left unread, and the voltage V of the read pulse is even higher._TMust be multiplied by the voltage V of the read pulse in the drive method according to the present invention._THigher voltage is required.

【0016】

In the above embodiment, the clock voltage φOFB applied to the P well 8 functioning as the overflow barrier is set to a low level at the generation timing of the read pulse, as is clear from the timing chart of FIG. As shown in the timing chart, the level may be lowered by T for a certain period including the generation timing of the read pulse of the third phase (φV3) in synchronization with the read pulse of the first phase (φV1). The same effect as in the case can be obtained. Further, in the above embodiment, in the overflow drain structure, the potential of the photosensor 21 is made shallow by applying the clock voltage φOFB to the P well 8, but the N-type silicon substrate 1 is used to perform the so-called electronic shutter operation. Read the voltage of the substrate pulse φSUB to be applied, and read the pulse V._TIt may be set to a low level in synchronization with the above case, and the same effect as the above case can be obtained.

【0017】

Furthermore, in the above-described embodiment, the case where it is applied to a CCD solid-state image sensor having a vertical OFD structure has been described, but the present invention can be similarly applied to a CCD solid-state image sensor having a horizontal OFD structure. FIG. 6 shows a cross-sectional structure diagram around the sensor portion of the CCD solid-state image sensor having a horizontal OFD structure. In the figure, an overflow barrier region 11 is continuously formed by P-type impurities next to the photosensor 21, and an overflow drain region 12 is continuously formed by N-type impurities next to the photosensor 21.

【0018】

Then, in the solid-state image sensor having the horizontal OFD structure having the above configuration, when the signal charge is read from the photosensor 21 to the vertical transfer register 23, the gate electrode arranged above the overflow barrier region 11 is synchronized with the read pulse. Apply a negative clock voltage to 13. According to this, the potential of the overflow barrier region 11 becomes shallow due to the modulation, and the potential of the photo sensor 21 can be made shallow when reading the signal charge from the photo sensor 21. Therefore, the same as in the case of the above embodiment. The effect can be obtained.

【0019】

[Effect of the invention]

As described above, according to the present invention, in the solid-state imaging device having an OFD structure, when the signal charge is read from the sensor unit to the vertical transfer unit, the signal charge reading drive is performed while making the potential of the sensor unit shallow. By doing so, the potential difference between the sensor unit and the vertical transfer unit becomes large, and the electric field from the sensor unit to the vertical transfer unit becomes strong. Therefore, even if the voltage of the read pulse is lower than before, the signal charge is sufficient. Can be read, and as a result, the voltage of the device can be reduced.

[Simple explanation of drawings]

[Figure 1]

It is sectional drawing around the sensor part in the vertical OFD structure.

[Figure 2]

It is a timing chart (No. 1) for explaining the operation of the driving method by this invention.

[Fig. 3]

It is a channel potential diagram at the time of charge accumulation.

[Fig. 4]

It is a channel potential diagram at the time of charge reading.

[Fig. 5]

It is a timing chart (No. 2) for explaining the operation of the driving method by this invention.

[Fig. 6]

It is sectional drawing around the sensor part in a horizontal OFD structure.

[Fig. 7]

It is an overall block diagram which shows the typical structural example of the interline transfer type CCD solid-state image sensor.

[Fig. 8]

It is a timing chart of vertical transfer pulses φV1 to φV4.

[Explanation of symbols]

2 hole storage layer 3 Signal charge storage layer 5 Signal charge transfer area 6 Transfer electrode 8 P well (overflow barrier) 21 photo sensor 22 Read gate 23 Vertical transfer register 24 Imaging unit 25 horizontal transfer register