Solid-state image pickup element

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to an XY address type solid-state image sensor having a shutter function having a simple configuration.

【0002】

[Conventional technology]

Conventionally, as a multifunctional solid-state image sensor, a shutter function has been added to the element itself, and it is used in a wide range of applications such as photography of high-speed moving objects and measures against flicker. In the XY address type solid-state image sensor, the shutter operation can be performed by shifting the timing of the signal reset and read operation. In order to realize such an operation, it has been conventionally known to provide two separate vertical scanning circuits for reset and read operations, as shown in, for example, Proceedings 4-7 of the 1987 Television Society National Convention. Has been.

【0003】

Next, a configuration of a solid-state image sensor in which the vertical scanning circuits are provided individually to perform the shutter operation will be described with reference to FIG. In FIG. 19, 501 is a vertical scanning circuit for signal sweeping, 502 is a horizontal scanning circuit, 503 is a vertical scanning circuit for signal reading, and 504 is a light receiving unit in which photoelectric conversion elements are arranged in a matrix in two dimensions. In order to perform the shutter operation in the solid-state image sensor having such a configuration, the signal sweeping vertical scanning circuit 501 is operated in advance of the signal reading vertical scanning circuit 503 to perform the sweeping scan.

【0004】

For example, assuming that the signal sweeping vertical scanning circuit 501 is operating n lines ahead of the signal reading vertical scanning circuit 503, first, each pixel of the light receiving unit 504 arranged in two dimensions is The light storage signal is sequentially reset by the output pulse of the vertical scanning circuit 501 for signal sweeping and the output pulse of the horizontal scanning circuit 502. Then, after a period of n lines has elapsed, the optical storage signal of each pixel is read out by the output pulses of the vertical scanning circuit 503 for signal reading and the horizontal scanning circuit 502. By the above operation, each pixel signal is read out after the light storage time of n lines, and the shutter operation is performed with the shutter time nH corresponding to the n line cycle.

【0005】

FIG. 20 shows the timing of the scanning pulses output from the vertical scanning circuits 501 and 503 during this operation. Here φ_VIs a clock with a period of 1 horizontal scanning period (1H) for operating each vertical scanning circuit 501, 503, and 501-1, 501-2, 501-3 is the output pulse of the vertical scanning circuit 501 for signal sweeping. 503-1, 5032, 503-3 are the output pulses of the vertical scanning circuit 503 for signal reading, output pulses 501-1 and 503-1, output pulses 501-2 and 5032, output pulses 501-3. And 503-3 are given to each horizontal line that controls reset and read, connected to a row of pixels, each arranged in the same row.

【0006】

As described above, in the XY address type solid-state imaging device, the shutter operation is possible by realizing the vertically-scanned pulse trains that are out of phase.

【0007】

[Problems to be Solved by the Invention]

However, when an attempt is made to realize an XY address type solid-state image sensor having a shutter function by using a conventional vertical scanning method, the following problems occur. That is, when two vertical scanning circuits for signal sweeping and signal reading are provided as shown in FIG. 19, the chip area increases and the cost of the solid-state image sensor increases.

【0008】

The present invention has been made to solve the above-mentioned problems in the conventional XY address type solid-state image sensor having a shutter function, and is a shutter having a simple configuration in which the rate of increase in chip area is reduced and the increase in cost is suppressed. An object of the present invention is to provide a solid-state image sensor having a function.

【0009】

[Means and Actions for Solving Problems]

In order to solve the above problem, in the present invention, a light receiving unit in which photoelectric conversion elements are arranged in a matrix in two dimensions as pixels and a horizontal light storage unit for sequentially addressing and reading out the light storage charge signal of each pixel of the light receiving unit. In a solid-state image sensor provided with a vertical scanning circuit and a vertical scanning circuit, a means for sequentially shifting and outputting pulses at read-out and reset timings, and a shift output by shifting from the pulse shift output means. The light receiving unit synchronizes with the means for identifying the read and reset timings by the pulse and the control signal, and the pulse shifted at the read and reset timings by the outputs from the pulse shift output means and the read / reset identification means. It is composed of a read signal for sequentially selecting the corresponding pixel rows of the above and a means for generating a reset signal.

【0010】

In the solid-state image sensor configured in this way, the light receiving unit synchronizes with the pulse shifted at the timing of reading and resetting by the reading signal and reset signal output from the reading signal and reset signal generating means constituting the vertical scanning circuit. Each pixel row of is selected, and at each selection time, a read operation and a reset operation of the optical storage charge signal are performed. Therefore, it is possible to realize an XY address type solid-state image sensor having a shutter function that does not require a plurality of vertical scanning circuits, reduces the increase in chip area, and suppresses the increase in cost.

【0011】

[Example]

Next, an embodiment will be described. FIG. 1A is a conceptual diagram showing a vertical scanning circuit 4 which is a main part of a basic embodiment of the solid-state image sensor according to the present invention. In (A) of FIG. 1, 1 is a shift register, 2 is an identification means for identifying read and reset timings using a control signal CONT, and the control signal CONT is shifted by the output of the shift register 1 and the control signal CONT is shifted by the output of the shift register 1. The read and reset timings are identified by the level of the shift control signal CONT. Reference numeral 3 denotes a means for combining the output of the shift register 1 and the output of the read / reset identification means 2 in order to output the read / reset line selection signal. FIG. 1B is a block diagram showing a solid-state imaging device configured by using the vertical scanning circuit 4 shown in FIG. 1A, where 5 is a horizontal scanning circuit and 6 is a two-dimensional photoelectric conversion element. It is a light receiving part arranged in.

【0012】

In the solid-state image sensor configured in this way, in the read / reset identification means 2 in the vertical scanning circuit 4, for example, the control signal CONT is at the H level depending on the level of the control signal CONT shifted by the output of the shift register 1. When it is at the "read" level, it is recognized as "read", and when it is at the "L" level, it is recognized as "reset", and the signals required for the read and reset operations are output. Then, in the combination means 3, the output of the shift register 1 and the output signal from the read / reset identification means 2 are combined and output as a read signal and a reset signal. With the read signal and the reset signal, each pixel row of the light receiving unit is selected in synchronization with the pulse shifted at the timing of the read and reset, and the read operation and the reset operation of the optical storage charge signal are performed at each selection time. As a result, the shutter function can be provided without providing a plurality of vertical scanning circuits.

【0013】

Next, a specific example will be described. FIG. 2 is a circuit configuration diagram showing a configuration of a vertical scanning circuit which is a main part of a first specific embodiment of a solid-state imaging device having a shutter function according to the present invention. In FIG. 2, 10 is a shift register used in a vertical scanning circuit, and 10-0, 10-1, 10-2, ... Indicates a shift register unit constituting each stage of the shift register 10. This shift register 10 has a drive pulse φ having a horizontal scanning period of one cycle._VBy, the start pulse φ_VSTHas the function of shifting. Reference numeral 12 denotes a circuit for identifying read / reset using the control signal CONT that shifts by the output of the shift register 10, and is an identification circuit corresponding to each shift register unit 10-0, 10-1, 10-2, ... Each stage of 12 has transfer gates 13-1, 13-2, 13-3, ... and two inverters 14-1, 14-2, 14-3, ..., 15-1, 15 It is composed of -2,15-3, ....

【0014】

Reference numeral 16 denotes a circuit that combines the output of the shift register 10 and the output of the read / reset identification circuit 12, and has two inputs AND17-1,17-2,17-3, ... For reset timing signal generation, and read timing. It consists of two inputs for signal generation AND18-1,18-2,18-3, ... Reset timing For signal generation 2-input AND17-1,17-2,17-3, ..., output from output terminals 11-1,11-2, ... of shift register 10 and read / reset The outputs of the inverters 14-1, 14-2, 14-3, ... Of the identification circuit 12 are input respectively, and the two inputs for generating the read timing signal AND18-1,18-2,18-3, ... The output from the output terminals 11-1, 11-2, ... of the shift register 10 and the output of the inverters 15-1, 15-2, 15-3, ... Of the read / reset identification circuit 12 Each is to be input.

【0015】

Next, the operation of the vertical scanning circuit configured in this way will be described with reference to the timing diagram shown in FIG. In this vertical scanning circuit, the drive pulse φ during one vertical scanning period._VTwo pulses that are "H" level for one cycle are set to the start pulse φ of the shift register 10._VSTAs a result, the shift operation in the shift register 10 is performed. Here, the two "H" level pulses correspond to the reset timing on one side and the read timing on the other side. Start pulse φ shown in Fig. 3_VSTIn, t₀~ t₁The timing when the period becomes "H" level is reset, t₆~ t₇The timing at which the period "H" level is reached corresponds to each read.

【0016】

Such a start pulse φ_VSTWhen is input, the output terminals 11-0, 11-1, 11-2, ... of each shift register unit 10-0, 10-1, 10-2, ... of the shift register 10 are shown in the figure. At 3, the pulses indicated by the same codes 11-0, 11-1, 11-2, ... As these output terminals are output. The control pulse CONT is recognized as a reset when the level of the control signal CONT in the read / reset identification circuit 12 is L level, and as a read when the level of the control signal CONT is H level. Since the control signal CONT in 12 is shifted by the output of the shift register 10, the outputs of the inverters 15-1, 15-2, 15-3, ... Are the same as the inverter 15- in FIG. 3, respectively. It becomes like the signal indicated by 1,15-2,15-3, ...

【0017】

Therefore, the outputs of the two inputs AND17-1,17-2, and 17-3 for generating the reset timing signal in the combinational circuit 16 are t, respectively.₂~ t₃, t₃~ t₄, t₄~ t₅A reset signal 19-1, 19-2, 19-3 that becomes "H" level is generated during the period of. The outputs of the two inputs AND18-1,18-2, and 18-3 for generating the read timing signal are t, respectively.₈~ t₉, t₉~ t₁₀, t₁₀~ t₁₁A read signal 20-1,20-2,20-3 that becomes "H" level is generated during the period of. Then, by giving these reset signals 19-1, 19-2, ... And read signals 20-1, 20-2, ... To the row selection line of the light receiving unit, the pixel rows are sequentially selected. The reset and read operations of each pixel are performed.

【0018】

As described above, according to the vertical scanning circuit having the configuration shown in FIG. 2, it is possible to perform a shutter operation having an optical storage time corresponding to the phase difference of the pulses shifted at the reset and read timings. It can be applied to a solid-state image sensor that reads out signals by the XY address method.

【0019】

In the first embodiment described above, in the shift register, a pulse having an "H" level for one cycle of the drive pulse is used for information transmission, but of course, the "L" level part is used for information transmission. It is also possible, and it is clear that the information transmission level of the read / reset identification can be made different from that of the above embodiment for the control signal.

【0020】

FIG. 4 is a circuit configuration diagram showing a modified example of the vertical scanning circuit of the first embodiment shown in FIG. 2, and the same or corresponding members as the vertical scanning circuit shown in FIG. 2 are designated by the same reference numerals. ing. In this modification, the shift operation of the control signal CONT of the read / reset identification circuit 12 is thinned out, and the number of elements can be reduced. In this modification, the shift operation of the control signal CONT is shown in two steps each, but the shift operation can be further thinned out.

【0021】

Next, as a second specific example, a vertical scanning circuit when the present invention is applied to a solid-state image sensor using a CMD (Charge Modulation Device) which is an amplification type photoelectric conversion element as a light receiving element will be described. When a video signal is output from the CMD light receiving element, the signal applied to the common gate line of each row of the CMD light receiving elements arranged in a two-dimensional array is the accumulated voltage V as shown in FIG._INT, Overflow voltage V_OF, Read voltage V_RDAnd reset voltage V_RSTPulse φ that combines the four voltages of_G1, φ_G2, ... are needed.

【0022】

Next, first, the case of the most common readout method using a gate application signal in which such four voltages are combined in a time series will be described. In the non-selected line, the accumulated voltage V during the horizontal validity period of the video signal._INTOverflow voltage V during horizontal blanking interval_OFAnd in the selected line, the read voltage V during the horizontal valid period of the video signal._RD, Reset voltage V during horizontal blanking interval_RSTIs needed. In order to apply such a signal to the gate of the CMD light receiving element, a vertical scanning circuit including a circuit having a configuration in which a selection / non-selection binary logic output is obtained from each scanning stage and a level mix circuit is required. Used.

【0023】

The level mix circuit has a configuration as shown in FIG. In Figure 6, the clock V_CK1The "L" level corresponds to the horizontal valid period of the video signal, and the "H" level corresponds to the horizontal blanking interval. The RD / RS signal is clock V_CK1Reset voltage V during the period when the level of is H_RSTIn addition, the read voltage V during the period of "L"_RDIt is a signal that becomes.

【0024】

FIG. 7 is a diagram showing the operation timing of the level mix circuit shown in FIG. S is a selection / non-selection signal, the L level is selected and the H level is non-selected. Read voltage V at output while select / deselect signal S is at L level_RDOr reset voltage V_RSTOn the other hand, during the period when the selected / unselected signal S is at the H level, the overflow voltage V is output to the output._OFOr accumulated voltage V_INTAppears and a 4-value level gateline application signal G is obtained. When this gate line application signal G is applied to the common gate line of the CMD light receiving element, the optical storage period of that line is t in FIG.₁~ t₂It will be the period of. Therefore, the variable shutter operation can be realized by controlling the timing of the selection / non-selection signal S input to the level mix circuit.

【0025】

FIG. 8 is a circuit configuration diagram showing a vertical scanning circuit of the second specific embodiment. In FIG. 8, 100 is a shift register used in the vertical scanning circuit, and 100-0, 100-1,100-2, ... Are the shift register units of each stage constituting the shift register 100. This shift register 100 has a drive pulse φ having a horizontal scanning period of one cycle._VBy start pulse φ_VSTHas the function of shifting. 110 is a circuit that identifies the read / reset timing using the control signal CONT that shifts with the output of the shift register 100, and corresponds to each shift register unit 100-0, 100-1, 100-2, ... Each stage of the identification circuit 110 has a transfer gate 130-1, 130-2, 130-3, ... And two inverters 140-1, 140-2, 140- to shift the control signal CONT. When 3, ... and 150-1, 150-2, 150-3, ... are provided and a CMD light receiving element is used as a pixel, the period during which the read operation and the reset operation are performed is 1 as described above. Since it differs within the horizontal scanning period, the clock φ that gives the read period depending on the level of the control signal CONT._RDAnd the clock φ that gives the reset period_RSThe transfer gates 160-1, 160-2, 160-3, ... And 170-1, 170-2, 170-3, ... In this embodiment, a CMOS switch is used as the transfer gate for shifting the control signal CONT, unlike the first embodiment shown in FIG. 2, but of course, it can be configured in the same manner as in the first embodiment. It is possible and the clock φ_RDAnd φ_RSThe same applies to the transfer gate for switching.

【0026】

120 Is a circuit that combines the output of the shift register 100 and the output of the read / reset identification circuit 110, and the output of the shift register 100 and the output of the read / reset identification circuit 110 are input to each stage of the combination circuit 120. It consists of two inputs NAND180-1, 180-2, 180-3, ... Then, the output of the combinational circuit 120 is input to the level mix circuit LM described above, and the output signal G₁, G₂, G₃, ... is configured to get.

【0027】

FIG. 9 is a timing chart for explaining the operation of the vertical scanning circuit shown in FIG. φ_VSTIs the start pulse of the shift register 100, and is at the H level at the timing corresponding to the reset and read operations. The control signal CONT recognizes the reset at the L level and the read at the H level. φ_RDIs a clock that becomes "H" level during the horizontal effective period when the read operation is performed when CMD is used as a light receiving element, and φ_RSIs the clock that reaches the "H" level during the horizontal blanking interval during which the reset operation is performed. S₀, S₁, S₂, S₃Is the output of the shift register units 100-0, 100-1, 100-2, 100-3 of each stage of the shift register 100 shown in Fig. 8. C₁, C₂, C₃Is a control signal that shifts in the read / reset identification circuit 110 shown in FIG. 8 by the output of the shift register 100. D₁, D₂, D₃Is the output of the read / reset identification circuit 110, and is the output D.₁, D₂, D₃Is a control signal C that shifts in the read / reset identification circuit 110, respectively.₁, C₂, C₃When is "H" level, the clock φ_RDIs output, and when it is at the L level, the clock φ_RSIs output.

【0028】

M₁, M₂, M₃Is the output of the combinational circuit 120 shown in FIG. 8, and at the reset timing, only the horizontal blanking interval, which is the reset period of the CMD light receiving element, becomes the L level in sequence, and at the read timing, the CMD light receiving element reads out. Only the horizontal effective period, which is the period, becomes the "L" level in sequence. G₁, G₂, G₃Is the output M of the combinational circuit 120₁, M₂, M₃Is an output signal when is input to the level mix circuit LM, and is a quadrature level gate line application signal applied to the common line of each line in order to operate the CMD light receiving element.

【0029】

As described above, according to the vertical scanning circuit of the second embodiment having the configuration shown in FIG. 8, a shutter operation having an optical storage time corresponding to the phase difference of the pulses shifted at the reset and read timings is performed. be able to.

【0030】

In the second embodiment, as in the first embodiment, the shift register using the H level pulse for information transmission is shown, but of course the L level part is used for information transmission. The control signal is also recognized as read at the "H" level and reset at the "L" level, but this level should be different from that of this embodiment. Is clearly possible. Further, as in the first embodiment, the shift operation of the control signal can be thinned out to reduce the number of elements.

【0031】

Next, a third specific embodiment will be described. In this embodiment, switching between 1-line interlaced scanning and non-interlaced scanning is possible, and 1-line interlaced scanning includes field accumulation and frame accumulation. Is applied. In this embodiment as well, a vertical scanning circuit when CMD is used as the light receiving element will be described.

【0032】

First, the circuit configuration of the shift register used in the vertical scanning circuit of this embodiment will be described with reference to FIG. This shift register consists of one unit of the shift register 200-0, 200-1, 200-2, ... By two clocked inverter stages surrounded by a broken line in Fig. 10, and this shift register is a symbol. When shown using, it is represented as shown in FIG. In Figures 10 and 11, / φ_V2A, / φ_V1A, / φ_V2B, / φ_V1BAre clocks φ_V2A, φ_V1A, φ_V2B, φ_V1BShows the inverted clock of.

【0033】

Figures 12, 13 and 14 show timing charts for explaining the operation of the shift register having the above configuration. The clock used for this shift register is two-phase, and as shown in FIGS. 12, 13 and 14, the shift operation is changed by controlling this two-phase clock. Start pulse φ to the first stage unit 200-0 of the shift register_VSTIs applied to the clock φ_V1AOr φ_V1BOutput S of each shift register unit 200-0, 200-1, 200-2, ...₀, S₁, S₂, ... appears.

【0034】

In FIG. 12, the clock φ_V1AAnd φ_V1B, And clock φ_V2AAnd φ_V2BOutput S sequentially shifted by clocking and₀, S₁, S₂, ... appears. In FIGS. 13 and 14, the clock φ_V1BAnd φ_V2BOr clock φ_V1AAnd φ_V2ABy fixing to the L level, the input / output levels of the shift register units to which those clocks are input become the same, and as shown in FIGS. 13 and 14, the output shifted every two units appears.

【0035】

FIG. 15 is a circuit configuration diagram showing a vertical scanning circuit of the third embodiment using the shift registers shown in FIGS. 10 and 11 above. In FIG. 15, 200 is a shift register having the configuration shown in FIGS. 10 and 11 that shifts the pulse by a drive pulse having a horizontal scanning period of one cycle. As described above, the shift operation is performed by controlling the drive pulse. Can be changed. Reference numeral 210 denotes a circuit that identifies the read / reset timing using the control signal CONT that shifts by the output of the shift register 200. The transfer gate and two inverters for shifting the control signal CONT are shown in Fig. 4. Similar to the modified example of the first embodiment shown, the number of elements is reduced by providing every two stages. In addition, when a CMD light receiving element is used as a pixel, there are two clock lines each that give a read and reset period during one horizontal scanning period, and each clock φ_RDA, φ_RDBAnd the clock φ_RSA, φ_RSBIs to be applied.

【0036】

Clock φ_RDA, φ_RSAThe line to which is applied is connected to an odd-numbered transfer gate that switches the output according to the level of the control signal CONT. On the other hand, clock φ_RDB, φ_RSBThe line to which is applied is connected to an even-numbered transfer gate. Therefore, when the control signal CONT recognizes the read timing, the clock φ is used in the odd-numbered stages._RDAHowever, in even-numbered stages, the clock φ_RDBAppears in the output, and when it is recognized as the reset timing, the clock φ in the odd-numbered stage_RSAHowever, in even-numbered stages, the clock φ_RSBAppear in the output respectively.

【0037】

220 Is a circuit that combines the output of the shift register 200 and the output of the read / reset identification circuit 210, and is composed of a 2-input NAND in which each output is input. The LM to which the output of this 2-input NAND is input is a level mix circuit having the same configuration as that of the second embodiment.

【0038】

Next, the operation of the vertical scanning circuit configured in this way will be described. In the case of non-interlaced scanning, the same operation as in the second embodiment shown in FIG. 8 may be performed. Therefore, the shift register 200 has a clock φ as shown in FIG._V1AAnd φ_V1B, And clock φ_V2AAnd φ_V2BAre the same so that the output from the shift register unit of each stage is sequentially shifted. In the read / reset identification circuit 210, the clock φ that gives the read period_RDA, φ_RDBIs a pulse that becomes H level during the horizontal effective period, and the clock φ that gives a reset period is set as in the second embodiment._RSA, φ_RSBIs a pulse that reaches the H level during the horizontal blanking interval. By setting in this way, the vertical scanning circuit shown in FIG. 15 performs the same operation as that of the second embodiment shown in FIG. 8, and non-interlaced scanning is performed.

【0039】

Next, the one-line interlaced scan will be described based on the timing chart of FIG. The one-line interlaced scanning is a scanning method in which an odd-numbered line of pixel signals is read out in one field and an even-numbered line of pixel signals is read out in the other field to form one frame. In FIG. 16, the field in which the odd-numbered line signal is read is referred to as the A field, and the field in which the even-numbered line signal is read is referred to as the B field. The RSA field is from the start pulse of the reset timing that determines the optical storage time of the signal read in the A field to the start pulse of the reset timing that determines the optical storage time of the signal read in the B field. The RSB field is from the start pulse of the reset timing that determines the optical storage time to the start pulse of the reset timing that determines the optical storage time of the signal read in the A field.

【0040】

φ_VSTIs the start pulse of the shift register 200, and becomes the H level at the timing corresponding to the read and reset. The control signal CONT recognizes the read at the "H" level and the reset at the "L" level. Clock φ_RDAIs a clock signal that is at the "H" level during the horizontal effective period, which is the read period of the CMD light receiving element in the A field, and is always at the "L" level in the B field. Clock φ_RDBIs the clock φ in the B field_RDAThe clock signal is the same as that of the A field, and the A field is always set to the L level. Clock φ_RSAIs a clock signal that becomes "H" level during the horizontal blanking interval, which is the reset period of the CMD light receiving element in the RSA field, and is always set to "L" level in the RSB field. Clock φ_RSBIs the RSB field, clock φ_RSAThe clock signal is the same as that of the RSA field of, and the level is always "L" in the RSA field.

【0041】

S₀~ S₄Is the output of the shift register 200, where the drive pulse of the shift register 200 is clock φ, as shown in FIG._V1BAnd φ_V2BIs a clock signal, and the clock φ_V1AAnd φ_V2AIs always the L level, and the shift register output S₁And S₂, S₃And S₄Are operated so that they have the same timing.

【0042】

M₁~ M₄Is the output of the combinational circuit 220. At the read timing, the output of the read / reset identification circuit 210 is clock φ in odd stages._RDA, Clock φ in even stages_RDBWill be. In the A field, φ_RDAIs the clock that becomes the H level during the horizontal effective period, which is the read period of the CMD light receiving element, so the output M of the odd-numbered stages of the combinational circuit 220₁, M₃, ... will be at the "L" level during the horizontal validity period when the output of the shift register 200 is at the "H" level. On the other hand, φ_RDBIs always at the L level, so the even-numbered output M of the combinational circuit 220₂, M₄, ... are always at "H" level. In the B field, φ_RDAIs always L level, φ_RDBIs a clock signal, so the odd-numbered stage output M of the combinational circuit 220₁, M₃, ... are always "H" level, and even-numbered output M₂, M₄, ... will be at the "L" level during the horizontal validity period when the shift register output is at the "H" level.

【0043】

On the other hand, at the reset timing, as with the read timing, in the RSA field, the output M of the odd-numbered stages of the combinational circuit 220₁, M₃However, when the output of the shift register 200 reaches the H level, it becomes the L level during the horizontal blanking interval, which is the reset period of the CMD light receiving element, and the even-numbered output M₂, M₄, ... are always "H" level. On the other hand, in the RSB field, the output M of odd-numbered stages₁, M₃, ... are always "H" level, and even-numbered output M₂, M₄, ... will be at the L level during the horizontal blanking interval when the output of the shift register 200 is at the H level.

【0044】

G₁~ G₄Is the output of the level mix circuit LM, and is the output M of the combinational circuit 220.₁~ M₄Is input to output a quadrature level signal for operating the CMD light receiving element, which is applied to the common line of each line.

【0045】

As described above, according to the vertical scanning circuit having the configuration shown in FIG. 15, the shutter operation having an optical storage time corresponding to the phase difference of the pulses shifted at the reset and read timings can be performed, and the clock can be operated. By controlling, it is possible to switch between single-line interlaced scanning and non-interlaced scanning.

【0046】

In the third embodiment as well, the information levels of H and L can be made different from those shown in the third embodiment as in the first and second embodiments. It is also clear that it is possible to further thin out the shift operation of the control signal and further reduce the number of elements. Further, in the configuration of the vertical scanning circuit shown in FIG. 15, the output load of the shift register unit of each stage is not uniform, but the output load can be made uniform by providing a dummy transistor.

【0047】

Next, a fourth specific embodiment will be described. In this embodiment, the present invention is applied to a solid-state image sensor capable of switching between two-line mixed interlaced scanning and non-interlaced scanning, which is generally used as a standard television system. A vertical scanning circuit when CMD is used as an element will be described. FIG. 17 is a circuit configuration diagram of the vertical scanning circuit of the fourth embodiment. In FIG. 17, 300 is a start pulse φ due to a drive pulse having a horizontal scanning period of one cycle._VSTIt is a shift register for shifting the above, and is configured so that the shift operation can be changed by controlling the drive pulse, as in the third embodiment shown in FIG. The 310 is a circuit that identifies read and reset using the control signal CONT that shifts by the output of the shift register 300. A transfer gate and two inverters for shifting the control signal CONT are provided in every two stages. ing. The transistor indicated by the reference numeral MD is a dummy transistor provided to make the output load of the shift register unit of each stage uniform. In addition, the read / reset identification circuit 310 has a transfer that switches and outputs a clock that gives a read / reset period during one horizontal scanning period, depending on the level of the control signal CONT, when a CMD light receiving element is used as a pixel. It is provided on the stage.

【0048】

And the clock line that gives the read period is one system, which is connected to the transfer gates of all stages, and the clock φ_RDIs applied. On the other hand, there are four clock lines that give a reset period, and each line has a clock φ every four stages._RS1, φ_RS2, φ_RS3, φ_RS4Is applied. Therefore, when the control signal CONT recognizes the read timing, each stage has a clock φ._RDAppears in the output, and when it is recognized as the reset timing, the clock φ is 1,5,9, ... in every 4th stage._RS1However, in the 2,6,10, ... stage, the clock φ_RS2However, the clock φ in the 3,7,11, ... stage_RS3However, in the 4,8,12, ... stage, the clock φ_RS4Is now appearing in the output.

【0049】

320 Is a circuit that combines the output of the shift register 300 and the output of the read / reset identification circuit 310, and each stage of the combination circuit 320 is composed of a 2-input NAND in which each output is input. Then, the output of the combinational circuit 320 is input to the level mix circuit LM configured in the same manner as in the second embodiment.

【0050】

Next, the operation of the vertical scanning circuit shown in FIG. 17 will be described. In the case of non-interlaced scanning, the same operation as in the second embodiment may be performed in the same manner as in the third embodiment shown in FIG. Therefore, the shift register 300 has a clock φ._V1AAnd φ_V1BAnd clock φ_V2AAnd φ_V2BAre the same so that the output from the shift register unit of each stage is sequentially shifted. In the read / reset identification circuit 310, the clock φ that gives the read period_RDIs the clock pulse that becomes the H level during the horizontal validity period, and the clock φ that gives the reset period_RS1, φ_RS2, φ_RS3, φ_RS4Is a clock pulse that is at the H level during the horizontal blanking interval. By setting in this way, the vertical scanning circuit shown in FIG. 17 operates in the same manner as in the second embodiment shown in FIG. 8, and non-interlaced scanning is performed.

【0051】

Next, the two-row mixed interlaced scan will be described based on the timing chart shown in FIG. In this timing chart, the field in which the signals of lines 1, 2, 3, 4, ... Are mixed is set as the A field, and the field in which the signals of lines 2, 3, 4, 5, ... Are mixed is the field. Is the B field. The RSA field is from the reset timing start pulse that determines the optical storage time of the signal read in the A field to the reset timing start pulse that determines the optical storage time of the signal read in the B field, and the opposite period is the RSAB. It is a field.

【0052】

φ_V1A, φ_V1BIs the drive pulse of the shift register 300, and in the A field, φ_V1BAlthough not shown in Fig. 18, φ_V2BOnly clock signal, φ_V1AAs in Fig. 18, although not shown in Fig. 18, φ_V2AIs always at the L level, while in the B field, φ_V1AAnd φ_V2AOnly clock signal, φ_V1BAnd φ_V2BIs always set to "L" level so that the shift timing changes for each field. In this embodiment, φ is used only for one cycle so that the shift operation is performed even at the time of field switching._V1A, φ_V2AAnd φ_V1B, φ_V2BAre configured to overlap. φ_VSTIs the start pulse, which is the pulse that reaches the "H" level at the timing of reading and resetting. In this embodiment, the period during which the reset timing reaches the H level is set to 2H. CONT is a control signal that identifies the timing of reading and resetting. In this embodiment, the H level is recognized as reading and the L level is recognized as reset.

【0053】

φ_RDIs a pulse at the H level during the horizontal effective period, which is the read period of the CMD light receiving element. φ_RS1, φ_RS2, φ_RS3, φ_RS4Is a 2H period pulse that reaches the H level during the horizontal blanking interval, which is the reset period of the CMD light receiving element._RS1And φ_RS2And φ_RS3And φ_RS4Is in phase with, and in the RSB field, φ_RS1And φ_RS4And φ_RS2And φ_RS3Are in phase with.

【0054】

S₀~ S₄Is the output of shift register 300, and in the A field due to clock control, S₁And S₂, S₃And S₄, ... at the same timing, in the B field, S₂And S₃, S₄And S not shown in Figure 18₅, ... are at the same timing.

【0055】

M₁~ M₄Is the output of the combinational circuit 320. At the read timing, the shift register output and the clock φ_RDSince the output will be at the "L" level during the period when both are at the "H" level, M in the A field.₁And M₂, M₃And M₄In the combination of, ..., and in the B field, M₂And M₃, M₄And M not shown in Figure 18₅With the combination of, ..., the level becomes "L" during the horizontal effective period, which is the read period of the CMD light receiving element. On the other hand, at the reset timing, the shift register output and the clock φ_RS1, φ_RS2, φ_RS3, φ_RS4In the RSA field, M because either of the above will be at the "L" level during the period when both are at the "H" level.₁And M₂, M₃And M₄In the combination of, ..., and in the RSB field, M₂And M₃, M₄And M₅With the combination of, ..., the level becomes "L" during the horizontal blanking interval, which is the reset period of the CMD light receiving element.

【0056】

G₁~ G₅Is the output of the level mix circuit LM, and is the output M of the combinational circuit 320.₁, M₂, M₃By inputting, ... To the level mix circuit LM, a quadrature level signal for operating the CMD light receiving element is output and applied to the common line of each line.

【0057】

As described above, by using the vertical scanning circuit having the configuration shown in FIG. 17, it is possible to perform a shutter operation having an optical storage time corresponding to the phase difference of the pulses shifted at the reset and read timings. By controlling the clock, it is possible to switch between two-line mixed interlaced scanning and non-interlaced scanning. Further, in the two-row mixed interlaced scan, since the light accumulation time of each row is the same even if the fields are different, field flicker does not occur due to the difference in the light accumulation time between the fields.

【0058】

In the fourth embodiment as well, as in the first to third embodiments, the information transmission levels of H and L can be different from those in the present embodiment, and the control signal It is clear that it is possible to further thin out the shift operation and reduce the number of elements.

【0059】

Further, as can be seen from the third and fourth embodiments, the clock lines that give the read and reset periods in the read / reset identification circuit are set to 2 systems and 4 systems, respectively, so that only clock control can be performed. A vertical scanning circuit capable of switching between non-interlaced, 2-line mixed interlaced, and 1-line interlaced scans can be configured.

【0060】

[Effect of the invention]

As described above based on the embodiment, according to the present invention, in a single vertical scanning circuit, a pixel row is selected in synchronization with a pulse that shifts at the timing of signal reading and resetting, and a signal reading operation and a signal reading operation and Since it is configured to generate a read signal and a reset signal that perform a reset operation, it is possible to switch between interlaced / non-interlaced scanning by controlling the clock, which reduces the rate of increase in chip area and suppresses the increase in cost with a simple configuration. It is possible to provide an XY address type solid-state image sensor having a shutter function.

[Simple explanation of drawings]

[Figure 1]

It is a conceptual diagram which shows the basic example of the solid-state image sensor which concerns on this invention.

[Figure 2]

It is a circuit block diagram which shows the vertical scanning circuit of 1st specific embodiment of this invention.

[Fig. 3]

It is a timing chart for demonstrating the operation of the vertical scanning circuit of 1st Example shown in FIG.

[Fig. 4]

It is a circuit block diagram which shows the modification of the vertical scanning circuit of 1st Example shown in FIG.

[Fig. 5]

It is a figure which shows the signal applied to the common gate line of each line in the solid-state image sensor using the CMD light receiving element.

[Fig. 6]

It is a circuit block diagram which shows the structural example of the level mix circuit.

[Fig. 7]

It is a timing chart for demonstrating the operation of the level mix circuit shown in FIG.

[Fig. 8]

It is a circuit block diagram which shows the vertical scanning circuit of the 2nd specific embodiment of this invention.

[Fig. 9]

It is a timing chart for demonstrating the operation of the vertical scanning circuit of the 2nd Example shown in FIG.

[Fig. 10]

It is a figure which shows the structure of the shift register used in the vertical scanning circuit of the 3rd specific embodiment of this invention.

[Fig. 11]

It is a figure which shows the shift register shown in FIG. 10 by a symbol.

[Fig. 12]

It is a timing chart for demonstrating the operation of the shift register shown in FIGS. 10 and 11.

[Fig. 13]

It is a timing chart for demonstrating the operation of the shift register shown in FIGS. 10 and 11.

[Fig. 14]

It is a timing chart for demonstrating the operation of the shift register shown in FIGS. 10 and 11.

[Fig. 15]

It is a circuit block diagram which shows the vertical scanning circuit of 3rd Example.

[Fig. 16]

It is a timing chart for demonstrating the operation of the vertical scanning circuit of the 3rd Example shown in FIG.

[Fig. 17]

It is a circuit block diagram which shows the vertical scanning circuit of the 4th specific embodiment of this invention.

[Fig. 18]

It is a timing chart for demonstrating the operation of the vertical scanning circuit of 4th Example shown in FIG.

[Fig. 19]

It is a block diagram which shows the structural example of the solid-state image sensor provided with the conventional shutter function.

[Fig. 20]

It is a figure which shows the timing of the output scanning pulse of the vertical scanning circuit in the conventional solid-state image sensor shown in FIG.

[Explanation of symbols]

1 shift register 2 Read / reset identification means 3 Combination means 4 Vertical scanning circuit 5 horizontal scanning circuit 6 Receiver