Apparatus and method for electric-power management of dram by self-refreshing

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a dynamic random access memory (DRAM) component, and more particularly to a DRAM that can be used in a personal computer such as a product compatible with an IBM PC to save power.

【0002】

[Conventional technology]

Computers generally use DRAM as working memory. The working memory provides storage of programs that can be used by the arithmetic processing unit (processor) at that time, storage of data to be processed, and storage of information displayed to the user. DRAM is used in place of the above-mentioned applications because it is superior in speed and price to other types of memory devices, such as static random access memory (SRAM) components.

【0003】

However, DRAM needs to periodically refresh the data bits stored in those cells in order to keep the stored data. This refresh occurs through the operation of the memory controller. This memory controller is usually embedded in a separate integrated circuit such as a central processing unit or a chip for other applications. This memory controller repeatedly accesses or addresses the data bit rows in the array of each DRAM unit at regular intervals. For 4 mega DRAM components, 1024 rows are typically accessed every 16 milliseconds.

【0004】

This refresh is done in several different ways. Refreshing with RAS_ only uses only the active low-level row address strobe (RAS_) to specify the row address. CAS_Before RAS_Previous CAS_ or CBR refresh puts the column address strobe (CAS_) in the active low-level state before RAS_ becomes the low-level active state, and then RAS_ for the address of each row to be refreshed. Toggle.

【0005】

Personal computers designed for portability have special requirements to save power consumption. Since such computers draw power from relatively heavy batteries, reducing the amount of power required to run a machine means reducing the size and weight of the batteries. This leads to more desirable products.

【0006】

In normal use, when the power is turned off, the personal computer saves it by writing data from the DRAM working memory to a hard disk or soft disk. If the data is not saved to disk, it will be lost when the DRAM is powered off. Later, in order to turn on the power of the personal computer to restore it and restart the processing, it is necessary to read the stored data back from the disk to the DRAM working memory. This normal operation of saving data to disk, retrieving it, and resuming processing consumes a relatively large amount of power to operate the mechanical disk drive.

【0007】

One way to reduce the power required is to put the personal computer into so-called sleep mode deterministically, from an idling state, or by automatic entry. In this mode, the personal computer holds the data in the DRAM and the power continues to be supplied to the DRAM. Refreshing occurs when the DRAM enters the internal self-refresh mode, in which case the refresh occurs slowly, thus reducing the amount of power consumed by the DRAM. This saves the power needed to operate the disk drive, but it is probably costly for the power required to hold the data in the DRAM for extended periods of time.

【0008】

A paper by Y. Konishi et al. Published in the October 1990, Vol. 25, No. 5 of the IEEE Journal of Solid-State Circuits, "38ns 4 Megabit DRAM in Battery Backup (BBU) Mode (A 38-" ns 4Mb DRAM with a Battery-Backup (BBU) mode) describes a BBU mode that provides automatic data retention with extremely low power consumption. Automatic data retention is done by a refresh generated inside the DRAM. This extremely conserved power consumption is derived from the minimization of refresh current and back-bias generator current.

【0009】

The disclosed DRAM enters BBU mode by receiving a pre-RAS CAS (CBR) refresh instruction with a low level of CAS_ for 16 ms without a CAS before RAS_refresh cycle. This BBU mode lasts as long as CAS_ is low, regardless of RAS_ level. Row refresh in BBU mode is achieved through the use of the internal refresh address counter, which is also used in CBR refresh mode.

【0010】

BBU mode refreshes by driving only one of the four array drives, the wordline drive, in one cycle instead of the four array drives that are normally driven in one cycle. The current is reduced. As a result, each array drive, also described as a peripheral circuit, will be driven every four cycles. Effectively, the turnaround refresh cycle in BBU mode is four times longer, and the average refresh cycle is four times longer than the standard refresh cycle. This reduces the array and array drive currents in one cycle of BBU mode to about one-fourth the current used in conventional CBR mode.

【0011】

BBU mode reduces its current by reducing the duty ratio of the back bias generator to about one-eighth that of normal mode. The back bias generator functions during the reset and sensing operations determined by the refresh request signal.

【0012】

NEC's data sheet on uPD424xxxx memory components shows a CBR self-refresh cycle similar to the BBU mode disclosed in the cited paper.

【0013】

[Summary of Invention]

The present invention achieves reduced power consumption in DRAM components over the sleep modes realized in the accompanying computer system through the use of power management circuits. The power management circuit reduces the power in the first circuit group required for the DRAM section to realize internal or self-refreshing of the stored data, and also in the DRAM section, etc. Alternatively, the second set of circuits reduces or eliminates the power consumed during self-refresh.

【0014】

The power management circuit in the DRAM section recognizes the signal in the personal computer instructing the sleep mode. It is a CBR refresh signal typically indicated by the absence of a RAS_cycle for about 10 microseconds. Upon recognizing the sleep mode signal, the power management circuit reduces the frequency of the oscillator on the same chip and removes power from some of the DRAM's internal circuitry. Their internal circuits may include column data paths, overvoltage detectors, and Vbb detectors.

【0015】

Some time after the recognition of the sleep mode signal, typically 100 microseconds, the power management circuit initiates a special self-refresh process, which provides specific refresh support before and after each row refresh. Turn the circuit on and off. These refresh support circuits may include a dummy cell reference voltage generator, a bitline reference voltage generator, and a Vbb pump.

【0016】

The power management circuit of the present invention realizes the above-mentioned features by a simple counter and decoder circuit. The counter and accompanying decoder circuits operate to recognize sleep mode instructions from the central processing unit and generate specific power management control signals to remove power from the desired circuit. Other ancillary detector circuits generate other power management control signals that control data refresh and turn-on / off of the refresh support circuit.

【0017】

Alternatively, you can use two separate counters. Further, this power management method is similarly effective for a computer that is powered by a normal power line, and is not limited to applications that are powered by batteries.

【0018】

[Example]

In FIG. 1, the computer system 20 includes a central arithmetic processing unit 22, a keyboard control 24, a display control 26, a power supply 28, a dynamic random access memory (DRAM) 30, a disk drive 32, and a ROM 34. These different parts are interconnected through the data bus 36, the address bus 38, and the control bus 40. The keyboard control 24 is connected to the keyboard 42 by the lead 44, and the display control 26 is connected to the display 46 by the lead 48. The power supply 28 can include 50 battery equipment, but it can also be connected to a line power supply using a plug 52.

【0019】

The central arithmetic processing unit 22 includes a memory controller 54. The DRAM 30 includes a self-refresh and power management circuit 56.

【0020】

In FIG. 2, the DRAM 30 receives the address signals A0-A8 into the row address buffer 58 and the column address buffer 60. These address signals are received into the timing and control block 62: row address strobe (low level active, RAS_), upper row address strobe (low level active, UCAS_), and lower row address strobe (low level active, low level active,). Latched into the address buffer by using the LCAS_) control signal. Lead 63 carries the desired timing and control signals from block 62 to buffers 58 and 60.

【0021】

The data signals DQ0-DQ17 are carried on the read 64 in parallel to the data input register 66 and the data output register 68. Eighteen parallel data signals propagate through read 70 from data input register 66 to 18 I / O buffers 72, and 18 parallel data signals pass through data read 74 to 18 Propagate from the I / O buffer 72 to the data output register 68. Eighteen parallel data signals propagate through read 78 from I / O buffer 72 to column decoder 76. The I / O buffer 72 also receives timing and control signals from the timing and control block 62 on the read 63. The column decoder 76 receives nine address signals in parallel from the column address buffer 60 through the read 80. The row decoder 82 receives nine address signals in parallel from the row address buffer 58 on the read 84. The column decoder 76 and row decoder 82 address individual memory cells in the entire array 86 containing 4,718,592 data bits grouped into 262,144 (256K) words in an 18-bit configuration per word. The entire array 86 contains 36 array parts such as the array part 88, and each array part contains 128K data bits. Eighteen array parts are arranged on each side of the row decoder 82. The data signal from the selected data bit row in the array portion propagates through the sense amplifier 90 to the column decoder 76.

【0022】

The write (low level active, W_) and output enable (low level active, OE_) control signals connected to the timing and control block 62 direct and control the write and read of the data signal to and from the overall array 86.

【0023】

Note that the underline following the symbol for a signal in the text indicates the active low-level state of the signal. This would facilitate word processing documentation, even if the drawings use overlines to indicate active low levels.

【0024】

The DRAM 30 also includes additional support circuitry required for proper operation. These include a voltage generator 92, a clock generator 94, a power-on reset circuit 96, a test circuit 98, an oscillator circuit 100, a board bias generator 102, a Vbb pump circuit 104, a voltage detector 106, and the self-refresh of the present invention. And power management circuits 56, but are not limited to them.

【0025】

In Figure 3, a CBR or CAS before RAS_pre-CAS_refresh occurs when the CAS_ first goes to the active low level before the RAS_ goes to the active low level. The CAS remains at the active low level while the RAS_ toggles between the active low level and the inactive high level to address 1024 consecutive rows. In this refresh mode, the external address is ignored and the refresh address is generated internally. Figure 3 shows that the CAS before RAS refresh is initiated by the transition of the RAS to the active low level at the active low level CAS_.

【0026】

In Figure 4, the CBR refresh is initiated in its usual way, but the signal RAS_ remains at an active low level. After the start of CBR refresh, the power management function of the present invention is activated at T1. The time T1 is 10 microseconds, which is set longer than one cycle of the signal RAS_ in CBR refresh mode. The function of the present invention starts the self-refresh of the entire memory array at T2 after the start of CBR refresh. The time T2 is typically 100 microseconds. The function of the present invention exits the power management and self-refresh cycle or mode by shifting the signal RAS_ to an inactive high level state.

【0027】

In FIG. 5, the power management circuit 56 includes a counter 108 that receives a clock signal from the high / low frequency oscillator 100 on the lead 110 and generates a binary count on the outputs Q1-Q7. Both the power management detection and latch 112 and the self-refresh circuit on / off decoder 114 receive these binary counts Q1-Q7. The binary count value Q7 also acts as an input clock and refresh frequency signal to the internal RAS generator 116.

【0028】

The self-refresh circuit on / off decoder 114 generates an on / off signal to the circuit group or the first circuit group 120 necessary for self-refresh on the reed 118. This circuit group includes a dummy cell reference voltage generator 122, a bitline reference voltage generator 124, and a Vbb pump 104. The power management detection and latch circuit 112 generates a self-refresh signal on the switch 132, the internal RAS generator 116, and the lead 130 leading to the high / low frequency oscillator 100. The switch 132 controls supplying Vdd or Vss to a group of circuits or a second group of circuits 134 that are unnecessary for self-refreshing. The circuits 134 that are not needed for self-refresh include a shallow Vbb detector 136, a deep Vbb detector 138, an overvoltage detector 140, and a column path 142 in the entire array.

【0029】

The internal RAS generator 116 generates an internal RAS_ signal on the lead 144. This internal RAS_ provides rowline drive in each refresh cycle.

【0030】

The self-refresh enable and reset_circuit 146 is enabled on the lead 148 in response to receiving an external RAS_ signal on the lead 150, an RLCBR on the lead 152, and a power-on reset signal POR_ on the lead 154. Generates a / reset_ signal. The enable / reset_ signal on lead 148 resets the counter 108 and the power management detection and latching circuit 112 in the low level state and allows them to operate in the high level state.

【0031】

The self-refresh signal on the lead 130 causes the oscillator 100 to generate a clock signal at a low frequency while this refresh instruction is given.

【0032】

In FIG. 6, counter 108 includes seven flip-flops 602-616. The input of the flip-flop 602 is connected to Vdd, while the subsequent flip-flops are connected to the output of the preceding flip-flop. Clock 110 is connected to the clock input of each flip-flop, and the enable / reset_ signal on read 148 is connected to all reset inputs. In this embodiment, the self-refresh enable and reset_circuit 146 includes two inverters 620 and 622 and one AND gate 624.

【0033】

In FIG. 7, the switch 132 receives a self-refresh signal on the lead 130 and supplies it to the gates of the P-channel transistor 702 and the N-channel transistor 704. Transistors 702 and 704 are MOS field effect transistors, and are described here assuming that the drain and source can be interchanged with each other. Transistor 702 connects one source / drain of it to Vdd and the other through reed 706 to unnecessary circuits for self-refreshing. Transistor 704 also has one of its sources / drains connected to Vss and the other through reed 706 to circuits 134, which are not needed for self-refreshing. The other side of the circuit group 134, which is unnecessary for these self-refreshing, is connected to Vss through the lead 707. In this way, the switch 132 completely shuts off the power supply to the circuits 134, which is unnecessary for self-refreshing, and therefore cannot use power in those circuits. In particular, circuits that are not or are not needed for self-refresh include shallow Vbb detector 136, deep Vbb detector 138, overvoltage detector 140, and column path 142.

【0034】

In FIG. 8, the on / off signal on the lead 118 and the clock signal 110 are supplied to the NAND gate 802 to generate a Vbb pump signal on the lead 804 connected to the Vbb pump 104. This controls the operation of the Vbb pump by the action of the on / off signal and the clock signal.

【0035】

In FIG. 9, the internal RAS_ signal generates a refresh pulse for each refresh cycle. Temporarily positioned by the refresh pulse, the on / off signal produces an active high level signal, which turns on and off at a point where it can be individually programmed relative to the refresh pulse transitioning to low and high levels, respectively. .. Since the internal RAS generator sequentially generates the internal RAS_ signal according to the binary count value from the binary count signal Q7, the on / off signal can be positioned relative to the refresh pulse. By modifying the decoding in the on / off decoder 114 of the self-refresh circuit, the on and off signal ends can be programmed as desired. The Vbb pump signal is a combination of the on / off signal and the clock signal, so the Vbb pump signal is of the refresh pulse determined by the internal RAS_ signal. Shows the active pump status before and after. The Vbb pump signal indicates an inactive pump state during the refresh signal. This runs the Vbb pump once before and after refreshing a row of data cells. If desired, the Vbb pump can be driven more than once before and after the refresh pulse using the appropriate gate input.

【0036】

In FIG. 10, the self-refresh circuit on / off decoder 114 receives the binary count value of the signals Q1-Q7 and generates an on / off signal on the read 118. Switches 1002 to 1014 are connected to the binary signals Q7-Q1 and Vdd, respectively. Switch 1016-1028 is connected to the binary signals Q1-Q7 and Vss, respectively. The switch 1002-1028 can be formed on the same integrated circuit as the DRAM 30 if desired, preferably by a fuse or a melting connection. Antifuse can also be used. The connection of the reed to the Vdd, Vss or binary counts Q1-Q7 determines the chosen timing of the on / off signal 118. The output from switch 1002-1014 propagates through NAND gate 1030, inverter 1032, and NAND gate 1034 to form the Y input for NAND gate 1036. The output of switch 1016-1028 propagates through inverter 1040, NAND gate 1042, inverter 1044, and NAND gate 1046 to form an X input to inverter 1036.

【0037】

In FIG. 11, the power management detection and latch circuit 112 receives the binary counts Q1-Q7 and generates a self-refresh signal on the leads 130. Each circuit 112 contains a switch 1102-1114 connected to a binary count value Q1-Q7. Switch 1102-1114 can also be formed in the semiconductor material of DRAM30 as a meltable articulated or anti-fuse. Each of them is connected to Vdd. The output of switch 1102-1114 propagates through NAND gate 1120, inverter 1122, and NAND gate 1124 to form a set input to latch 1126. The enable / reset_signal on lead 148 provides the reset_input to latch 1126. The output of latch 1126 forms a self-refresh signal on the lead 130.

【0038】

The disclosed invention thus comprises a process of retaining data in the personal computer when or during the time the personal computer enters or is set to sleep mode. This eliminates the need to save the data to disk. This process involves receiving a user's sleep mode instruction, which may be a deterministic action of pressing a button or switch from the user, but the portable computer will continue to perform over a period of time. It may be a passive operation that is not used. In this way, the personal computer can retain all the data stored in its dynamic random access memory unit during the sleep mode. This eliminates the need to move the data to disk.

【0039】

The personal computer using the memory controller internally generates a signal instructing the dynamic random access memory unit to activate the sleep mode. In response to this sleep mode signal, the dynamic random access memory unit executes self-refresh of the dynamic memory cell internally controlled by the operation of the power management circuit.

【0040】

This self-refresh occurs slower than normal refresh frequency because the power management circuit reduces the frequency of the internal oscillator. The power management circuit also operates the first set of circuits that need to operate to achieve self-refresh, essentially only when refreshing one row of memory cells. The power management circuit also removes the power normally supplied from the second circuit group of the dynamic random access memory unit. This second set of circuits does not need to operate and power may be removed during row refresh of the memory cell.

【0041】

The present invention described above can be executed by a method different from the details described here. For example, different counting and decoding schemes may be employed to reduce the frequency of oscillators on the same chip and to remove power from some of the DRAM's internal circuitry that is not needed for self-refreshing. Another embodiment is possible in another way to implement a special self-refresh process that turns a particular refresh support circuit on and off before and after each row is refreshed. Furthermore, the length of time, such as 10 microseconds or 100 microseconds, can be changed to the required length in different embodiments.

【0042】

Further, the present invention has been described in the context of a DRAM having a 4 Mbit memory array configured to supply 256 Kwords with 18 data bits per word. The claimed invention may use arrays of other dimensions and configurations within the scope of the claims.

【0043】

The following sections are further disclosed with respect to the above description. (1) It is a computer system: A. A central processing unit that executes the processing of the computer system, B. A memory that holds data to be processed by the central processing unit and instructions to be used in the central processing unit for processing the data. C. A memory controller that generates a signal indicating a sleep mode to the memory in order to control access to the memory by the central processing unit associated with the central processing unit, and a memory controller. D. The memory having a dynamic random access memory unit including an array of memory cells, and the cells are of a dynamic type, and the cells are stored at a constant frequency in order to hold the data stored in the cells. Between the first circuit group, which needs to be refreshed for each group, and the dynamic random access memory unit needs to operate to support the refreshing of the memory cells, and the refreshing of the memory cells. Including a second group of circuits whose power may be removed, the dynamic random access memory unit further refreshes the first group of circuits in response to a signal instructing a sleep mode, essentially one group of cells. A computer system comprising the memory, which is operated only on time and has come to operate to realize self-refreshing of the memory cell by removing power from the second circuit group.

【0044】

(2) The computer system according to paragraph 1, wherein the group of cells is one row of cells.

【0045】

(3) The computer system according to paragraph 1, wherein the first circuit group includes a dummy cell reference voltage generator circuit.

【0046】

(4) The computer system according to paragraph 1, wherein the first circuit group includes a bitline reference voltage generator circuit.

【0047】

(5) The computer system according to paragraph 1, wherein the first circuit group includes a Vbb pump circuit.

【0048】

(6) The computer system according to paragraph 1, wherein the second circuit group includes a shallow Vbb detector circuit.

【0049】

(7) The computer system according to paragraph 1, wherein the second circuit group includes a deep Vbb detector circuit.

【0050】

(8) The computer system according to paragraph 1, wherein the second circuit group includes an overvoltage detector circuit.

【0051】

(9) The computer system according to paragraph 1, wherein the second circuit group includes a column path circuit.

【0052】

(10) In the computer system according to paragraph 1, the power management circuit is a binary counter that generates a binary signal, and the first and second decoder circuits both decode the binary signal. Also, the first and second decoder circuits, each of which generates its own output signal, and the dual frequency oscillator, which generates a clock signal to be supplied to the binary counter and indicates one of the dual frequencies. It includes a dual frequency oscillator that receives the output signal of the second decoder circuit, the output of the first decoder circuit controls the first circuit group, and the output of the second decoder circuit is said. A computer system that controls a second set of circuits.

【0053】

(11) In the computer system described in paragraph 1, the power is removed from the second circuit group about 10 microseconds after the power management circuit recognizes CBR refresh due to the absence of RAS_ in the active state. Computer system that became.

【0054】

(12) In the computer system described in paragraph 1, for supporting the refresh of the memory cell about 100 microseconds after the power management circuit recognizes the CBR refresh due to the absence of the active RAS_. A computer system that operates the first circuit group.

【0055】

(13) In the computer system according to paragraph 1, the power management circuit is adapted to generate an internal refresh pulse for refreshing the group of memory cells, and the power management circuit is the internal. A computer system that now generates a Vbb pump signal once before and after a refresh pulse.

【0056】

(14) In the computer system according to paragraph 1, the power management circuit is adapted to generate an internal refresh pulse for refreshing the group of memory cells, and the power management circuit is a cell. A computer system that selectively operates the first circuit group before and after an internal refresh pulse for refreshing a group of.

【0057】

(15) In the computer system according to the first paragraph, the second circuit group is connected between the power supply leads of Vdd and Vss, and the power management circuit is each of the second circuit groups. A computer system that has a switch circuit for each second circuit to switch the Vdd connection to another Vss power lead to remove power from the circuit.

【0058】

(16) The computer system according to paragraph 1, wherein the computer system includes a keyboard control circuit, a display control circuit, a disk drive circuit, and a ROM circuit connected to the central arithmetic processing unit and the memory circuit. system.

【0059】

(17) A dynamic random access memory unit with a self-refresh mode: A. An entire array of dynamic memory cells, configured in the form of sub-arrays of cells connected to each other in rows and columns, which require refreshing to retain stored data. B. A first set of circuits that are connected to the array of cells and are required to operate to support the refresh of the memory cells. C. A second set of circuits that may be connected to the array of cells and deprived of power during the refresh of the memory cells, and D. Connected to the first and second circuit groups, operate the first circuit group essentially only when refreshing one row of cells, and remove power from the second operation group. A dynamic random access memory unit including a power management circuit for realizing self-refreshing of the memory cells.

【0060】

(18) The memory unit according to paragraph 17, wherein the first circuit group includes a dummy cell reference voltage generator circuit.

【0061】

(19) The memory unit according to paragraph 17, wherein the first circuit group includes a bitline reference voltage generator circuit.

【0062】

(20) The memory unit according to paragraph 17, wherein the first circuit group includes a Vbb pump circuit.

【0063】

(21) The memory unit according to paragraph 17, wherein the second circuit group includes a shallow Vbb detector circuit.

【0064】

(22) The memory unit according to paragraph 17, wherein the second circuit group includes a deep Vbb detector circuit.

【0065】

(23) The memory unit according to paragraph 17, wherein the second circuit group includes an overvoltage detector circuit.

【0066】

(24) The memory unit according to paragraph 17, wherein the second circuit group includes a column path circuit.

【0067】

(25) The memory unit according to paragraph 17, wherein the power management circuit is a binary counter that generates a binary signal, and the first and second decoder circuits both decode the binary signal. Also, the first and second decoder circuits, each of which generates its own output signal, and the dual frequency oscillator, which generates a clock signal to be supplied to the binary counter and indicates one of the dual frequencies. It includes a dual frequency oscillator that receives the output signal of the second decoder, the output of the first decoder circuit controls the first circuit group, and the output of the second decoder circuit is the second. Memory unit that controls the 2 circuit groups.

【0068】

(26) The second memory unit according to paragraph 17, about 10 microseconds after the power management circuit recognizes the CBR refresh supplied to the memory unit due to the absence of the active RAS_. A memory unit that removes power from the circuits.

【0069】

(27) The memory cell according to paragraph 17, about 100 microseconds after the power management circuit recognizes the CBR refresh supplied to the memory unit due to the absence of the active RAS_. A memory unit that operates the first circuit group to support refreshing.

【0070】

(28) The memory unit according to paragraph 17, wherein the power management circuit generates an internal refresh pulse for refreshing the row of the memory cell, and the power management circuit is inside the memory cell. A memory unit that generates a Vbb pump signal once before and after the target refresh pulse.

【0071】

(29) The memory unit according to paragraph 17, wherein the power management circuit generates an internal refresh pulse for refreshing the row of the memory cell, and the power management circuit is a cell. A memory unit that selectively operates the first circuit group before and after an internal refresh pulse for refreshing a group of.

【0072】

(30) The memory unit according to paragraph 17, wherein the second circuit group is connected between the power supply leads of Vdd and Vss, and the power management circuit is each of the second circuit groups. A memory unit that has a switch circuit for each second circuit to switch the Vdd connection to another Vss power lead to remove power from the circuit.

【0073】

(31) A way to retain data in a personal computer: A. The process of receiving sleep mode instructions from the user, B. The process of holding data in the dynamic random access memory section of a personal computer during the sleep mode. C. A step of generating a signal instructing the dynamic random access memory unit to execute the sleep mode. In response to D. The dynamic random access memory unit to generate a signal indicating that it should perform a sleep mode, die in the dynamic random access memory unit there in the step of performing a self-refresh of Na Mick memory cell Therefore, only when the step of reducing the frequency of self-refreshing from the normal frequency of refreshing and the first circuit group required to be operated to perform self-refreshing are essentially refreshing the rows of memory cells. Self-refreshing execution process, including the process of operating E. In response to the generation of a signal instructing the dynamic random access memory unit to execute sleep mode, power is removed during self-refreshing contained in the dynamic random access memory unit. A method that includes the step of removing the power normally supplied from the second circuit group, which may be acceptable.

【0074】

(32) The method according to paragraph 31, wherein the step of reducing the frequency of self-refreshing includes reducing the frequency of the oscillator in the memory unit.

【0075】

(33) In the method described in paragraph 31, the step of operating the first circuit group operates the Vbb pump once before and after the refresh of the row of the memory cell, and does not operate during the refresh. The method that includes that.

【0076】

(34) The method according to paragraph 31, wherein the step of removing the electric power includes removing the electric power from the column path.

【0077】

(35) The method according to paragraph 31, wherein the step of generating the signal includes generating a CBR refresh signal by the line address strobe being inactive for at least 10 microseconds.

【0078】

(36) The DRAM 20 removes power from the circuits 134 on the DRAM that are not needed for self-refreshing, and turns the other circuits 120 that are needed for self-refreshing on and off relative to the refresh cycle in time. It is equipped with a power management circuit 56. The power management circuit 56 includes a counter 108 and simple decoder circuits 112 and 114 that decode the binary output of the counter.

[Simple explanation of drawings]

[Figure 1]

A block diagram of a computer system configured for use as a personal computer.

[Figure 2]

The block diagram of the internal circuit of DRAM including the power management circuit of this invention.

[Fig. 3]

Timing diagram of normal CAS_before RAS_pre-CAS_refresh cycle.

[Fig. 4]

The timing diagram of the signal which indicates a sleep mode used in this invention.

[Fig. 5]

The block diagram of the power management circuit of this invention.

[Fig. 6]

The circuit diagram of the self-refresh counter used in this invention.

[Fig. 7]

A circuit used in the present invention to remove power from a particular circuit.

[Fig. 8]

Block diagram of the circuit used to turn on and off the Vbb pump in the present invention.

[Fig. 9]

A timing diagram of a signal used to achieve self-refreshing of data in DRAM using the process of the present invention that turns on and off the Vbb pump circuit.

[Fig. 10]

The circuit diagram of the on / off decoding circuit used to realize self-refresh in the present invention.

[Fig. 11]

The circuit diagram of the detection and latch circuit of the power management of this invention.

[Explanation of symbols]

20 computer system 22 Central arithmetic unit 24 keyboard control 26 Display control 28 Power supply 30 Dynamic Random Access Memory (DRAM) 32 disk drive 34 ROM 36 data bus 38th bus 40 Control bus 42 keyboard 44 lead 46 display 48 reed 50 batteries 52 plug 54 Memory controller 56 Power management circuit 58 Line address buffer 60 column address buffer 62 Timing and control block 63 lead 64 reed 66 Data input register 68 Data output register 70 reed 72 I / O buffer 74 lead 76 column decoder 78 lead 80 reed 82 line decoder 84 Lead 86 whole array 88 Array part 90 sense amplifier 92 Voltage generator 94 clock generator 96 Power on reset circuit (POR) 98 test circuit 100 oscillator circuit 102 Board bias generator 104 Vbb pump circuit 106 Voltage detector 108 counter 110 leads 112 Detection and latching 114 Self-refresh circuit on / off decoder 116 Internal RAS generator 118 Lead 120 1st circuit group 122 Dummy cell reference voltage generator 124 Bitline Reference Voltage Generator 130 leads 132 switch 134 Second circuit group 136 Shallow Vbb detector 138 Deep Vbb detector 140 Overvoltage detector 142 column route 144 leads 146 Self-refresh enable / reset_circuit 148 lead 150 reeds 152 lead 154 Lead 602-616 Flip flop 620,622 Inverter 624 AND gate 702 P-channel transistor 704 N-channel transistor 706,707 lead 802 NAND gate 804 lead 1002-1028 switch 1030 inverter 1032 inverter 1034 NAND gate 1036 NAND gate 1040 inverter 1042 NAND gate 1044 Inverter 1102-1114 switch 1120 NAND gate 1122 inverter 1124 NAND gate 1126 latch