Battery operation type information processor

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a battery-operated information processing device such as a portable personal computer, a word processor, a workstation terminal, and a pen input computer, and is particularly characterized by a battery-operated information processing device. resume) Regarding an information processing device with optimized functions.

【0002】

[Conventional technology]

Conventionally, the interruption of the process of stopping the CPU (Central Processing Unit) when the computer is not used temporarily, and the restoration from this interrupted state to the state before the CPU was stopped when it is used again are resumed. It is performed as a control process. In a computer that does not have the interrupt / return function of this process, if the computer is not used temporarily, if it is left as it is, the power consumption during operation will be applied as it is, and the power consumption will increase. Also, if all software is shut down, the power is turned off, and all software is restarted when you want to reuse it, power consumption will increase due to these processes. As described above, the power consumption can be reduced by using the functions of suspending and resuming these processes.

【0003】

Conventionally, the following methods have been known as a method of suspending and returning such processing. A method of stopping only the CPU clock (Japanese Patent Laid-Open No. 58-205226). A method of reading the state of the CPU to the outside of the CPU, saving it in the memory, and turning off the power of the CPU (Japanese Patent Laid-Open No. 3-27419). A method of recording the contents of a CPU and a memory on a non-volatile medium such as a hard disk and turning off the power of the CPU and the memory (Japanese Patent Laid-Open Nos. 56-108119 and 57-94821).

【0004】

The following two factors are important factors in the above three methods. That is, the power consumption required when the CPU is stopped in the suspended state (hereinafter referred to as the suspended power consumption) and the time required for the process of transitioning from the normal use state to the suspended state in which the CPU is stopped. Power consumption (hereinafter, this is referred to as interruption processing time and interruption processing power consumption). From these two points of view, the above three methods are given superiority or inferiority, and the ones with the highest power consumption during interruption are arranged in the order of ,, and the ones with the lowest interruption processing time and power consumption during interruption processing are arranged in the order of. It will be in order.

【0005】

In recent years, such interruption of processing is often used as an effective means for reducing power consumption in a battery-operated small information processing apparatus.

【0006】

[Problems to be Solved by the Invention]

By the way, the above method is excellent in terms of power consumption reduction effect, and it is possible to set the power consumption during interruption to 0. Therefore, data disappearance and file system destruction due to insufficient battery power do not occur. However, since the above method requires interruption processing time and power consumption during interruption processing in proportion to the amount of memory to be saved, the interruption processing time becomes longer and interruption occurs as the capacity of the memory in the information processing apparatus increases. Power consumption during processing also increases. Therefore, firstly, the interruption processing time becomes longer, which makes it difficult to use the interrupt function. Second, if the interruption and restoration are performed in a short period of time, not only is there no power consumption reduction effect, but conversely, power consumption is reduced. There is a problem of increasing.

【0007】

Therefore, it is conceivable to shorten the interruption processing time and reduce the power consumption during the interruption processing by using the method described above. However, with these methods, the power consumption during interruption cannot be set to zero. Therefore, in the worst case, the power of the battery may be exhausted when the battery drive is interrupted. In this case, there is a problem that the data is lost and the file system may be destroyed.

【0008】

As described above, in the conventional method, even with the above method, there is a problem that the interruption processing time becomes longer as the memory capacity increases, and the power consumption also increases when the interruption is performed for a short time. On the other hand, the above-mentioned method has a problem that it cannot deal with a power shortage of the battery when the processing is interrupted.

【0009】

Therefore, the technical problem to be solved by the present invention is to solve the above-mentioned problems of the prior art, and the object thereof is that the interruption processing time can be shortened, the power consumption during interruption processing can be reduced, and the power consumption during interruption processing can be reduced. Another object of the present invention is to provide a battery-operated information processing device having a function of reliably storing data even if the power supply battery runs out of power at the time of interruption.

【0010】

[Means for solving problems]

In order to achieve the above object, the present invention can hold data without a central processing unit (hereinafter referred to as CPU), a memory control means, RAM, ROM, and power supply, for example, an external storage device, an internal device. A data storage means such as a disk storage device and a non-volatile semiconductor memory, various command input means, a battery for supplying power, and the power of the battery can be selectively supplied to each part, and the power of the battery can be used. In a battery-operated information processing device having a battery control means capable of detecting a shortage, when an interruption command from the input means arrives at the CPU, the CPU interrupts the job currently being processed and owns itself. Data such as the current internal register information is saved and stored in a predetermined area of the RAM, and then the battery control means supplies power to the minimum necessary circuit elements including the RAM by a command from the CPU. The power supply to other circuit elements is stopped to shift the information processing unit to the interrupted state, and the battery control means has insufficient power of the battery in the interrupted state of the information processing unit. When the battery control means detects, the battery control means restarts the power supply to each circuit element that has stopped the power supply, and the CPU activated by this resumes the data in the RAM without the power supply. Is configured to be saved and stored in the data storage means capable of holding the CPU.

【0011】

[Action]

The battery-operated information processing device according to the present invention receives, for example, an interrupt processing start interrupt signal for receiving an input of a suspend command from the input means and notifying the CPU of the reception of the suspend command, and a current information processing device in a suspended state. An interrupt processing control unit that transmits an interrupt status signal indicating that the data is interrupted, a return processing power control signal for starting power control for recovery processing when a return command is received from the input means, and the battery control. With the battery Low signal from the means and the interruption status signal from the interruption processing control unit, the save condition determination unit that transmits the save control trigger signal for starting the save operation and the save control trigger signal described above are received. It has a save control unit that transmits a save processing power supply control signal to the battery control means and a save process start interrupt signal to the CPU, and inputs a suspend command from the input means to cause an information processing apparatus to perform interrupt processing. When the interrupt processing control unit receives the interrupt processing control unit, the interruption processing control unit transmits the interrupt processing start interrupt signal to interrupt the CPU, and the CPU receiving the interrupt interrupts its own current internal register information. Data such as the above are saved and stored in the RAM, and then the battery control means maintains the power supply to the minimum necessary circuit elements including the RAM by a command from the CPU, and the CPU, the said. When the power supply to the memory control means, the ROM, and the data storage means is stopped to shift the information processing device to the interrupted state, and when the power of the battery is insufficient in the interrupted state of the information processing device, the said The save condition determination unit that has detected the battery Low signal from the battery control means transmits the save control trigger signal to the save control unit, and the save control unit transmits the save processing power supply control signal to the battery control means. The battery control means that has received the save process power control signal restarts the power supply to the CPU, the memory control means, the ROM, and the data storage means, and is activated by this and receives the save process start interrupt signal. The CPU keeps the data in the RAM without supplying power.It is automatically saved and stored in the data storage means that can be held.

【0012】

Thus, in the present invention, when the interrupt command arrives, the current CPU register state and the like are written to a predetermined area of RAM, and then the minimum necessary circuit elements including RAM are maintained to supply power to other circuits. Since the element is shifted to the interrupted state in which the power supply is stopped, the above-mentioned interruption processing time and power consumption during the interruption processing can be reduced, and when the power shortage of the battery is detected in the interrupted state, the data in the RAM Is automatically saved and stored in a data storage means that can hold data without power supply, so that necessary data can be reliably saved even if the battery life is exhausted in the interrupted state.

【0013】

[Example]

Hereinafter, the present invention will be described with reference to the illustrated examples. FIG. 1 is a block diagram showing a configuration of a battery-operated information processing apparatus according to a first embodiment of the present invention, and FIG. 2 is a flowchart showing a CPU startup processing flow according to the present embodiment.

【0014】

In FIG. 1, 101 is a CPU (central processing unit), 102 is a memory control unit, 103 is a ROM, 104 is a RAM, and 105 is, for example, a magnetic disk storage device, an optical disk storage device, an optical magnetic disk storage device, or an IC card memory. External storage device using non-volatile storage medium such as device, 108 is address / data bus, 106 is input device such as keyboard, 107 is battery (primary battery or secondary battery), 112 is battery control device, 113 120 is a power supply line, 109 is an interruption processing control unit, 110 is a save condition determination unit, and 111 is a save control unit. Further, in FIG. 1, 114 is an interruption processing start command signal, 115 is an interruption processing start interrupt signal, 116 is an interruption processing power control signal, 117 is an interruption status signal, 118 is a reset processing start command signal, and 119 is a reset processing power control. A signal, 121 is a battery low signal, 122 is a save control trigger signal, 123 is a save processing power control signal, 124 is a save processing start interrupt signal, and 125 is a power off signal.

【0015】

The operation of the information processing apparatus of this embodiment according to the above configuration will be described below. During normal operation of this information processing device, at least CPU 101, memory control unit 102, ROM 103, RAM 104, external storage device 105, address / data bus 108, battery control device 112, input device 106, interruption processing control unit 109, etc. The power from the battery 107 is supplied via the battery control device 112 (the power is supplied to all the circuit components of the information processing device necessary for normal operation). At this time, when an interrupt command is input by the operator in the input device 106, the interrupt processing start command signal 114 is transmitted from the input device 106 to the interruption processing control unit 109, and the interruption processing control unit 109 receiving this signal 114 sends the interruption processing start command signal 114 to the CPU 101. The interruption processing start interrupt signal 115 is transmitted to. As a result, the CPU 101 that receives the interrupt processing start interrupt signal 115 interrupts the job currently being processed, saves the current register state to the stack area on the RAM 104, and transfers the processing to the interruption processing routine in the ROM 103. .. In this routine, the CPU 101 writes the address of the save destination stack to a predetermined location on the RAM 104, and finally, the interruption processing power supply for turning off the power of the CPU 101, the memory control unit 102, the ROM 103, and the external storage device 105. The control signal 116 is transmitted to the battery control device 112. After that, the battery control device 112 that received the interruption processing power control signal 116 turns off the power of the CPU 101, the memory control unit 102, the ROM 103, and the external storage device 105, and the device (information processing device) goes into the interruption state. Transition. In this interrupted state, power is supplied to at least the part of the input device 106 for inputting the return command, the interrupt processing control unit 109, the battery control device 112, and the RAM 104 (the minimum necessary circuit including the RAM 104). The element is powered).

【0016】

When a return command is input to the input device 106 by the operator in the interrupted state of the above-mentioned device, the input device 106 transmits a return process start command signal 118 to the interrupt process control unit 109, and the interrupt process receives this signal 118. The return processing power supply control signal 119 is transmitted from the control unit 109 to the battery control device 112. As a result, the battery control device 112 that has received the return processing power control signal 119 turns on the power of the CPU 101, the memory control unit 102, the ROM 103, and the external storage device 105. Then, upon turning on the power, the CPU 101 executes the startup processing routine on the ROM 103 shown in FIG. That is, in this startup processing routine, the CPU 101 reads the location where the address of the save destination stack was written during the processing for interruption (step 206 in FIG. 2), and if the address is written, the recovery processing is performed. (Step 207), and the process is transferred to the return processing routine in ROM 103 (step 208). In this return processing routine, the interrupted / saved CPU 101 register state is restored (step 209), and the processing is restarted.

【0017】

Further, when the power of the battery 107 becomes insufficient, this is detected by the voltage detecting means in the battery control device 112, and the battery low signal 121 indicating that the remaining battery level is low is detected from the battery control device 112. Is transmitted. When the battery Low signal 121 and the interruption status signal 117 transmitted from the interruption processing control unit 109 in the interruption state enter the evacuation condition determination unit 110 and both signals 117 and 121 are true, the evacuation condition determination unit 110 The evacuation control trigger signal 122 is transmitted to the evacuation control unit 111. Upon receiving the save control trigger signal 122, the save control unit 111 transmits a save processing power supply control signal 123 to the battery control device 112, and the battery control device 112 that receives this signal 123 sends the CPU 101, the memory control unit 102, and the ROM 103. , Turn on the power of the external storage device 105. Then, upon turning on the power, the CPU 101 executes the startup processing routine on the ROM 103 shown in FIG. That is, at this time, the CPU 101 first checks the evacuation process start interrupt signal 124 issued from the evacuation control unit 111, and determines whether the evacuation process is startup or evacuation processing (step 201 in FIG. 2). Then, if the save processing start interrupt signal 124 is true, the process is transferred to the save processing routine in ROM 103 (step 202), and it is confirmed that the external storage device 105 starts up in this save processing routine (step 203). ), Next, the contents of the RAM 104 are sequentially read, and the data read from the RAM 104 is written to a predetermined area of the external storage device 105 (step 204). After all the writing to the external storage device 105 is completed, the CPU 101 sends a power off signal 125 to the battery control device 112 (step 205), whereby the battery control device 112 cuts off all the power supplies and externally stores the power. The save processing routine to the device 105 ends.

【0018】

The recovery process from the saved state described above is performed as follows. Now, if the power is turned on again after replacing the battery 107 (or after charging the battery 107 if it is a secondary battery), the CPU 101 executes the startup processing routine on the ROM 103 shown in FIG. .. In this start-up process, the CPU 101 reads a part of the area (the beginning of the save area) in which the data in the RAM is saved / stored in the external storage device 105 (step 211 in FIG. 2), and the save process is performed. Whether or not it is determined (step 212). Then, when the save process has been performed, the data saved / stored in the external storage device 105 is sequentially read out and written to a predetermined area of the RAM 104 (step 214), and the data is written to the external storage device 105. After writing all the saved / stored data to the RAM 104, the area used for determining whether the saved process of the external storage device 105 is being performed (the first part of the saved area) is erased (step 215). After that, the process is transferred to the return processing routine (step 208 described above), and the return of the process is completed.

【0019】

FIG. 3 is a logic circuit diagram showing a specific example of the interruption processing control unit 109 of FIG. Assuming that the five signals related to the interruption processing control unit 109 (the signals 114,115,117,118,119 described above) are active high signals, the interruption processing control unit 109 is realized by two NOT gates and a flip-flop. The truth table of this flip-flop is as shown in FIG. 4, and any logic conforming to this truth table may be used. In the circuit shown in FIG. 3, when the interruption processing start command signal 114 becomes H (high), the Q output of the flip-flop is H and the Q CLK (inverted Q) output is L (low). It becomes. Therefore, the interrupt processing start interrupt signal 115 and the interruption status 117 signal are true, and the return processing power control signal 119 is false. After that, even if the interruption processing start command signal 114 becomes L, the flip-flop keeps the state, so that the states of the three signals are held. When the return processing start command signal 118 becomes "H", the Q output of the flip-flop is "L", Q. The output of М (inverted Q) is H. Therefore, the interrupt processing start interrupt signal 115 and the interruption status signal 117 are false, and the return processing power control signal 119 is true. After that, even if the interruption processing start command signal 118 becomes L, the states of the three signals are held by the flip-flop.

【0020】

FIG. 5 is a diagram showing a specific example of the evacuation condition determination unit 110 of FIG. Assuming that the three signals related to the evacuation condition determination unit 110 (the signals 117, 121, 122 described above) are set to active high, the evacuation condition determination unit 110 is realized by one AND gate. As is clear from FIG. 5, when both the interruption status signal 117 and the battery low signal 121 become H, the evacuation control trigger signal 122 becomes H.

【0021】

FIG. 6 is a diagram showing a specific example of the evacuation control unit 111 of FIG. Assuming that the three signals related to the evacuation control unit 111 (the signals 122, 123, 124 described above) are set to active high, the evacuation control unit 111 is realized by one latch circuit that subsequently holds the input trigger signal. As shown in FIG. 6, the evacuation control trigger signal 122 enters the latch and becomes the evacuation process start interrupt signal 124. In this example, the signal line for the evacuation control trigger signal 122 is directly connected to the signal line of the evacuation processing power supply control signal 123.

【0022】

FIG. 7 is a block diagram showing a specific example of the battery control device 112 of FIG. The battery control device 112 of this example monitors two OR gates, six power ON / OFF switches described later, and the voltage of the power supply, and the input voltage is lower than a predetermined threshold voltage. In this case, it is composed of a voltage detector whose true value is the output signal. The power ON / OFF switch used in FIG. 7 is configured by a logic circuit as shown in FIG.

【0023】

In the battery control device 112, when the power ON signal or the return processing power control signal 119 or the save processing power control signal 123 is true, all the circuit components of the information processing device from the battery 107 (external storage device 105 described above). Power is supplied to). If the interruption processing power control signal 116 is true, the power of the CPU 101, the memory control unit 102, the ROM 103, and the external storage device 105 is turned off, and the RAM 104 and the input device 106 are supplied with power from the battery 107. Furthermore, if the power off signal 125 is true, all circuit components of the information processing device (including the external storage device 105 described above) are turned off.

【0024】

As described in detail above, according to the present embodiment, when the interrupt command arrives, the current CPU register state and the like are written to a predetermined area of the RAM 104, and then power is supplied to the minimum necessary circuit elements including the RAM 104. Since the circuit elements are maintained and the other circuit elements are shifted to the interrupted state in which the power supply is stopped, the above-mentioned interruption processing time can be shortened, and the power consumption during the above-mentioned interruption processing is also reduced, which greatly contributes to the reduction of power consumption. To do. Further, when the power shortage of the battery 107 is detected in the suspended state, the data of the RAM 104 is automatically saved and stored in the external storage device (nonvolatile recording medium), so that an accident due to the battery power shortage in the suspended state is prevented. Therefore, it is possible to avoid the destruction of data in the information processing device.

【0025】

Next, a second embodiment of the present invention will be described with reference to FIGS. 9 to 11. FIG. 9 is a block diagram showing a configuration of a battery-powered information processing apparatus according to this embodiment. The difference between this embodiment and the first embodiment is that a sub-battery 701 is added and the battery 107 is used as a main battery. It is in the point that it is used as. In FIG. 9, 701 is a sub-battery 701 and 703 having a capacity smaller than that of the battery (main battery) 107, and 703 is a power line for the sub-battery. Further, the 702 is a battery control device, which can be used by switching between the main battery 107 and the sub battery 701 to selectively supply power to each part, and the voltage of the main battery 107 is the same as in the first embodiment. The battery Low signal 121 is transmitted by detecting the decrease.

【0026】

As described above, in the first embodiment, when the battery Low signal 121 is emitted when the device is interrupted, the process of saving and storing the data stored in the RAM 103 in the external storage device 105 is performed by reducing the remaining power of the battery 107. I was using it. On the other hand, in this embodiment, when the battery Low signal 121 is emitted due to the exhaustion of the battery (main battery) 107 when the device is interrupted, the power is supplied from the sub-battery 701 to save the data to the external storage device 105. The storage process is performed.

【0027】

FIG. 10 is a block diagram showing a specific example of the battery control device 702 according to the present embodiment. As shown in FIG. 10, in this example, the number of sub-battery power supply lines is increased as compared with FIG. 7, and the configuration in the power ON / OFF switch is changed as shown in FIG. In the battery control device 702 of FIG. 10, when the power ON signal or the return processing power control signal 119 is true, all the circuit components of the information processing device (including the external storage device 105 described above) are connected from the main battery 107. Power is supplied. If the interruption processing power control signal 116 is true, the power of the CPU 101, the memory control unit 102, the ROM 103, and the external storage device 105 is turned off, and the RAM 104 and the input device 106 are supplied with power from the main battery 107. When the power off signal 125 is true, all the circuit components of the information processing device (including the external storage device 105 described above) are turned off. Then, when the evacuation processing power supply control signal 123 becomes true, the sub-battery 701 supplies power to all the circuit components of the information processing device (including the external storage device 105 described above).

【0028】

In the first embodiment, the battery 107 is usually deteriorated and the battery capacity is reduced, so that it is difficult to set the threshold voltage. However, in this embodiment, since the sub-battery 701 is dedicated to the evacuation process, it is not necessary to leave the evacuation power in the main battery 107, and the threshold voltage can be easily set.

【0029】

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 12 is a block diagram showing a configuration of a battery-powered information processing device according to the present embodiment, and the difference between the present embodiment and the first embodiment is that the external storage device 105 in the first embodiment is a built-in hard disk. It was replaced with device 901. In this embodiment, the internal hard disk device 901 saves the saved data from the RAM 104, which was performed by the external storage device 105 in the first embodiment, and other operations are the same as those in the first embodiment. Is. As described above, in this embodiment, the effect of the first embodiment can be obtained even in an information processing device having an internal hard disk device 901 without having an external storage device 105.

【0030】

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a block diagram showing a configuration of a battery-powered information processing device according to the present embodiment, and the difference between the present embodiment and the first embodiment is that the external storage device 105 in the first embodiment is information-oriented. It has been replaced with a non-volatile semiconductor memory 1001 such as a flash memory or EEPROM built in a processing device. In this embodiment, the non-volatile semiconductor memory 1001 such as a flash memory or EEPROM saves the saved data from the RAM 104, which was performed by the external storage device 105 in the first embodiment, and other operations are performed. Is the same as in the first embodiment. As described above, the present embodiment is characterized in that the effects of the first and third embodiments can be obtained even in an information processing device that does not have the external storage device 105 or the internal hard disk device 901.

【0031】

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 14 is a schematic configuration diagram showing a state in which the information processing device 1100 according to the present embodiment is connected to another information processing device 1200 via a network. Although not shown, the information processing device 1100 of this embodiment is an external storage device 105, an internal hard disk device 901, and a non-volatile semiconductor memory 1001 prepared for storing saved data from the RAM 104 in each of the above-described embodiments. It has the same function as the information processing apparatus of each of the above-described embodiments, except that it does not have. In this embodiment, the data on the RAM 104 is saved in the data storage means (external storage device 105, internal hard disk device 901, or non-volatile semiconductor memory 1001) managed by the information processing device itself in each of the above-described embodiments. Instead of storing it (the saved data is not stored on the information processing device according to the present invention), it is stored on another information processing device 1200 connected by the network 1300. That is, if the information processing device 1100 of the present embodiment is in the suspended state and the battery runs short, the information processing device 1100 is temporarily activated to read the data on the RAM 104, and the read data is transmitted to the network 1300. This data is received by another information processing device 1200 connected to the network and stored in the storage device 1201 managed by the information processing device 1200. In this embodiment having such a configuration, the effect of each of the above-described embodiments can be obtained even in an information processing device having no storage means other than RAM and ROM.

【0032】

[Effect of the invention]

As described above, according to the battery-operated information processing apparatus of the present invention, when the interruption command arrives, the current CPU register state and the like are written to a predetermined area of RAM, and then the minimum necessary circuit elements including RAM are used. Since the power supply is maintained and the other circuit elements are shifted to the interrupted state in which the power supply is stopped, the above-mentioned interruption processing time can be shortened, and the power consumption during the above-mentioned interruption processing is also reduced, so that the power consumption can be reduced. It can greatly contribute to the reduction. In addition, when a power shortage of the battery is detected in the suspended state, the RAM data is automatically saved and stored in the non-volatile recording medium (because the suspended state is maintained), so that the battery is in the suspended state of processing. Even when the power is insufficient, it is possible to reliably prevent the loss of data such as in the main memory due to the power shortage of the battery and the destruction of the file being processed.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the structure of the battery-operated type information processing apparatus which concerns on 1st Embodiment of this invention.

[Figure 2]

It is a flowchart which shows the CPU start-up processing flow by 1st Embodiment of this invention.

[Fig. 3]

It is a logic circuit diagram which shows 1 specific example of the interruption processing control part of FIG.

[Fig. 4]

It is explanatory drawing which shows the truth table of the flip-flop in FIG.

[Fig. 5]

It is a logic circuit diagram which shows 1 specific example of the evacuation condition determination part of FIG.

[Fig. 6]

It is a logic circuit diagram which shows 1 specific example of the evacuation control part of FIG.

[Fig. 7]

It is a block diagram which shows 1 specific example of the battery control part of FIG.

[Fig. 8]

It is a logic circuit diagram which shows the structure of the power ON / OFF switch of FIG.

[Fig. 9]

It is a block diagram which shows the structure of the battery-operated type information processing apparatus which concerns on 2nd Embodiment of this invention.

[Fig. 10]

It is a block diagram which shows 1 specific example of the battery control part of FIG.

[Fig. 11]

It is a logic circuit diagram which shows the structure of the power ON / OFF switch of FIG.

[Fig. 12]

It is a block diagram which shows the structure of the battery-operated type information processing apparatus which concerns on 3rd Embodiment of this invention.

[Fig. 13]

It is a block diagram which shows the structure of the battery-operated type information processing apparatus which concerns on 4th Embodiment of this invention.

[Fig. 14]

It is a schematic block diagram which shows the state that the information processing apparatus according to 5th Embodiment of this invention was connected to the other information processing apparatus by a network.

[Explanation of symbols]

101 Central Processing Unit (CPU) 102 Memory control unit 103 ROM 104 RAM 105 External storage 106 Input device 107 Battery 108 Address / Data Bus 109 Suspension processing control unit 110 Evacuation condition judgment unit 111 Evacuation control unit 112 Battery controller 113 Power line 114 Suspension processing start command signal 115 Interruption processing start interrupt signal 116 Suspension processing power control signal 117 Suspension status signal 118 Return processing start command signal 119 Recovery processing power control signal 120 battery power line 121 Battery Low signal 122 Evacuation control trigger signal 123 Evacuation processing power control signal 124 Save processing start interrupt signal 125 Power off signal 701 sub-battery 702 Battery controller 901 Internal hard disk drive 1001 Non-volatile semiconductor memory 1100 Information processing device 1200 Other information processing equipment 1300 network