Semiconductor integrated circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a semiconductor integrated circuit having a boost power generation circuit for charging a load at high speed, and particularly in a semiconductor integrated circuit for memory, a fail bit address determination test for relieving redundant of a defective memory cell is surely performed. Regarding semiconductor integrated circuits that enable.

【0002】

[Conventional technology]

In semiconductor integrated circuits for memory, in order to improve the yield, a redundant relief method is generally used to replace defective memory cells due to miniaturization with normal cells and relieve them, and to identify the address of the memory cell to be relieved. A fail bit address determination test is being conducted in.

【0003】

An example of a conventional semiconductor integrated circuit will be described below with reference to the drawings. FIG. 6 shows an example of a connection diagram of a step-up power probe inspection pad of a conventional semiconductor integrated circuit. In FIG. 6, the word line drive circuit 3, which is not shown, charges the word line to a boost potential using a word line driver determined by decoding the address to transfer the transfer gate of the selected memory cell. turn on. The boost power probe inspection pad 1 is connected to the boost power supply wiring 6 between the boost power generation circuit 2 that supplies the boost voltage to the word line drive circuit 3 and the word line drive circuit 3.

【0004】

The conventional semiconductor integrated circuit configured as described above will be described below in terms of its usage and operation at the initial stage of development.

【0005】

First, at the time of probing inspection, whether or not the step-up power generation circuit 2 realizes the performance as designed is checked by passing the needle 5 on the step-up power probe inspection pad 1 to check the boost voltage (VPP) and the current consumption of the step-up power generation circuit 2. It is possible to measure. Further, the step-up power generation circuit 2 is originally a circuit for replenishing the electric charge consumed by the word line inside the chip and has a low current supply capacity. Therefore, when the selected word line is short-circuited with another power source. The current flows more than the capacity of the step-up power generation circuit 2.

【0006】

Therefore, when the selected word line is short-circuited, the boost voltage (VPP) potential drops, and the next time a normal word line is selected, the boost voltage does not recover to the full potential, causing malfunction. Could happen. By connecting the first external power supply 7 having a voltage equivalent to the boosted power supply voltage capable of supplying current to the boosted power probe inspection pad 1, the above malfunction could be prevented. The current supply capacity of the step-up power generation circuit 2 is sufficient for a chip that has undergone redundant relief after the failbit address determination test.

【0007】

[Problems to be Solved by the Invention]

However, in the above-mentioned conventional configuration, as described below, a short circuit of the word line may be overlooked during the fail bit address determination test.

【0008】

FIG. 7 is an assumed diagram in which the selected word line and the non-selected word line are short-circuited, and FIG. 3 shows an enlarged view of one part of the circuit in FIG.

【0009】

When the selected word line 34 is short-circuited with the non-selected word line 35 in FIGS. 7 and 3, the resistance value R2 of the resistance 17 between the boost power generation circuit 2 and the word line drive circuit 3 and the word line drive circuit 3 and the ground are grounded. Resistance value R3 of resistance 18 between power supply pads (hereinafter VSS pads) 4, resistance value R4 of resistance 33 of short circuit 14, resistance value R5 of resistance 15 of selected word line 34, short circuit with selected word line 34 Non-selected word line 35 resistance 16 resistance value R6, word line drive signal drive transistor 30 on resistance Rtr1, word line charging transistor 31 on resistance Rtr2, word line grounding transistor 32 on resistance Rtr3 The boosted voltage (VPP) is distributed according to the resistance ratio of the above, and in the fail bit address determination test, the decrease in the word line potential due to a short circuit (Equation 1) depends on the pad arrangement and the position of the short circuit. Has a problem that the circuit cannot detect the potential drop of the word line, and the short-circuited word line to be relieved may be regarded as a normal word line.

【0010】

[Number 1]

<img file="JPH06150697A_D0001.tif" />【0011】

The present invention solves the above-mentioned conventional problems, and at the time of a fail bit address determination test, the drop of the word line potential due to the word line short circuit is set to a potential that can be reliably detected by the circuit regardless of the pad arrangement and the position of the short circuit. An object of the present invention is to provide a semiconductor integrated circuit that can be controlled.

【0012】

[Means for solving problems]

In order to solve the above problems, the semiconductor integrated circuit of the present invention boosts a boost power probe inspection pad to which a first external power supply that supplies a voltage equivalent to that of a boost power supply can be connected via a voltage drop resistor. A configuration connected to the power supply wiring, or a configuration in which a boost power probe inspection pad to which a second external power supply that supplies an optimized voltage lower than the boost power supply voltage can be connected is connected to the boost power supply wiring. Have.

【0013】

[Action]

According to the above configuration, in the fail bit address determination test at the chip development stage, the present invention causes a malfunction caused by a drop in the boosted voltage due to a short circuit between the selected word line and another power supply to the step-up power supply probe inspection pad equivalent to the boosted power supply. Prevent by connecting a first power supply of voltage. Furthermore, the drop in the ward line potential when the ward wire is short-circuited is controlled by a resistor with the optimum resistance value inserted between the boost power generation circuit and the step-up power probe inspection pad, or the boost power probe inspection is performed instead of inserting a resistor. The pad is controlled by an optimized second external power supply that is lower than the boost potential, making it possible to reliably grasp the redundant relief address of the chip.

【0014】

[Example]

(Example 1) Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

【0015】

In FIG. 1, the boost power generation circuit 2, which is not shown in FIG. 1, supplies voltage to the gate and source of the word line driver in the word line drive circuit 3, and the word line drive circuit 3 has a low address. The word line is selected by the decode signal, the word line is charged at high speed, and the transfer gate in the memory cell is turned on. The step-up power probe inspection pad 1 is connected to the step-up power supply wiring 6 between the word line drive circuit 3 and the step-up power source generation circuit 2 via a resistor 8 calculated from the pad arrangement and the position of the word line short circuit in the worst case. It is connected.

【0016】

The operation of the semiconductor integrated circuit configured as described above when the selected word line and the non-selected word line are short-circuited at the time of the fail bit address determination test will be described. Fig. 2 is an assumed diagram when the selected word line and the non-selected word line are short-circuited, and Fig. 3 is an enlarged view of a part of the circuit in Fig. 2.

【0017】

In FIGS. 2 and 3, it is assumed that one selected word line 34 and one non-selected word line 35 are short-circuited during the fail bit address determination test. The number of non-selected word lines that are short-circuited is set to one because the word line potential is the highest in that case. At this time, the resistance value of the resistance 8 inserted between the boost power generation circuit 2 and the boost power probe inspection pad 1 is R1, and the resistance value of the wiring resistance 17 between the boost power generation circuit 2 and the word line drive circuit 3 is R2. , The resistance value of the wiring resistance 18 between the word line drive circuit 3 and the VSS pad 4 is R3, the resistance value of the wiring resistance 15 of the selected word line 34 is R5, and the resistance value of the wiring resistance 16 of the non-selected word line 35 is R6. , The resistance value of the short-circuit resistance 33 is R4, the on-resistance of the ward wire drive signal drive transistor 30 is Rtr1, the on-resistance of the ward wire charging transistor 31 is Rtr2, and the on-resistance of the ward wire grounding transistor 32 is Rtr3. .. At this time, if the potential of the boost power supply is VPP, the potential of the selected word line 34 becomes (Equation 2), and the resistance value R1 of the resistance 8 between the step-up power probe inspection pad 1 and the boost power generation circuit 2 is optimized. By doing so, the potential of the selected word line can be reliably lowered, so that a short circuit of the word line can be reliably detected.

【0018】

[Number 2]

<img file="JPH06150697A_D0002.tif" />【0019】

Next, taking the pad arrangement as shown in FIGS. 2 and 3 as an example, the optimum value of the resistance value R1 of the resistor 8 added between the step-up power generation circuit 2 and the step-up power probe inspection pad 1 is actually obtained. The conditions for the optimum value are (1) when the selected word line is short-circuited with the non-selected word line, the potential of the selected word line drops sufficiently, and (2) the selected word line is changed by changing the address. When changing from a shorted word line to a non-shorted word line, the time it takes for the potential of the word line drive signal to recover to the boost potential is shorter than the time it takes for a normal word line to rise after an address change. Imposing.

【0020】

First, the condition (1) of the optimum value is imposed, and the lower limit of the resistance value of the added resistor is considered. In such a pad arrangement, the potential of the shorted word line becomes the highest when the word line closest to the pad is short-circuited. The on-resistance Rtr1 of the p-channel transistor 30 for the word line drive signal drive is 200Ω, the on-resistance Rtr2 of the n-channel transistor 31 for the word line drive is 200Ω, and the on-resistance Rtr3 of the n-channel transistor 32 for the word line precharge is 450Ω. Assuming that the wiring resistance value R5 of the selected word line 34 and the wiring resistance value R6 of the non-selected word line are equal, R5 = R6 = 2KΩ. The sheet resistance of 1-layer aluminum is 55 mΩ, the sheet resistance of 2-layer aluminum is 35 mΩ, the wiring width of the boost power supply wiring is 10 μm, the wiring length is 4 mm, the wiring width of the VSS power supply wiring is 50 μm, and the wiring length is 4 mm. Assuming that the wiring in the side direction is 2-layer aluminum and the wiring in the short side direction of the chip is 1-layer aluminum, the resistance value R2 of the wiring resistance 17 for boost power supply is 22Ω, and the resistance value R3 of the wiring resistance 18 for VSS power supply is 4Ω. If the resistance value R4 of the line short-circuited resistance 33 is 68Ω and the potential of the boosted power supply is VPP, the short-circuited word line potential Vwl is 0.51VPP when the additional resistance 8 is not inserted.

【0021】

When the word line potential is the most required in the fail bit judgment test, write H (VDD) to the memory cell 40 in Fig. 4, and then read H, and set the precharge potential of bit lines 46 and 47 to 1.5 V. If the threshold voltage of the transfer gate 42 in the memory cell is 1V, the potential of the word line is simply 2.5V or more even if the sensitivity of the sense amplifier 41 is not taken into consideration, and if the boost voltage VPP of the boost power supply is 5V, it is 0.5. VPP or higher is required. Considering the sensitivity of the sense amplifier, a higher word line potential is required. Therefore, in order to reduce the shorted word line potential to 0.5 VPP or less, the resistance value R1 of the additional resistor 8 must be 100 Ω or more.

【0022】

Next, consider the upper limit of the resistance value of the resistor to be added by imposing the condition (2) of the optimum value. In the fail bit address determination test, the chip precharge period of 1.5 μS will be secured. In the original evaluation, the judgment time per chip is several tens of nS, but a high resistance value is desirable in order to judge the fail bit more reliably. If the resistance is high, it becomes difficult to satisfy the condition (2). Since the additional resistance is used only in the fail bit address determination test, the cycle time is lengthened during the test. When applied to an actual device, the increase in test time due to the above test is also small in view of the total test time. It is necessary to recover from the potential of 0.5VPP to the potential of VPP within 1.5μS, and if the parasitic capacitance to the ward line drive circuit of the boost power generation circuit is 300pF, the value of the resistance value R1 of the additional resistor 8 is 5KΩ or less. Will have to be.

【0023】

From the consideration given the above conditions (1) and (2), it can be seen that the resistance value R1 of the additional resistor 8 should be in the range of 100Ω to 5KΩ. If you want to shorten the evaluation time, you can set the value of the added resistor to a small value of several hundred Ω, and if you want to make a reliable judgment in consideration of the variation in the short-circuit resistance, you can add a large resistor.

【0024】

(Example 2) FIG. 5 is a configuration diagram of a semiconductor integrated circuit in the second embodiment. As shown in FIG. 5 in comparison with FIG. 1, instead of inserting an optimized resistor between the boost power generation circuit 2 and the boost power probe inspection pad 1, the boost power is supplied to the boost power probe inspection pad 1. It has a configuration that can connect an optimized second external power supply 8 below the voltage.

【0025】

Hereinafter, the operation during the fail bit address determination test will be considered using the same example as above. Consider the condition that the potential of the word line is sufficiently lowered when the selected word line is short-circuited with the non-selected word line. From the result of the previous example, when R1 = 0, the potential of the shorted word line was 0.51VPP, so if the voltage of the second external power supply is V2, the potential of the shorted word line is 0.51V2. ..

【0026】

Therefore, it can be seen that the value of the voltage V2 of the second external power supply should be V2 &lt;0.5VPP / 0.51 in order to surely grasp the short circuit of the word line. In this case, since the resistance component is about 20Ω and the delay time is about 10nS, the potential of the boosted power supply recovers by the time the measurement is started after switching the address from the short-circuited selected word line to the normal word line. The conditions to be done are satisfied.

【0027】

[Effect of the invention]

As described above, in the present invention, the boost power supply probe inspection pad can be connected to the boost power supply wiring via the optimized additional resistance, or a second external power supply having a voltage lower than that of the boost power supply can be connected to the boost power supply. By connecting the probe inspection pad to the boost power supply wiring, the ward line potential at the time of ward line short circuit can be sufficiently lowered, and the ward line short circuit can be reliably detected at the time of the fail bit address determination test.

【0028】

Furthermore, since it is not necessary to design the current supply capacity of the boost power generation circuit to be particularly large in consideration of the short circuit between the boost power supply and other power supplies, it is possible to suppress the power consumption of the boost power generation circuit and perform complicated control. It is not necessary to design a step-up power supply that requires the above, and the design period can be shortened.

[Simple explanation of drawings]

[Figure 1]

Configuration diagram of the step-up power probe inspection pad according to the first embodiment of the present invention. [Figure 2]

Assumed diagram of word line short circuit [Fig. 3]

Partially enlarged view of the assumed view of word line short circuit [Fig. 4]

DRAM memory cell configuration diagram [Fig. 5]

Configuration diagram of the step-up power probe inspection pad in Example 2 of the present invention [Fig. 6]

Configuration diagram of conventional chip boost power probe inspection pad [Fig. 7]

Assumed diagram of word line short circuit in a conventional chip [Explanation of symbols]

1 Step-up power probe inspection pad 2 Boost power generation circuit 3-word line drive circuit 4 Grounded power supply (VSS) pad 7 1st external power supply 8 Optimized additional resistance 9 Optimized second power supply 14,33 Short part 15 Selected word line resistance 16 Non-selected word line resistance 17 Wiring resistance between boost power generation circuit and word line drive circuit 18 word line drive circuit, wiring resistance between VSS pads 19 VSS capacitance between the boost power generation circuit and the word line drive circuit 34 Selected word line 35 unselected word line