Semiconductor memory device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a semiconductor memory device.

【0002】

[Conventional technology]

Recently, the density of semiconductor memory devices has been increasing, and in particular, the high integration and high density of dynamic random access memory (so-called DRAM) have been remarkable. The development of such DRAM is largely due to the structure of memory cells, which occupy more than half of the chip size, and the ingenuity of their layout.

【0003】

FIG. 7 is an example of such a memory cell. FIG. 7 (A) is a plan view of a main part of the memory cell, and FIG. 7 (B) is a cross-sectional view taken along the line bb ́ in FIG. 7 (A). FIG. 8 shows an example of a conventional semiconductor memory device having the memory cell array configuration of FIG. 7.

【0004】

In FIG. 7, 1 is a conductor constituting a bit wire, 2 is a drain portion also connected to the bit wire, 3 is a gate electrode of a signal readout MOS transistor constituting a word wire, and 4 is the above signal readout MOS. The gate oxide film of the transistor, 5 is the cell plate electrode connected to the cell plate voltage source, 6 is the insulating film for separating between cells, 7 is the interlayer insulating film between each conductor, and 8 is the opposite conductive type to the drain part 2. Semiconductor substrate, 9 is the source part of the memory cell, 10 is the charge storage part of the first memory cell, 11 is the charge storage part of the second memory cell, 12 is the insulating film constituting the first memory cell capacitor, 13 Is an insulating film constituting the second memory cell capacitor, and 14 is a contact window connecting the conductor 1 constituting the bit wire and the drain portion 2.

【0005】

The memory cell shown in FIG. 7 has a memory cell structure in which a trench type and a stack type are used in combination.

【0006】

In FIG. 5, SA1 to SA4 are sense amplifiers, ROWDEC is a low decoder, WL1 to WL12 are word lines, BL1 to BL8 are bit lines, and Q51 to Q58 are N-channel MOS transistors. VCC is the power supply voltage. The circle at the intersection of the word line and the bit line indicates the memory cell.

【0007】

The memory cell array of this semiconductor memory device is composed of word lines WL1 to WL12 and bit lines BL1 to BL8 in a grid pattern, and one in two for any one word line selection. A memory cell capacitor is connected to a ratio of bit lines, and it is a so-called folded bit line type memory cell array.

【0008】

In this memory cell, the gate electrode 3 constituting the word line is set to the logic voltage H, so that the information of the conductor 1 constituting the bit line is transmitted from the drain portion 2 to the source portion 9 and is charged in the memory cell. The operation of accumulating in 10 or 11 (writing state) or reading the information accumulated in the charge storage unit 10 or 11 of the memory cell into 1 bit line (reading state) is performed.

【0009】

[Problems to be Solved by the Invention]

In a memory cell array in which a memory cell capacitor is connected to one in two bit lines for the selection of any one word line as shown in Fig. 7, it is connected to any one bit line. The number of memory cells generated is one in two, and one out of every two word lines intersecting any one bit line is simply a bit line, not as a gate electrode of a MOS transistor. Is just crossing.

【0010】

As described above, in the memory cell array configuration of the conventional example, since the ratio of the word lines crossing the bit lines is only one in two, it is a big obstacle to the reduction of the memory cells in the bit line direction. In this example, the two word lines that cross the upper part of the memory cell capacitor forming portion that uses both the trench type and the stack type in FIG. 7B are obstacles to the reduction of the memory cell.

【0011】

An object of the present invention is to provide a semiconductor memory device capable of reducing memory cells to achieve high integration and high density.

【0012】

[Means for solving problems]

In order to solve the above problems, in the semiconductor memory device of the present invention, a memory cell capacitor is connected to the source portion of the memory cell transistor, a plurality of word lines constituting the gate electrode of the memory cell transistor, and the memory cell transistor. A memory cell array in which a plurality of bit lines connected to the drain portion of the above are configured in a grid pattern, and the bit lines at a ratio of 2 to 3 with respect to the selection of any one word line are described. It is composed of a memory cell array to which a memory cell transistor is connected.

【0013】

In order to solve the above problems, the semiconductor memory device of the present invention has a circuit that divides each bit line of the plurality of bit lines into a bit line group of the first part and a bit line group of the second part. Then, with respect to the selection of any one word line of the plurality of word lines, the first bit line and the second bit line to which the memory cell capacitor is connected at a ratio of two to three, and 3 With respect to the third bit line to which the memory cell capacitor is not connected at a rate of one to the book, the bit line belonging to the bit line group of the first part of the first bit line and the third bit line It has a first bit line selection circuit for connecting a bit line belonging to the bit line group of the first part of the bit lines to the first sense amplifier, and the bit of the second part of the second bit line. It has a second bit line selection circuit that connects the bit line belonging to the line group and the bit line belonging to the bit line group of the second portion of the third bit line to the second sense amplifier.

【0014】

In order to solve the above problems, in the semiconductor memory device of the present invention, a memory cell capacitor is connected to the source portion of the memory cell transistor, a plurality of word lines constituting the gate electrode of the memory cell transistor, and the memory cell transistor. The plurality of bit lines connected to the drain portion of the above and the plurality of bit lines are divided into a bit line group of the first part and a bit line group of the second part, and the three bit lines having the first part It has a bit line dividing circuit that connects two of them and connects two of the three bit lines with the second part, and 3 for the selection of any one word line of the word line. To the first bit line and the second bit line to which the memory cell capacitor is connected at a ratio of two to the book, and to the third bit line to which the memory cell capacitor is not connected at a ratio of one to three. On the other hand, the bit line belonging to the bit line group of the first part of the first bit line and the bit line belonging to the bit line group of the first part of the third bit line are the first sense amplifier. It has a first bit line selection circuit connected to, and the bit line belonging to the bit line group of the second part of the second bit line and the bit line of the second part of the third bit line. It has a second bit line selection circuit that connects the bit lines belonging to the group to the second sense amplifier.

【0015】

[Action]

As described above, in the memory cell array configuration of the present invention, the memory cell capacitor is connected to two out of three bit lines for the selection of any one word line, and thus is arbitrary. The number of memory cells connected to one bit line is two in three, and one in three word lines intersecting any one bit line is the gate electrode of the transistor. It simply crosses the bit line, and the ratio of word lines that simply cross the bit line is one in three, which is less than the ratio of one in two in the past, and it is possible to reduce the memory cell in the bit line direction. Become. Furthermore, the memory cell capacitor is connected to 2 out of 3 bit lines for the selection of any 1 word line, and the memory cell capacitor is not connected to 1 in 3 bit lines. Therefore, by using this bit line, it is possible to adopt the folded bit line method, and the unused bit line should be placed next to the bit line pair that performs the sense operation by selecting the bit line of the sense amplifier. It is less affected by the adjacent bit line that operates, and the malfunction of the sense operation is reduced.

【0016】

[Example]

A first embodiment of the semiconductor memory device according to the present invention will be described with reference to FIGS. 1 and 2.

【0017】

First, FIG. 1 (A) is a plan view of a main part of the memory cell, and FIG. 1 (B) is a cross-sectional view of FIG. 1 (A) in aa ́. FIG. 2 is a circuit diagram of the layout of the semiconductor memory device of the present invention in the memory cell array configuration of FIG.

【0018】

In FIG. 1, 1 is a conductor constituting a bit wire, 2 is a drain portion also connected to the bit wire, 3 is a gate electrode of a signal reading MOS transistor forming a word wire, and 4 is the signal reading MOS transistor. Gate oxide film, 5 is a cell plate electrode connected to a cell plate voltage source, 6 is an insulating film for cell-cell separation, 7 is an interlayer insulating film between each conductor, and 8 is a drain part connected to a bit wire. 9 is the source part of the memory cell, 10 is the charge storage part of the first memory cell, 11 is the charge storage part of the second memory cell, and 12 is the first memory cell capacitor. 13 is an insulating film constituting the second memory cell capacitor, and 14 is a contact window connecting the bit wire 1 and the drain portion 2. This memory cell is a memory cell in which a trench type and a stack type are used together.

【0019】

In Fig. 2, SA1 to SA4 are sense amplifiers, ROWDEC1 and ROWDEC2 are low decoders, BLSC1 and BLSC2 are bit line selection circuits, WL1 to WL12 are word lines, BL1 to BL12 are bit lines, and BLS21 to BLS26 are bit line selection signals. Q21 to Q44 are N-channel MOS transistors, and the circles at the intersections of word lines and bit lines are memory cells.

【0020】

In this memory cell, the information of the bit line 1 is stored in the charge storage part 10 or 11 of the memory cell from the drain part 2 through the source part 9 by setting the gate electrode constituting the word line 3 to the logic voltage H. It performs an operation of reading (writing state) or reading information stored in the charge storage unit 10 or 11 of the memory cell to bit line 1 (reading state).

【0021】

In this memory cell array, word lines and bit lines are configured in a grid pattern, and a memory cell capacitor is connected to two out of three bit lines for the selection of any one word line. This is to promote the reduction of memory cells in the bit line direction.

【0022】

With such a configuration, the number of memory cells connected to any one bit line is 2 out of 3 at the intersection with the word line, and 3 of the word lines intersecting with any 1 bit line. Only one word line per book will simply cross the bit line, not as the gate electrode of the transistor. The ratio of word lines that simply cross the bit line is one in three, which is less than the ratio of one in two in the past, and the memory cell in the bit line direction can be reduced. Assuming that the line width and the space width of the word line are constant, this memory cell is reduced to 3/4 of that of the conventional memory cell.

【0023】

Next, a specific operation in the layout of the memory cell array of the semiconductor memory device of FIG. 2 will be described.

【0024】

For example, when the word line WL2 is selected, charge information is read out to the bit lines BL1, BL3, BL4, and BL6, and at this time, the bit line selection signals BLS22, BLS23, BLS24, and BLS25 are selected by the bit line selection circuits BLSC1 and BLSC2. , Bit lines BL1 and BL7, Bit lines BL3 and BL9, Bit lines BL4 and BL10, Bit lines BL6 and BL12 are amplified by the sense amplifiers SA1, SA2, SA3, and SA4, respectively. This is a so-called open bit line system configuration.

【0025】

As described above, in the memory cell array configuration of this embodiment, the memory cell capacitor is connected to two out of three bit lines for the selection of any one word line. The number of memory cells connected to any one bit line is two in three, and one in three word lines intersecting any one bit line is a transistor. It simply crosses the bit line, not as a gate electrode, and the number of word lines that simply cross the bit line is one in three, which is less than the conventional ratio of one in two, and memory in the bit line direction. The cell can be reduced.

【0026】

Furthermore, the memory cell capacitor is connected to 2 out of 3 bit lines for the selection of any 1 word line, and the memory cell capacitor is not connected to 1 in 3 bit lines. Therefore, by using this bit line, it is possible to adopt the folded bit line method, and the unused bit line should be placed next to the bit line pair that performs the sense operation by selecting the bit line of the sense amplifier. It is less affected by the adjacent bit line that operates, and the malfunction of the sense operation is reduced.

【0027】

A second embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG.

【0028】

FIG. 3 is a circuit diagram of the layout of the semiconductor memory device in the memory cell array configuration of FIG.

【0029】

In Fig. 3, SA1 to SA4 are sense amplifiers, ROWDEC1 and ROWDEC2 are low decoders, BLSC1 and BLSC2 are bit line selection circuits, BLEQ1 and BLEQ2 are bit line precharge control circuits, and BLE21 to BLE26 are bit line precharge control signals, VBE. Is a bit line precharge voltage signal, WL1 to WL12 is a word line, BL1 to BL12 is a bit line, BLS21 to BLS26 is a bit line selection signal, Q21 to Q44 is an N-channel MOS transistor, and at the intersection of the word line and the bit line. The mark is a memory cell.

【0030】

A specific operation in the layout of the memory cell array of the semiconductor memory device of FIG. 3 will be described. The basics are the same as in the first embodiment of FIG.

【0031】

For example, when the word line WL2 is selected, when the bit line precharge control signal bit lines BLE22 and BLE25 have the logic voltage H and the BLE21, BLE23, BLE24 and BLE26 have the logic voltage L, the N channel type. The MOS transistors Q302, Q305, Q308, and Q311 are turned on, and Q301, Q303, Q304, Q306, Q307, Q309, Q310, and Q312 are turned off. After that, when the word line WL2 is selected, the charge information is read out to BL1, BL3, BL4, and BL6. At this time, the bit line selection signals BLS22, BLS23, BLS24, and BLS25 are selected by the bit line selection circuits BLSC1 and BLSC2. As a result, the charge information of the bit lines BL1 and BL7, the bit lines BL3 and BL9, the bit lines BL4 and BL10, and the bit lines BL6 and BL12 is amplified by the sense amplifiers SA1, SA2, SA3, and SA4, respectively. At this time, the bit lines BL2, BL5, BL8, and BL11 are precharged and fixed to the bit line precharge voltage signal VBP.

【0032】

In this way, by fixing the bit line adjacent to the bit line from which the charge information is read to a certain potential, the charge information of the bit line from which the charge information is read is read against noise or when the charge information is amplified. Become stronger.

【0033】

A third embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG.

【0034】

FIG. 4 is a circuit diagram of the layout of the semiconductor memory device in the memory cell array configuration of FIG.

【0035】

In FIG. 4, SA1 to SA4 are sense amplifiers, ROWDEC1 and ROWDEC2 are low decoders, BLSC1 and BLSC2 are bit line selection circuits, BLDC is a bit line dividing circuit, WL1 to WL12 are word lines, BL1 to BL12 are bit lines, and BLS11 to BLS14 is a bit line selection signal, BLD is a bit line division signal, Q1 to Q18 are N-channel type MOS transistors, the circles at the intersections of word lines and bit lines are memory cells, and VCC is the power supply voltage.

【0036】

A specific operation in the layout of the memory cell array of the semiconductor memory device of FIG. 4 will be described.

【0037】

First, in the initial state, the bit line dividing signal BLD output from the bit line dividing circuit BLDC is the logic voltage H. Here, for example, when the word line WL2 is selected, the charge information is read out to the bit lines BL1 and BL7, BL3 and BL9, BL4 and BL10, and BL6 and BL12.

【0038】

Next, the bit line division signal BLD becomes the logic voltage L, and the bit lines BL1 and BL7, BL3 and BL9, BL4 and BL10, and BL6 and BL12 are divided, respectively. Here, the bit line selection signals BLS12 and BLS14 are selected by the bit line selection circuits BLSC1 and BLSC2, and the bit line BL1 and BL2, the bit line BL8 and BL9, the bit line BL4 and BL5, and the bit line BL11 and BL12 are the sense amplifiers SA1 and BL12, respectively. Charge information is amplified by SA2, SA3, and SA4. This is a so-called folded bit line system configuration.

【0039】

With such a circuit configuration, a folded bit line system can be configured. Therefore, as is generally said in the folded bit line method, the imbalance of noise from the word line to the bit line is small, and the bit line becomes stronger against noise as compared with the first embodiment.

【0040】

Similarly, in the memory cell array configuration of this embodiment, the memory cell capacitor is connected to two out of three bit lines for the selection of any one word line, so that it is arbitrary. The number of memory cells connected to one bit line is two in three, and one in three word lines intersecting any one bit line is the gate of the transistor. It simply crosses the bit line, not as an electrode, and the ratio of word lines that simply cross the bit line is one in three, which is less than the ratio of one in two in the past, and the memory cell in the bit line direction can be reduced. It becomes.

【0041】

Furthermore, the memory cell capacitor is connected to 2 out of 3 bit lines for the selection of any 1 word line, and the memory cell capacitor is not connected to 1 in 3 bit lines. Therefore, by using this bit line, it is possible to adopt the folded bit line method, and the unused bit line should be placed next to the bit line pair that performs the sense operation by selecting the bit line of the sense amplifier. It is less affected by the adjacent bit line that operates, and the malfunction of the sense operation is reduced.

【0042】

A fourth embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG.

【0043】

FIG. 5 is a circuit diagram of the layout of the semiconductor memory device in the memory cell array configuration of FIG.

【0044】

In FIG. 5, SA1 to SA4 are sense amplifiers, ROWDEC1 and ROWDEC2 are low decoders, BLSC1 and BLSC2 are bit line selection circuits, BLDC5 is a bit line dividing circuit, WL1 to WL12 are word lines, BL1 to BL12 are bit lines, and BLS11 to BLS14 is a bit line selection signal, BLD51 to BLD53 are bit line division signals, Q1 to Q18 are N-channel type MOS transistors, the circles at the intersections of word lines and bit lines are memory cells, and VCC is the power supply voltage.

【0045】

A specific operation in the layout of the memory cell array of the semiconductor memory device of FIG. 5 will be described.

【0046】

First, in the initial state, the bit line dividing signals BLD51 to BLD53 output from the bit line dividing circuit BLDC5 have a logic voltage H. Here, for example, when the word line WL2 is selected, the bit line dividing signals BLD51 and BLD52 are set to the logic voltage L, and then the word line WL2 is selected. Then, the charge information is read out to the bit lines BL1, BL3 and BL9, BL4, BL6 and BL12, the bit line selection signals BLS12 and BLS14 are selected by the bit line selection circuits BLSC1 and BLSC2, and the bit line BL1 and BL2 and the bit line are selected. The charge information is amplified by the sense amplifiers SA1, SA2, SA3, and SA4 for BL8 and BL9, bit lines BL4 and BL5, and bit lines BL11 and BL12, respectively.

【0047】

With such a circuit configuration, the word line is selected, and the bit line dividing circuit is operated to divide the bit line before the charge information is read out to the bit line. Therefore, the bit wire does not receive noise after the charge information is read out from the bit wire.

【0048】

A fifth embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG.

【0049】

FIG. 6 is a circuit diagram of the layout of the semiconductor memory device in the memory cell array configuration of FIG.

【0050】

In FIG. 6, SA1 to SA4 are sense amplifiers, ROWDEC1 and ROWDEC2 are low decoders, BLSC1 and BLSC2 are bit line selection circuits, BLDC6 is a bit line dividing circuit, WL1 to WL12 are word lines, BL1 to BL12 are bit lines, and BLS11 to BLS14 is a bit line selection signal, BLD61 to BLD69 are bit line division signals, Q1 to Q72 are N-channel type MOS transistors, the circles at the intersections of word lines and bit lines are memory cells, and VCC is the power supply voltage.

【0051】

A specific operation in the layout of the memory cell array of the semiconductor memory device of FIG. 6 will be described.

【0052】

First, in the initial state, the bit line dividing signals BLD61 to BLD69 output from the bit line dividing circuit BLDC6 have a logic voltage H. Here, for example, when the word line WL2 is selected, the bit line dividing signals BLD61, BLD62, BLD64, BLD65, BLD67, BLD68, and BLD69 are set to the logical voltage L, and then the word line WL2 is selected. Then, the charge information is read out to the bit lines BL1, BL3 and BL9, BL4, BL6 and BL12. The bit line selection signals BLS12 and BLS14 are selected by the bit line selection circuits BLSC1 and BLSC2, and the bit line BL1 and BL2, the bit line BL8 and BL9, the bit line BL4 and BL5, and the bit line BL11 and BL12 are the sense amplifiers SA1 and SA2, respectively. , SA3, SA4 amplifies the charge information.

【0053】

At this time, the bit lines BL3 and BL9, the bit lines BL6 and BL12, the bit lines BL7 and BL8, and the bit lines BL10 and BL11 are electrically connected via the N-channel MOS transistors Q3, Q6, Q61, and Q64, respectively. This is for the purpose of equalizing the load of the bit line pairs connected to one sense amplifier. This eliminates the load imbalance between the bit line pairs and stabilizes the operation of the sense amplifier.

【0054】

Similarly, in the memory cell array configuration of this embodiment, the memory cell capacitor is connected to two out of three bit lines for the selection of any one word line, so that it is arbitrary. The number of memory cells connected to one bit line is two in three, and one in three word lines intersecting any one bit line is the gate of the transistor. It simply crosses the bit line, not as an electrode, and the ratio of word lines that simply cross the bit line is one in three, which is less than the ratio of one in two in the past, and the memory cell in the bit line direction can be reduced. It becomes.

【0055】

Furthermore, the memory cell capacitor is connected to 2 out of 3 bit lines for the selection of any 1 word line, and the memory cell capacitor is not connected to 1 in 3 bit lines. Therefore, by using this bit line, it is possible to adopt the folded bit line method, and the unused bit line should be placed next to the bit line pair that performs the sense operation by selecting the bit line of the sense amplifier. It is less affected by the adjacent bit line that operates, and the malfunction of the sense operation is reduced.

【0056】

As described above, according to the semiconductor memory device having the memory cell array configuration of the present invention, the memory cell can be reduced, and more sensitive sense operation such as a folded bit line method is possible, which is inexpensive and stable. It has become possible to supply an operating semiconductor memory device, and its practical effect is extremely large.

【0057】

[Effect of the invention]

As described above, according to the semiconductor memory device having the memory cell array configuration of the present invention, the memory cell can be reduced, and more sensitive sense operation such as a folded bit line method is possible, which is inexpensive and stable. It has become possible to supply an operating semiconductor memory device, and its practical effect is extremely large.

[Simple explanation of drawings]

[Figure 1]

Configuration diagram of the semiconductor memory device according to an embodiment of the present invention [Figure 2]

A circuit diagram showing a first embodiment of the layout of the semiconductor memory device of the present invention. [Fig. 3]

A circuit diagram showing a first embodiment of the layout of the semiconductor memory device of the present invention. [Fig. 4]

A circuit diagram showing a second embodiment of the layout of the semiconductor memory device of the present invention. [Fig. 5]

A circuit diagram showing a third embodiment of the layout of the semiconductor memory device of the present invention. [Fig. 6]

A circuit diagram showing a fourth embodiment of the layout of the semiconductor memory device of the present invention. [Fig. 7]

Configuration diagram of a conventional semiconductor memory device [Fig. 8]

A circuit diagram showing an example of the layout of a conventional semiconductor memory device [Explanation of symbols]

1 Conductor 2 Drain part 3 Gate electrode 4 Gate oxide film 5 cell plate electrode 6 Insulating film for separation 7 interlayer insulating film 8 Semiconductor substrate 9 Source section 10, 11 Charge storage 12, 13 Insulating film 14 contact window