Semiconductor integrated device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention particularly relates to a level amplifier circuit including a logic function created by using a BICMOS process in which a bipolar transistor and a MOS transistor are formed on the same substrate.

【0002】

[Conventional technology]

In the RAM of the ECL input / output interface, in addition to the level amplifier from the internal pseudo ECL signal to the CMOS signal level, a decoding function for selecting a memory cell, a control circuit for controlling various circuits, etc. are required.

【0003】

Conventionally, a level amplifier circuit as shown in FIG. 6 is used, a level amplifier is performed from an internal pseudo-ECL signal to a CMOS signal level, and then a CMOS gate or a BICMOS gate is used to configure a decoding circuit and a control circuit as shown in FIG. The circuit has been proposed. In FIG. 5, the level amplifier LA and the logic unit LG are composed of separate gate stages. In FIG. 6, the input signals are a CMOS current mirror type amplifier circuit SA1 composed of N-channel MOS transistors N1 and N2 configured as current mirrors and P-channel MOS transistor loads P1 and P2, and a P-channel MOS transistor P3. N-channel MOS transistors N3, N4, N5 and NPN bipolar transistors Q2, Q3 The level is amplified by the BICMOS inverter type amplifier circuit SA2 composed of. Further, the conventional circuit of FIG. 6 does not have a logic function and functions only as a simple level amplifier circuit. Therefore, the logic function must be realized by the ECL gate before the level amplifier, or by the CMOS gate or BICMOS gate after the level amplifier. The conventional example shown in FIG. 5 is a case where the logic is constructed by the CMOS gate after the level amplifier.

【0004】

[Problems to be Solved by the Invention]

When the logic is constructed by the CMOS gate or BICMOS gate after the level amplifier as in the conventional example shown in FIG. 5, there is a drawback that the delay time increases. Further, when the logic is constructed by the ECL gate before the level amplifier, the speed can be increased, but there is a drawback that the current consumption becomes very large. Furthermore, when using a conventional level amplifier as shown in Fig. 6, a total of 10 transistors are required, including 5 N-channel MOS transistors, 3 P-channel MOS transistors, and 2 NPN bipolar transistors. Therefore, there is a drawback that the layout area is greatly increased. The present invention solves the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated device having a high speed and a low layout area (high integration).

【0005】

[Means for solving problems]

The first conductive type emitter is connected to the first node, the base is connected to the second node, and the collector is connected to the output terminal. The first bipolar transistor and the first load connected between the first power supply and the output terminal. A circuit, a second bipolar transistor in which a first conductive emitter is connected to a first node and a base and a collector are connected to a second node, and the first is provided between the second node and the first power supply. A second load circuit that sets the current value that flows into the collector of the bipolar transistor, and an emitter current value of the first bipolar transistor and the second bipolar that are provided between the first node and the second power supply. It is characterized by including a current switching circuit for switching the emitter current value of the transistor.

【0006】

The current switching circuit described above is characterized by including a series-parallel circuit of a first conductive MOS transistor.

【0007】

[Example]

Hereinafter, examples of the present invention will be described with reference to the drawings.

【0008】

FIG. 1 is a diagram relating to an embodiment of the present invention.

【0009】

Figure 1 Example shows a current switching circuit SWN consisting of a series-parallel circuit of N-channel MOS transistors provided between VSS and node NO2, and an NPN in which the base and collector are connected to node NO1 and the emitter is connected to node NO2. Bipolar transistor Q1, collector is output DO, base is connected to node NO1, emitter is connected to node NO2, NPN bipolar transistor Q0 is connected to Q1 and current mirror, load circuit Z1 provided between VDD and output DO, and VDD. It is composed of a P-channel MOS transistor P0, which is provided between the and node NO1 and the gate is connected to VSS, the source is VDD, and the drain is connected to node NO1. Further, in this embodiment, the SWN has input signals INI1 to INIJ from the first series circuit composed of N-channel MOS transistors N11 to N1K in which input signals IN11 to IN1K are input to each gate. It has a configuration in which I series circuits up to the I-th series circuit consisting of N-channel MOS transistors NI1 to NIJ input to the gate are provided in parallel between VSS and node NO2.

【0010】

The operation will be briefly explained. In the current switching circuit SWN of FIG. 1, when any one of the series circuits from the first series circuit to the Ith series circuit conducts (that is, in the case of the first series circuit, the N channel Q1 turns on (when all the gate input signals IN11 to IN1K of the MOS transistors N11 to N1K are high). When Q1 turns on, Q0 connected to the current mirror turns on. If the on resistance of Q0 is set sufficiently smaller than that of Z1, the output DO will be lowered to the VSS potential when Q0 is turned on. Conversely, Q1 turns off when all of the first series circuit to the Ith series circuit are non-conducting. When Q1 turns off, Q0 connected to the current mirror turns off. Therefore, the output DO is raised to the VDD potential via Z1. As the load circuit Z1, a normally-on P-channel MOS transistor as shown in FIG. 2 and a resistor as shown in FIG. 3 can be considered.

【0011】

Here, VSS + VTHN (threshold voltage of N-channel transistor) + VBG (backgate bias voltage) is required as the high level of the input signal, and the value is usually about VSS + 1.5V. A VSS potential is required as the low level. In other words, 1.5V is sufficient as the input amplitude of SWN.

【0012】

In the embodiment of FIG. 4, a current switching circuit SWP consisting of a series-parallel circuit of P-channel MOS transistors provided between VDD and node NO4, and a PNP in which the base and collector are connected to node NO3 and the emitter is connected to node NO4. Bipolar transistor Q3, collector is output DO, base is connected to node NO3, emitter is connected to node 4, PNP bipolar transistor Q2 is connected to Q3 and current mirror, load circuit Z2 provided between VSS and output DO, and VSS. It is composed of an N-channel MOS transistor N0, which is provided between the and node NO3, and the gate is connected to VDD, the source is to VSS, and the drain is connected to node NO3.

【0013】

Further, in the present embodiment, the SWP has input signals IPI1 to IPIJ from the first series circuit composed of P channel MOS transistors P11 to P1K in which input signals IP11 to IP1K are input to each gate. It has a configuration in which I series circuits up to the I-th series circuit consisting of P-channel MOS transistors PI1 to PIJ input to the gate are provided in parallel between VDD and NO4.

【0014】

The operation will be briefly explained. In the current switching circuit SWP of FIG. 4, when any one of the series circuits from the first series circuit to the Ith series circuit conducts (that is, in the case of the first series circuit, the P channel When all the gate input signals IP11 to IP1K of the MOS transistors P11 to P1K are low, Q3 turns on. When Q3 turns on, the Q2 connected to the current mirror turns on. Set the on resistance of Q2 sufficiently smaller than that of Z2. Then, when Q2 is turned on, the output DO is raised to almost VDD potential. Conversely, if all of the first series circuit to the Ith series circuit are non-conducting, Q3 is turned off. Q3 is turned off. Then, Q2 connected to the current mirror is turned off. Therefore, the output DO is lowered to the VSS potential via Z2. Here, the low level of the input signal is VDD-VTHP (threshold voltage of P channel transistor) -VBG (back). (Gate bias voltage) is required, and its value is usually about VDD-1.5V. That is, 1.5V is sufficient as the input amplitude of the SWP.

【0015】

Although the present invention has been specifically described above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be variously modified without departing from the gist thereof.

【0016】

[Effect of the invention]

Since the logic function and the level amplifier function are realized by the same gate, the number of gate stages and the number of transistors can be reduced, and there is an effect that a semiconductor integrated device having a high speed and a low layout area (high integration) can be obtained.

[Simple explanation of drawings]

[Figure 1]

The figure which shows the 1st Example of this invention.

[Figure 2]

The figure which shows the 1st Example of the load circuit Z1 in FIG. 1 which shows the 1st Example of this invention.

[Fig. 3]

The figure which shows the 2nd Example of the load circuit Z1 in FIG. 1 which shows the 1st Example of this invention.

[Fig. 4]

The figure which shows the 2nd Example of this invention.

[Fig. 5]

The figure which shows the 1st conventional example which concerns on this invention.

[Fig. 6]

The figure which shows an example of the level amplifier circuit LA in FIG. 5 which shows the 1st conventional example which concerns on this invention.

[Explanation of symbols]

VDD High voltage side power supply. VSS: Low voltage side power supply. IN11, IN1K, INI1, INIJ IP11, IP1K, IPI1, IPIJ Current switching circuit input signal. N11, N1K, NI1, NIJ N-channel MOS transistors that make up the current switching circuit. P11, P1K, PI1, PIJ P-channel MOS transistors that make up the current switching circuit. SWN, SWP Current switching circuit. NO1 First node. NO2 Second node. NO3 Third node. NO4 ... the fourth node. DO Output. Z1, Z2 Load circuit. Q0, Q1 Current mirror configuration NPN bipolar transistor. Q2, Q3 PNP bipolar transistor with current mirror configuration. PL Normal on P channel MOS transistor. RL Resistance. LA Level amplifier circuit. LG CMOS or BICMOS logic circuit. SA1 CMOS current mirror type amplifier. SA2 BICMOS inverter type amplifier. INPUT Level amplifier input signal. OUTPUT Level amplifier output signal. VREF: Reference signal for CMOS current mirror amplifier. N0, N1, N2, N3, N4, N5 ... N-channel MOS transistor. P0, P1, P2, P3 P channel MOS transistor. Q4, Q5 NPN bipolar transistor.