Method for separating integrated circuits formed on a substrate.

Description: TECHNICAL FIELD [Detailed description of the invention]

Industrial application fields The present invention relates to a large semiconductor array, i.e., a method of separating semiconductor circuit chips with edges that can be accurately matched so that a straight or two-dimensional array can be made by arranging semiconductor integrated circuit chips in a row. Problems to be solved by the invention There is a growing demand for an easy and inexpensive way to create a full page width linear or two-dimensional array of semiconductor integrated circuit IC chips that can be butted, or lined up, glued together. In addition, there is a demand for the emergence of large-area arrays that can be used for various purposes such as displays, image bars for reading / writing, and thermal ink jet printers. Usually, a large number of IC chips are formed on one wafer and separated from each other by dicing (separation by shearing). The chips are then tested and the accepted chips are glued together to make a larger array. This dicing process can leave edges along the etched crystal planes to cause "cracks" and sometimes damage the passage layer above the circuit near the "cracks". Another problem with dicing is that the chips arranged in a row do not have the same height, and the surfaces of the chips arranged in a row are at an angle with each other, resulting in a slight lateral misalignment. is there. Means to solve problems An object of the present invention is to cut an integrated circuit chip without causing the above problems by using a method not previously disclosed so that a plurality of integrated circuit chips can be joined to each other to fabricate a large area array. To provide a way to separate. The first feature of the present invention is that the integrated circuit chip can be separated without damaging the edge or surface of the integrated circuit chip by combining the direction-dependent etching process and the reactive ion etching process. , The secondary processing method of the wafer is modified. More specifically, the method for separating the integrated circuit chip formed on the crystal substrate according to the present invention is as follows: (a) The upper surface of the substrate is subjected to reactive ion etching processing along a predetermined intersecting horizontal boundary line. A step of forming a plurality of vertical deep grooves, (b) a step of filling the deep groove with an etchingable substance, (c) a step of forming a plurality of integrated circuits on the surface of the substrate having the horizontal boundary line, (d). ) It consists of a step of inactivating both sides of the substrate and (e) a step of etching a plurality of V-shaped groove holes on the lower surface of the substrate in a substantially straight line with the vertical deep groove, and the etching extends to the inside of the deep groove. Suitable for corroding and removing the etchable material from the deep groove, the integrated circuit chip is separated by the combined action of the upper surface etching step (a) and the lower surface etching step (e), and The integrated circuit chip is characterized by having a flat joint surface formed by the formation of the vertical deep groove. Conventional technology The following patent documents are considered to be relevant to the present invention. That is, U.S. Patent No. 4612554 discloses an ink jet printing head and its manufacturing method from two identical parts. A plurality of V-shaped grooves are formed on each portion of the print head by anisotropic etching in each portion of the print head between the linear arrays of the heating elements. With these V-grooves, the print heads are automatically self-aligned and fit together. U.S. Pat. No. 4,599,952 discloses a method of creating a deep groove having a side wall that is approximately perpendicular to a silicon substrate. The deep groove is formed by sequentially forming a thick photoresist layer, a silicon nitride layer, and a thin photoresist layer on the surface of the substrate, and then by reactive ion etching. Example As shown in FIGS. 1 and 2, a wafer 10 made of a semiconductor material has two surfaces 12, 14 facing each other. Here, for convenience of explanation, it is assumed that the wafer 10 is silicon having a <100> crystal axis. However, the method disclosed below is basically applicable to most crystalline materials and is not limited to silicon. In FIG. 2, the surface of the wafer 10 is divided into grid patterns by imaginary lines 16 and 18, and the IC chip 20 is formed in the lattice pattern. The IC chips 20 may be the same or different from each other depending on a specific application. For convenience of explanation, it is assumed that the chip 20 is a plurality of identical integrated circuits that can be individually assembled to form a page width ink jet printing head. Each IC chip 20 contains an array of electronic detection or printing elements and the associated network required to enable chip interconnection. In the case of a specific ink jet printing device, each chip 20 has a transistor-driven logic circuit having an integrated structure and a resistance heating element formed therein. A U.S. patent application filed with the United States Patent Office on March 4, 1988 by the transferee of the present invention, the title of the invention "Monolithic silicon integrated circuit chip for thermal ink jet printer" has this function. The processing steps used to manufacture the integrated circuit chips are described. After a proper processing step, the chips 20 are separated and then joined to each other to make a page width thermal ink jet printing head with a channel plate and a resistance heating element. Before processing the wafer 10 to form a desired circuit, a processing process is performed along the separation lines 16 and 18 so that the chip 20 can be separated in the final etching process. FIG. 3 is a cross-sectional view of the area surrounded by the circle in FIG. The circled area extends to both sides of one decoupling line 16. It can be seen that the following explanations are all related to the tip cutting process along lines 16 and 18. As shown in Fig. 3, p⁺Layer 30 is formed in the wafer 10 about 10 microns below the surface. p⁺The layer 30 has a thickness of about 2 to 3 microns and is used as a direction-dependent etching stop (stop layer) when the wafer 10 is etched from the lower surface. p⁺Layer 30 is a thinly doped p with a thickness of about 10 microns.^-Formed under layer 32. The first processing step is to etch a vertical deep groove 34 on the wafer surface using a reactive ion etching method. As is well known, this etching is characterized by high precision directional (anisotropic) corrosion and is capable of forming nearly vertical sidewalls. The deep groove 34 generally has a width of 2-3 microns and a depth of about 10 microns and penetrates layers 30 and 32. After the deep groove 34 is oxidized to form the field oxide layer 36, low-pressure CVD polysilicon is filled to form the polysilicon plug 38. Next, a normal wafer fabrication sequence using the method disclosed in the US patent application is carried out to form a logic element and a detection element or a printing element of the circuit. After the logic circuit and resistance heating element production sequence is complete, the tip is inactivated with PSG, followed by plasma-enhanced Si on the top and bottom of the tip.₃N₄Cover with coating layers 40 and 42 (Fig. 4). Before depositing the plasma nitride layer, the PSG is patterned (opened) to expose the bonding pad. The plasma nitride coating layer on the underside of the wafer is then patterned and aligned using an IR aligner. The plasma nitriding coating layer is p⁺Prevents erosion of the completed network by direction-dependent etching (indicated by the dotted line) ending at layer 30. Alternatively, it can be applied to a silicone or ethylene-propylene elastic material and tightened tightly with Teflon or stainless steel to protect the front surface of the wafer. Etching is done through an ODE etching mask, but the consistency between the mask and the deep groove 34 is not important as long as the mask is given some tolerance. ODE etching is interrupted and a short wet oxide etching agent (oxide buffer etching agent) is used to corrode and penetrate the oxide layer 44 (Fig. 3) at the bottom of the deep groove 34. Next, the wafer is filled with ODE etching liquid to corrode and remove the polysilicon plug 38. FIG. 5 shows a wafer at the time when two adjacent chips 20 are separated as a result of the deep groove 34 encountering the groove hole by CDE etching. At this point, Si₃N₄Layers 40 and 42 are removed by plasma etching and a metal film is applied to the underside of the wafer for ohm contact. As shown in FIG. 5, this separation results in flat joint surfaces 50,52 on each chip 20. The two tips 20 do not have sharp edges and can be struck against each other, assuming they can be used by testing. Since the joint surface is flat, some lateral (vertical) misalignment is tolerated, and the tips can be reliably and correctly aligned. This processing and etching separation are performed along all lines 16 and 18 (Fig. 2) that separate all chips 20. Chips can then be tested, lined up and glued to other chips to produce the desired large area array. The following second method can be used to make the chips 20 described in FIGS. 3-5. In those figures, as a first example, the deep groove 34 is made to have flat joint surfaces 50,52. Alternatively, a joint surface with irregularly rust-shaped contours can be formed, as shown in FIGS. 6 and 7. The joint surfaces with different contours can be formed by exposing the resist with a suitable photomask. Each of the joint surfaces 50a, 50b, 52b fits snugly with the mating surface of the other side so that the two joint surfaces fit together like a tongue and a groove. This modification ensures accurate alignment in both the X and Y directions, and guarantees not only end-face to end-face alignment, but also side-to-side alignment. As yet another modification, in certain applications, p shown in Figure 5.^-P instead of board⁺It may be desirable to use a substrate. For example, in the case of modern CMOS chips with high density memory, as a starting material, p^-/ p⁺Wafers are used. Figure 5 p^-Layer 14 p⁺To replace with a layer, the p + layer p in the ODE etching solution^-Its resistivity must be high enough to be etched at the same speed as the wafer. Actually 0.01Ω^-A resistivity of cm is appropriate. As a third modification, for certain applications where the active circuit can be offset towards the center of the wafer (eg, thermal ink jet resistance heating element or ionographic printing head), p.^-Omitting layer 32 (Fig. 3), p⁺Layer 30 can be limited to the area in the immediate vicinity of the deep groove joint surface. As shown in Fig. 8, p⁺The layer 60 is formed by diffusing through a mask that exposes only the region of the deep groove 62 near the junction surface. Therefore, referring to Fig. 3 for comparison, p^-Layer 32 is omitted, p⁺Layer 60 is limited to the illustrated region near the joint surface of the deep groove. With reference to FIGS. 9-11, as yet another feature of the present invention, a 2 micron SiO is placed on the upper surface of the wafer before processing the wafer 14'.₂The mask 70 is deposited. Next, reactive ion etching is performed along lines 16 and 18 (Fig. 2) to form a deep groove 72 having a width of 3 microns and a depth of 10 microns. Next, SiO₂The mask 70 is removed to reoxidize the wafer 14'. If a deep groove 72 of 3 microns or less is formed, a 2 micron thermal oxide film covers the upper part of the deep groove, so that the next processing can be performed on the wafer surface without interfering with the deep groove (Fig. 10). it can. At the end of the wafer processing, SiO near the deep groove₂Is removed by perforated etching. That is, the resist layer 74 is applied again to form a pattern, and the final SiO₂SiO from deep groove by etching₂(Fig. 11). The purpose of perforated etching is to protect the network of integrated circuit chips and to provide deep groove SiO.₂Chip inactivating SiO during etching₂This is to provide the resist with a bare silicon substrate to avoid severe undercutting. FIG. 12 is a side view of the wafer after processing, in which the vertical deep groove 72 is shown. A groove hole 74'in which the center line is deviated from the center line of the deep groove is formed by a known dicing process. Next, the wafer 14'is separated by applying a bending force to each deep groove 72 as shown by the dotted line. Assuming that the separated chips 20 have passed the test, they are abutted (joined) with each other as shown in FIG. The joint surfaces 84a, 84b have flat vertical edges instead of the conventional sharp edges. Therefore, even if the two butted chips 20 are different, no lateral displacement occurs. 14 and 15 are still another embodiment. In FIG. 14, a groove hole 40 intersecting with the deep groove 72 is formed. By using the method of this example, it is possible to make accurate joint surfaces 84c and 84d without the damage caused by the folding method of the examples of FIGS. 12 and 13. The chipping and decoupling methods described above can be applied to any application where individual die pieces need to be abutted accurately and undamaged. For thermal ink jet printers for specific applications, the dual wafer wafers need to be separated into individual bondable chips. If the upper wafer (channel plate) is designed so that the deep groove die cut does not interfere with the disconnection of the San Germanchi after disconnecting the lower (resistive heating element) wafer, the above disconnection is done by the method described above. Can be carried out. Figures 16 and 17 show how the above separation is achieved. FIG. 16 shows an enlarged partial cross-sectional view having an upper wafer 90 and a lower wafer 92. A plurality of channel plates 94 are formed on the upper wafer 90, and a plurality of resistance heating element plates 96 are integrally formed on the lower wafer 92. Instead of joining each other in the separation area, the resistance heating element plate and the channel plate are firmly adhered with an adhesive, and then the front part and the rear part of the channel plate are joined in an area that can be easily cut with a dicing saw. Channel board 94 is made. The only remaining steps are the dicing cut 98 (Fig. 17) along the lower surface of the resistance heating element wafer to the reactive ion etching deep groove 100 to separate the San German chi die from the wafer. After cutting the chips using any of the methods described above, some known methods can be used to precisely join the chips, i.e. to line them up. For example, a vacuum robot operating under a closed-loop optical pattern recognition device can be used to align the chips 20 in a straight line.

[Simple explanation of drawings]

Fig. 1 is a side view of the <100> crystal axis wafer of the semiconductor crystal material, Fig. 2 is a plan view of the silicon wafer before separating the individual chips, and Fig. 3 is the first chip processing / separation process. FIG. 2 is a partially enlarged cross-sectional view of the wafer in FIG. 2, FIG. 4 is a sectional view of the wafer in FIG. 3 after the second processing step, and FIG. 5 is a cross-sectional view of the wafer after the chip is cut off. FIG. 3 is a cross-sectional view of the wafer, FIGS. 6 and 7 are contour views of a chip joint edge having a shape different from that of the chip edge of the embodiment of FIG. 5, and FIG. 8 is a second chip processing. -Partially enlarged cross-sectional view of the wafer in Fig. 2 showing the cutting method, and FIGS. 9 to 11 show the partially enlarged cross-sectional view of the wafer in Fig. 2 showing the third chipping / cutting method. FIG. 12 is a side view of the wafer after the processing / separating process shown in FIGS. 9 to 11, FIG. 13 is a diagram in which the chips separated from the wafer in FIG. 12 are joined, and FIG. 14 is a diagram in which the chips separated from the wafer are joined. , A cross-sectional view of another embodiment in which the chip is separated from the wafer in FIG. 2 by a dicing cut that encounters a deep groove due to reactive ion etching, FIG. 15 was made by the processing of FIG. The views in which the chips are joined, FIGS. 16 and 17, are side views and plan views of a two-layer wafer ink jet printing head manufactured by the etching process / separation method of the present invention, respectively. Explanation of symbols, 10 ...... wafers, 12, 14 ...... facing surfaces, 14'...... p-silicon layer (wafers), 16, 18 ...... Separation line, 20 ...... IC chip, 30 ...... p⁺Layer, 32 ...... p^-Layer, 34 ...... Vertical Deep Groove, 36 ...... Field Oxidized Layer, 38 ...... Polysilicon Plug, 40, 42 ...... Si₃N₄Membrane, 44 ... oxide layer, 50,52 ... flat joint surface, 50a, 50b ... joint edge, 52a, 52b ... joint edge, 60 ...... p⁺Layer (wafer), 62 ...... deep groove, 70 ...... SiO₂Mask, 72 ...... Deep groove, 74 ...... Resist layer, 74'...... Groove hole, 84a, 84b, 84c, 84d ...... Joint surface, 90. ..... Upper wafer, 92 ...... Lower wafer, 94 ...... Channel plate, 96 ...... Heat-generating resistor plate, 98 ...... Dice cut , 100 ...... Ion Etching Deep Groove.