Thin-film transistor

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to, for example, a thin film transistor suitable as a semiconductor switch element of an active matrix type liquid crystal display device.

【0002】

[Conventional technology]

In recent years, a large-capacity, high-density active matrix type liquid crystal display device suitable for television displays and graphic displays has been actively developed and put into practical use.

【0003】

In such a liquid crystal display device, a semiconductor switch element is used as a means for driving and controlling each pixel so that a high-contrast display without crost can be performed. This as the semiconductor switch device, is capable of transmissive display reasons equal large area is easy, thin film transistor formed on a transparent insulating substrate is generally used. Among them, a thin film transistor using an amorphous silicon is the most common because it can be formed on a large-area substrate and a low-temperature process is possible.

【0004】

The structure of a thin film transistor is roughly classified into a coplanar type and a staggered type according to the relative positional relationship between a gate electrode, a semiconductor thin film, a source electrode, and a drain electrode. In the case of an amorphous silicon thin film transistor formed on an insulating substrate, the latter, which has many significant aspects in the manufacturing process, is often used. Among them, the inverted staggered type having a structure in which a gate electrode, a gate insulating film, an amorphous silicon thin film, a low resistance semiconductor thin film, a source electrode, and a drain electrode are formed in this order on an insulating substrate is common. is there.

【0005】

This inverted staggered amorphous silicon thin film transistor is conventionally configured as shown in FIG. 7, in which reference numeral 1 is an insulating substrate, 2 is a gate electrode, 3 is a gate insulating film, and 5 Is an amorphous silicon thin film, 6 is an inorganic protective film, 7 is a low resistance semiconductor thin film, 8 is a channel region, 9 is a source region, 10 is a drain region, 11 is a source electrode, and 12 is a drain electrode. ..

【0006】

In this way, an inorganic protective film 6 made of, for example, silicon nitride is formed between the amorphous silicon thin film 5 and the low resistance semiconductor thin film 7, and the low resistance semiconductor thin film 7 is processed by processing this into a predetermined shape. It has a structure that enhances the sex. The manufacturing process of the conventional thin film transistor shown in FIG. 7 is shown in FIGS. 8 (a) to 8 (e).

【0007】

In general, as an active matrix type liquid crystal display device, two substrates each of which has been subjected to orientation processing by rubbing are arranged so as to face each other in parallel so that the orientation direction is 90 degrees, and nematic between them. A twisted nematic (TN) type having a type of liquid crystal composition is widely used.

【0008】

[Problems to be Solved by the Invention]

By the way, as shown in FIG. 8 (b), the amorphous silicon thin film transistor has a structure in which the source / drain electrode 28 is formed on the low resistance semiconductor thin film 7, so that the source / drain electrode 28 is Exists on the same layer. Therefore, in the source / drain electrode 28, both electrodes are formed at the same time by using photolithography technology. Further, as for the processing of the channel region for removing the unnecessary low resistance semiconductor thin film 7 between the source / drain electrodes 28, a method of using the shape-processed source / drain electrode 28 as a mask is mainly used. This is very efficient in terms of the process of forming the thin film transistor, and is a typical method that enables the production of a stable thin film transistor in a small number of steps.

【0009】

However, in the thin film transistor obtained by the above structure and manufacturing process, the channel length is generally defined by the photomask dimension (L in FIG. 8), which defines the outer diameter dimension of the inorganic protective film 6, and the source / drain electrode 28. Photolithography-The accuracy is limited because it depends largely on the processing accuracy. On the other hand, when considering the thin film transistor in terms of operating characteristics, this channel length is relative to the characteristic parameters during operation, that is, on-current (Ion), off-current (Ioff), and carrier mobility (μ). It is necessary to shorten the channel length in order to realize a thin film transistor with high characteristics.

【0010】

That is, in the conventional thin film transistor, the accuracy of the photomask itself and the photolithography-processing accuracy are limited, so that the lengthening of the short channel is also limited. There was a limit. Reference numeral 29 in FIG. 8 is a resist layer, and L is a channel length.

【0011】

FIG. 9 is a characteristic curve diagram showing the results of measuring the Ids-Vg characteristics of the conventional thin film transistor. The measurement was performed in the dark with Vds = 15V, and the transistor size was 100 μm in channel width and 10 μm in design channel length defined by the inorganic protective film 6. From this result, in the conventional thin film transistor, the value of Ion at Vg = 15V is 10.^-6It can be seen that about A is obtained.

【0012】

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin film transistor using amorphous silicon by shortening and controlling a substantial channel length and having excellent operating characteristics.

【0013】

[Means for solving problems]

In the present invention, a gate electrode, a gate insulating film, an amorphous silicon thin film, a first low resistance semiconductor thin film, a source electrode, and a drain electrode are sequentially formed on an insulating substrate, and the gate is formed. In a thin film transistor using an amorphous silicon that exhibits a switching action between the source electrode and the drain electrode due to the field effect of the voltage applied to the electrode. [0014]

A thin film transistor in which at least a second low-resistance semiconductor thin film or a metal thin film, or an intermediate layer obtained by laminating these two types of thin films is provided between the gate insulating film and the amorphous silicon thin film. ..

【0015】

[Action]

According to the present invention, the outer diameter of the low resistance semiconductor thin film can be easily and sufficiently controlled by photolithography processing using a conventional photomask or a self-alignment method using a gate electrode as a mask. Then, the film thickness of the amorphous silicon thin film sandwiched between the intermediate layer and the first low resistance semiconductor thin film is controlled, and further, the outer diameters of the source electrode and the drain electrode and the dimensions of the channel region are controlled. As a result, a thin film transistor having a substantially short channel length can be easily obtained without using a special method.

【0016】

[Example]

Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings. (First Example) [0017]

FIG. 1 shows a first embodiment of a thin film transistor according to the present invention, which will be described according to a manufacturing process. The same parts as those in the conventional example (Fig. 7) are designated by the same reference numerals.

【0018】

First, the gate electrode 2 is formed on the insulating substrate 1, and then the gate insulating film 3 is formed so as to cover the gate electrode 2. In this case, a nitriding silicon film is formed on the gate electrode 2 by a CVD method such as plasma, normal pressure, or reduced pressure using monosilane as a raw material to obtain a gate insulating film 3.

【0019】

Next, a low-resistance semiconductor thin film 4 having a film thickness of, for example, 500 angstroms is formed on a part of the gate insulating film 3 as an intermediate layer, which is a feature of the present invention, and a photomask or a gate electrode 2 is formed. It is processed into a desired shape by photolithography-processing using a self-alignment method using a mask. After that, an amorphous silicon thin film 5 having a film thickness of 5000 angstrom was formed so as to cover the low resistance semiconductor thin film 4, and an inorganic protective film 6 having a film thickness of 2000 angstrom was formed on the amorphous silicon thin film 5. Form.

【0020】

Next, after processing the inorganic protective film 6 into a predetermined shape, a low resistance semiconductor thin film 7 having a film thickness of, for example, 500 angstroms is formed so as to cover the inorganic protective film 6 and the amorphous silicon thin film 5. .. Then, the low resistance semiconductor thin film 7 and the amorphous silicon thin film 5 are processed to form a channel region 8, a source region 9, and a drain region 10. Further, when the source electrode 11 and the drain electrode 12 are formed so as to cover a part of the low resistance semiconductor thin film 7 and the gate insulating film 3, the thin film transistor is completed.

【0021】

Regarding the thin film transistor of the first embodiment, FIG. 2 shows the path through which the carrier electrons move through the amorphous silicon thin film 5, and the schematic channel region 8 is shown. It is an enlarged sectional view. FIG. 2A shows the case of the conventional example, and FIG. 2B shows the case of the first embodiment of the present invention. (1) to (6) in Fig. 2 show the movement path of electrons. Further, FIG. 3 shows an equivalent circuit of a thin film transistor. FIG. 3A shows the case of the conventional example, and FIG. 3B shows the case of the first embodiment of the present invention. In FIG. 3, S is a source electrode, D is a drain electrode, G is a gate electrode, R is a resistor, and TFT1,2,3 are TFTs in the thin film transistor section.

【0022】

In FIG. 2A, for example, the electrons injected into the amorphous silicon thin film 5 from the source electrode 11 are gated in the amorphous silicon thin film 5 due to the voltage applied to the gate electrode 2. It moves in the n-type channel generated in the vicinity of the insulating film 3 and reaches the drain electrode 12. This can be represented by the equivalent circuit shown in Fig. 3 (a), and the thin film transistor section is represented by TFT1.

【0023】

Now, taking the conventional thin film transistor as shown in Fig. 7 and Fig. 2 (a) as an example, when considering the movement path of the carrier electrons, it is possible to focus on the movement direction of the carrier electrons, and there are three paths (1). ), (2), (3). Paths (1) and (3) are paths for electrons to move from the source electrode 11 and the drain electrode 12 to the channel region 8, and the film thickness direction component d of the amorphous silicon thin film 5 is mainly the path. The length is decided. Further, since the path (2) is a path through which electrons move in the channel region 8 generated in the amorphous silicon thin film 5, this length is Lc, which corresponds to the actual channel length of the thin film transistor.

【0024】

By the way, the thin film transistor of the first embodiment shown in FIGS. 1 and 2 (b) shortens the actual channel length by providing a region having a higher conductivity than the channel conductivity in the channel (the actual channel length is shortened). Route (5)). This means that there is a resistor R in the movement path of the electrons connected in series to the extent that it does not hinder the movement of the electrons, so the equivalent circuit is also as shown in FIG. 3 (b). At this time, there are two thin film transistors that pose a problem in operation, TFT2 and TFT3, which are composed of amorphous silicon thin films 5 located at both ends of the low resistance semiconductor thin film 7, and the actual channel length is also the path (4). , (6) is the sum of the lengths 2Lc , that is, the sum of the values defined centering on the difference in the channel direction dimensions of the low resistance semiconductor thin film 4 and the inorganic protective film 6.

【0025】

Based on the above theory, for this invention and conventional examples, the actual channel length for a thin film transistor with a design channel length of 10 μm is calculated as shown in Table 1 below.

【0026】

[table 1]

<img file="JPH05190857A_D0001.tif" />【0027】

At this time, if the self-alignment process is used to form the low-resistance semiconductor thin film 4 and Lc'is controlled by defining W shown in FIG. 2 (b), the exposure technology can achieve 3 μm or less. Therefore, it can be said that 2Lc = 0 to 6 μm is possible as the channel length.

【0028】

Now, the structure of the present invention which has been subjected to the shortening of the channel as described above, that is, the low resistance semiconductor thin film 4 is formed between the gate insulating film 3 and the amorphous silicon thin film 5, and the outer diameter dimension thereof is determined. When the Ion is calculated for the thin film transistor obtained by controlling the thickness of the amorphous silicon thin film 5 (5000 angstroms in this example) at the same time as controlling, the Ion value shown in FIG. 9 is used to obtain the low resistance semiconductor thin film. Conductivity of 4 to 10²(Ωcm)^-1By assuming that 10^-5A value of A or higher can be obtained. As described above, in the conventional thin film transistor, the value of Ion at Vg = 15V is 10.^-6About A is obtained. In the first embodiment, the low resistance semiconductor thin film 4 is formed as the intermediate layer, but a metal thin film may be formed as the intermediate layer. (Second Example) [0029]

FIG. 4 shows a second embodiment of the present invention, in which a metal thin film 4b made of, for example, Mo is formed between the gate insulating film 3 and the amorphous silicon thin film 5 from the gate insulating film 3 side. This is a case where an intermediate layer formed by laminating the low resistance semiconductor thin film 4a is provided.

【0030】

In order to manufacture this thin film transistor, in the thin film transistor manufacturing process shown in the first embodiment, a metal thin film 4b forming and shape processing step is added before the low resistance semiconductor thin film 4a is formed. Further, at this time, when processing the shape of the metal thin film 4b, the self-alignment method using the gate electrode 2 as a mask cannot be used. Also in the thin film transistor shown in the second embodiment, the substantial channel length can be calculated by the same method as in the first embodiment, and a very short channel length can be realized.

【0031】

FIG. 5 is an active element substrate using the thin film transistor of the present invention, and shows the arrangement state of the thin film transistor. In the figure, the thin film transistor 13 existing for each pixel is a gate electrode 2 integrated with the row selection line 14, a drain electrode 12 integrated with the column selection line 15, and a source electrode connected to the pixel electrode 16. It is composed of 11 and an active element region 17 surrounded by a dotted line.

【0032】

Here, the row selection line 14 is, for example, an address line for giving a scanning signal to the gate electrode 2 of the thin film transistor 13, whereas the column selection line 15 is, for example, for giving a pixel signal to the drain electrode 12 of the thin film transistor 13. Data line. As a whole, one pixel is formed by each of a plurality of thin film transistors 13 and a pixel electrode 16 connected to the thin film transistors 13, and a row selection line 14 and a column selection line 15 are formed around the thin film transistors 13 on the matrix. It is formed. FIG. 6 is a schematic cross-sectional view of one pixel portion of the active matrix liquid crystal display device using the above active element substrate.

【0033】

To explain the manufacturing method, for example, a row selection line 14 and a pair of gate electrodes 2 are formed on one main surface of a substrate 18 made of glass, and then plasma is formed as a gate insulating film 3 so as to cover the row selection lines 14. A nitrous film is formed on the gate electrode 2 with a film thickness of 4000 angstrom using monosilane as a raw material by a CVD method such as normal pressure and reduced pressure. Next, for example, a low-resistance semiconductor thin film 4 of 500 angstrom is formed, processed into a desired shape by photolithography using a photomask or a self-alignment method using a gate electrode 2 as a mask, and then processed into a desired shape. Amorphous silicon thin film 5 with a film thickness of 5000 angstrom and an inorganic protective film 6 with a film thickness of 2000 angstrom are formed.

【0034】

Next, after processing the inorganic protective film 6 into a predetermined shape, for example, a low resistance semiconductor thin film 7 of 500 angstrom is formed, and the low resistance semiconductor thin film 7 and the amorphous silicon thin film 5 are processed to form a channel. A region 8, a source region 9, and a drain region 10 are formed. Then, the pixel electrode 16 is formed of the transparent conductive film, and the drain electrode 12 and the source electrode 11 integrated with the column selection line 15 are further formed. From the above, the active element substrate 19 is completed.

【0035】

On the other hand, for example, the opposed substrate 22 is formed by forming a common electrode 21 made of a transparent conductive film on one main surface of the substrate 20 made of glass. Then, on one main surface on which the thin film transistor 13 and the like of the active element substrate 19 are formed, an alignment film 23 made of, for example, a low temperature cure type polyimide (PI) is further formed on the entire surface. Further, on the one main surface on which the common electrode 21 of the opposing substrate 22 is formed, an alignment film 24 made of, for example, a low temperature cure type polyimide (PI) is also formed on the entire surface.

【0036】

Then, by rubbing the alignment films 23 and 24 on one main surface of the active element substrate 19 and the opposing substrate 22 with a cloth in predetermined directions, respectively, the alignment treatment by rubbing is performed. Further, the active element substrate 19 and the opposing substrate 22 are arranged so that one main surface side of each other faces each other and their orientation axes are approximately 90 degrees, and the liquid crystal 25 is held in these gaps.

【0037】

Here, when the active element substrate 19 and the opposing substrate 22 are combined, the rubbing directions of the alignment films 23 and 24 are set so that the good viewing angle direction faces the front direction. Polarizing plates 26 and 27 are adhered to the other main surfaces of the active element substrate 19 and the opposing substrate 22, respectively, and irradiation is performed from the other main surface side of either the active element substrate 19 or the opposing substrate 22. It is in the form of doing.

【0038】

In any of the inventions, the configuration of the thin film transistor 13 including the shape and structure of the low resistance semiconductor thin film, the metal thin film, or the intermediate layer formed by laminating these two types of thin films is not limited to those described so far. Needless to say, even if various modifications are made within the range that satisfies the constituent requirements of the present invention, they are included in the present invention. The technique of the present invention can be applied not only to the production of active matrix liquid crystal display devices but also to the manufacture of various sensors.

【0039】

[Effect of the invention]

As described in detail above, according to the present invention, at least an intermediate layer in which a low-resistance semiconductor thin film or a metal thin film, or these two types of thin films are laminated and formed between a gate insulating film and an amorphous silicon thin film. Therefore, the outer diameter of the low-resistance semiconductor thin film can be easily and sufficiently controlled by photolithography processing using a conventional photomask or a self-alignment method using a gate electrode as a mask. Then, by controlling the film thickness of the amorphous silicon thin film sandwiched between the intermediate layer and the low resistance semiconductor thin film, and further by controlling the outer diameters of the source electrode and the drain electrode and the dimensions of the channel region. A thin film transistor having a substantially short channel length can be easily formed without using a special method, and high operating characteristics can be obtained.

[Simple explanation of drawings]

[Figure 1]

The cross-sectional view which shows the thin film transistor which concerns on 1st Example of this invention.

[Figure 2]

(a) and (b) are enlarged cross-sectional views of a schematic channel region shown for explaining the transfer path of carrier electrons for the conventional thin film transistor and the thin film transistor of the present invention, respectively.

[Fig. 3]

(a) and (b) are equivalent circuit diagrams of the conventional thin film transistor and the thin film transistor of the present invention, respectively.

[Fig. 4]

The cross-sectional view which shows the thin film transistor which concerns on 2nd Example of this invention.

[Fig. 5]

The plan view which shows the active element substrate using the thin film transistor of this invention.

[Fig. 6]

FIG. 5 is a schematic cross-sectional view of one pixel of an active matrix liquid crystal display device using the active element substrate of FIG.

[Fig. 7]

Sectional drawing which shows the conventional thin film transistor.

[Fig. 8]

The cross-sectional view which shows the manufacturing process of the conventional thin film transistor.

[Fig. 9]

A characteristic curve diagram showing the results of measuring the Ids-Vg characteristics of a conventional thin film transistor.

[Explanation of symbols]

1 ... Insulated substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4,7 ... Low resistance semiconductor thin film, 5 ... Amorphous silicon thin film, 6. Inorganic protective film, 8 ... channel region, 9 ... source region, 10 ... drain region, 11 ... source electrode, 12 ... drain electrode.