Semiconductor device and manufacture thereof

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to the structure of a TFT transistor among semiconductor devices.

【0002】

[Conventional technology]

Currently, one of the features of SRAM widely used in the field of memory is low standby current that enables battery backup. In conventional SRAM, the standby current has been kept low by using a high resistance load type cell and increasing the resistance value of polysilicon that is the load. However, if 4MSRAM requires the same standby current as 1MSRAM, the standby current per cell must be reduced to 1/4, but the supply current in that case is about the same as the cell node leak current. Since it becomes or less than that, it becomes difficult to retain the information, and the data retention characteristics deteriorate.

【0003】

Therefore, a cell called a pMOS load type cell has appeared as a cell that has a low standby current and sufficient data retention characteristics even if it is highly integrated. This is a load of pMOS transistors stacked on top of an nMOS transistor, and has the advantage of being more highly integrated than the complete cMOS type.

【0004】

This pMOS transistor has a TFT (Thin Film Transistor) structure in which the source / drain channel portion is formed of a thin film silicon layer. Further, in SRAM, a structure called a lower gate structure in which a gate electrode is located below is widely used due to restrictions on memory cell design and the like.

【0005】

The manufacturing method of the TFT transistor having this lower gate structure will be described with reference to FIG. First, a silicon oxide film 202 is formed on the semiconductor substrate 201 by the CVD method or the like (Fig. 2 (a)), a polysilicon film is formed by the CVD method, impurities are introduced, and then the gate electrode is etched by using a positive resist by photolithography. Form 203. (Fig. 2 (b)) Next, after forming the gate oxide film 204 by the CVD method or the oxidation method, the polysilicon film 205 is formed by the CVD method or the like (Fig. 2 (c)), and impurities are ion-implanted using the resist as a mask. To form the source / drain portion 206. (Fig. 2 (d)) At this time, 207 not doped with impurities becomes a channel portion. Finally, after forming the silicon oxide film 208 on the entire surface, the contacts are opened by wet etching with hydrofluoric acid or hydrofluoric acid and ammonium fluoride to form the aluminum wiring 209. (Fig. 2 (e)) [0006]

[Problems to be Solved by the Invention]

By the way, when this TFT is used as a memory cell of SRAM, first, there is a reduction of off-current as a characteristic required for the TFT. This has a direct effect on the standby current of SRAM mentioned earlier. As one method of reducing this off-current, it is very effective to reduce the film thickness of the channel portion of the TFT.

【0007】

On the other hand, when the bulk portion (source drain channel portion) of this TFT is used as wiring, the required characteristic is reduction of sheet resistance. The resistance of this wiring part affects the speed of the circuit. In order to secure the sheet resistance that can be used as wiring, there is a method of increasing the impurity concentration, but a certain film thickness is also required. In addition, if the source / drain portion is thin, the contact holes cannot be directly dry-etched when connecting the wiring layers, so it is said that the contacts are connected by the lower layer wiring or wet-etched as described in FIG. I was taking steps.

【0008】

As described above, it is ideal that the channel portion is thin in the TFT and the source / drain portion of the TFT is thick, but in the prior art, the source / drain channel portion is formed at the same time, so the film thickness is formed. Will be the same.

【0009】

Further, in the prior art, the distance to the source / drain portion of the TFT and the offset length have conventionally varied depending on the photo accuracy and the alignment accuracy, and as a result, the TFT characteristics have also varied.

【0010】

Therefore, the present invention solves these problems, and an object of the present invention is to supply a lower gate structure TFT transistor capable of forming a thin TFT channel portion and a thick TFT source / drain portion.

【0011】

Moreover, the source / drain portion and the offset can be formed in a self-aligned manner with respect to the gate electrode, and a lower gate structure TFT transistor with little variation is supplied.

【0012】

[Means for solving problems]

The semiconductor device of the present invention is characterized in that, in a TFT transistor having a lower gate structure, the film thickness of the channel portion is thin and the film thickness of the source / drain portion is thick.

【0013】

The method for manufacturing a semiconductor device of the present invention is a step of forming a first insulating film on a semiconductor substrate in a TFT transistor having a lower gate structure, forming a first semiconductor film on the first insulating film, and then performing desired patterning. Steps to be performed, a step of forming a second insulating film on the patterned first semiconductor film and then performing a desired patterning, a step of forming a first semiconductor film on the patterned first semiconductor film and the second insulating film, It is characterized by consisting of a process of performing heat treatment.

【0014】

Another feature is that a laser annealing process is performed in the heat treatment step.

【0015】

[Example]

Hereinafter, the present invention will be described in detail based on examples.

【0016】

FIG. 1 is a diagram showing examples of the present invention in order of steps.

【0017】

First, a silicon oxide film 102 is formed on the entire surface of the semiconductor substrate 101 by a CVD method or thermal oxidation at 100 to 1000 nm, and then a polysilicon film 103 is formed at 600 to 640 ° C in a monosilane atmosphere by an LPCVD method at 20 to 300 nm. Subsequently, BF, which is a P-type impurity, covers the entire surface of the polysilicon film.₂⁺Or B⁺, Or an N-type impurity P⁺Or As⁺Doze amount 1 × 10¹⁴~1×10¹⁶After introducing impurities by ion implantation or thermal diffusion method with energy of 30 to 120 kev, patterning is performed by photolithography and etching. (Fig. 1 (a)) Next, after forming a silicon oxide film 104 at 10 to 100 nm on the entire surface by thermal oxidation or CVD method, patterning is performed by photolithography and etching. (Fig. 1 (b)) Subsequently, a polysilicon film 103 is formed at 600 to 640 ° C at 20 to 300 nm in a monosilane atmosphere by the LPCVD method. (Fig. 1 (c)) After that, the polysilicon film 103 is subjected to thermal annealing (700 to 1000 ° C, 30 minutes to 1 hour), lamp annealing (900 to 1100 ° C, 10 seconds to 30 seconds), or laser annealing. The impurities are diffused to a part of the polysilicon film 105 to form the source / drain portion of the TFT. (Fig. 1 (d)) Further, a polysilicon oxide film 106 is formed, the contacts are opened by wet or dry etching, and then the aluminum wiring 107 is connected. (Fig. 1 (e)) According to the semiconductor device completed by the above process, the channel portion can be formed thinly. Due to the action of spreading the depletion layer over the entire polysilicon of the channel and increasing the mobility, etc. Transistor characteristics are improved.

【0018】

Also, since the source and drain parts can be formed thick, Since the sheet resistance of the source / drain section is reduced, a stable memory cell can be created in which the voltage does not decrease even if the TFT bulk layer is used as the wiring layer.

【0019】

Since the source / drain part is the upper wiring, it is not necessary to drop it to the lower layer once, and there is a margin in the pattern, which is effective for wiring.

【0020】

Since dry etching processing is also possible when a contact for upper wiring is opened in the source / drain portion, there is a margin in the rules around the contact.

【0021】

There is such an effect.

【0022】

In addition, by adjusting the patterning dimensions in Fig. 1 (a), Since the source / drain portion can be formed in a self-aligned manner with respect to the gate electrode, a transistor with small variation can be formed.

【0023】

alike, Since the offset length can be formed in a self-aligned manner with respect to the gate electrode, it is possible to form a transistor having a small variation and a small leakage current.

【0024】

As a result When TFT is used for SRAM, the standby current is small and the variation is small.

【0025】

Further, when the source / drain portion is formed by the diffusion of impurities between the polysilicon 103 and the polysilicon 105, the crystal defects in the silicon joint can be reduced by performing the laser annealing treatment. resulting in, It is possible to form a TFT with a small leakage current, that is, a small standby current when the SRAM is used.

【0026】

In addition, by adjusting the distance between the gate electrode and the source / drain during the pattern shown in Fig. 1 (a), The offset length on the source side and drain side can be adjusted separately.

【0027】

Further, in FIG. 1 (b), since the silicon oxide film to be the gate film can be formed by CVD, it can also be formed on a glass substrate, so that the range of application is expanded.

【0028】

Further, in this embodiment, impurities are not introduced into the TFT channel portion, but the same effect can be obtained by introducing P-type or N-type impurities.

【0029】

Further, in this embodiment, the polysilicon film was formed at 600 to 640 ° C in a monosilane atmosphere, but the same effect can be obtained by forming the polysilicon film at 450 to 600 ° C in a monosilane atmosphere. The same effect can be obtained even if it is formed at 400 to 600 ° C in a disilane atmosphere. Further, the same effect can be obtained by performing a heat treatment at 500 to 900 ° C.

【0030】

Further, as described above, the same effect can be obtained by forming the glass substrate.

【0031】

Further, when the patterning of the polysilicon film 103 is difficult with a normal photo in this embodiment, the same effect can be obtained by patterning with excimer laser exposure or EB exposure.

【0032】

[Effect of the invention]

According to the present invention, since the channel portion is thin and the source / drain portion is thick, the TFT characteristics are improved, the resistance of the source / drain portion is small, and the lower gate structure TFT that can be freely wired can be supplied.

【0033】

Further, since the source / drain portion and the offset can be formed in a self-aligned manner with respect to the gate electrode, it is possible to provide a lower gate structure TFT having less variation in characteristics.

[Simple explanation of drawings]

[Figure 1]

The process forward sectional view which shows one Example of the manufacturing method of the semiconductor device of this invention.

[Figure 2]

FIG. 6 is a process sequential sectional view showing an embodiment of a conventional semiconductor device manufacturing method.

[Explanation of symbols]

101, 201 Semiconductor substrate 102, 104, 106, 202, 204, 208 Silicon oxide film 103, 105, 203, 205 Polysilicon film 206 TFT source / drain 207 TFT channel section 107, 209 Aluminum wiring