Manufacture of semiconductor device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a vertical gate type field effect transistor (FET).

【0002】

In recent years, as the density of semiconductor devices has increased, TFTs (Thin Film Transistors) have been used as load FETs for SRAM cells. In this case, it is advantageous to apply the upper and lower gate type FETs to improve the cutoff characteristics of the TFT, but countermeasures are required because the number of processes increases.

【0003】

[Conventional technology]

The manufacturing process of the conventional upper and lower gate type FET is as follows. (1) A lower gate electrode is formed on an insulating film or an insulating substrate.

【0004】

A polysilicon film is grown as a lower gate electrode material, doped with impurities, heat-treated, and the polysilicon film is patterned and formed using ordinary lithography. (2) A lower gate oxide film is formed on the lower gate electrode. (3) A thin-film silicon (Si) film is grown by covering the lower gate oxide film, doped with impurities, heat-treated, and patterned. (4) A gate oxide film for the upper gate is formed on the thin film Si film. (5) Form a contact hole with the lower gate in the oxide film for the upper gate. (6) Form the lower gate electrode.

【0005】

A polysilicon film is grown as an upper gate electrode material, doped with impurities, heat-treated, and patterned. In the conventional example, the upper and lower gate oxide films and the upper and lower gate electrodes are formed separately on the upper and lower sides as described above.

【0006】

[Problems to be Solved by the Invention]

The upper and lower gate type FETs have better cutoff characteristics than the upper gate type FET or the upper gate type FET, but there is a problem that the number of manufacturing steps is large in the conventional manufacturing method.

【0007】

An object of the present invention is to reduce the number of manufacturing steps of an upper and lower gate type FET.

【0008】

[Means for solving problems]

The solution to the above problems is a step of coating the spacer film 2 on the substrate surface or the insulating film 1 formed on the substrate and patterning the spacer film in a strip shape having a width in the gate length L direction, and the spacer film. A step of covering 2 and coating the semiconductor film 3 on the substrate and patterning it in a strip shape having a gate width W in a direction perpendicular to the gate length, and an etching method capable of selectively etching the semiconductor film. The step of removing the spacer film 2 by the above step, the step of forming the gate insulating film 4 on the exposed portion of the semiconductor film 3, and the step of covering the gate insulating film 4 with the gate material film to reduce the width of the gate length L. A step of forming the upper and lower gate electrodes 5 by patterning in a strip shape, and using the gate electrode 5 as a mask to introduce an impurity opposite to the semiconductor film into the semiconductor film 3 to form a source / drain region 3A. It is achieved by the manufacturing method of the semiconductor device having.

【0009】

[Action]

In the present invention, silicon nitride (Si) is previously placed under the thin film Si film which is an element forming film.₃N₄) The film is patterned and formed, and after patterning the thin film Si film, a part of the back surface of the thin film Si film is exposed by removing the silicon nitride film, so that the gate oxide film is formed on both the upper and lower surfaces of the thin film Si film. And the gate electrode are formed at the same time.

【0010】

[Example]

1A to 1D are cross-sectional views illustrating an embodiment of the present invention. The left side of each figure is a cross-sectional view in the gate length L direction, and the right side is a cross-sectional view in the direction perpendicular to the gate length (gate width direction W).

【0011】

In Fig. 1 (A), an insulating film formed on the substrate [silicon dioxide (SiO) with a thickness of 1000 Å).₂) Membrane] Silicon nitride (Si) with a thickness of 1000 Å as a spacer film 2 on 1₃N₄) The film is grown and patterned by the width of the gate length + source region + drain region.

【0012】

In FIG. 1 (B), a thin film Si film 3 having a thickness of 500 Å is adhered on the substrate so as to cover the spacer film 2 and patterned according to the gate width W. The thin film Si film is formed by, for example, vapor deposition (CVD) of a polysilicon film or an amorphous silicon film and recrystallization by laser irradiation.

【0013】

In Fig. 1 (C), the spacer film 2 is removed by isotropic dry etching or wet etching of thermal phosphoric acid. Then, by thermal oxidation or CVD method, SiO is applied to the exposed part of the thin film Si film as a gate oxide film 4.₂Form a film.

【0014】

In Fig. 1 (D), a polysilicon film with a thickness of 1000 Å is grown by the CVD method and patterned with the width of the gate length to form the upper and lower gate electrodes 5. After that, the gate electrode is used as a mask and impurities opposite to the thin film Si film are introduced into the thin film Si film to form the source / drain region 3A.

【0015】

In the examples, the gate length L is smaller than the width of the spacer film 2, but it is clear that FETs can be formed even if they are the same or larger.

【0016】

[Effect of the invention]

According to the present invention, the upper and lower gate oxide films and the upper and lower gate electrodes of the upper and lower gate type FET can be formed at the same time, and the number of manufacturing steps can be reduced.

[Simple explanation of drawings]

[Figure 1]

Sectional drawing explaining embodiment of this invention [Explanation of symbols]

1 Substrate or insulating film 2 Spacer film 3 Thin film Si film with semiconductor film 3A source / drain area 4 SiO with gate insulating film₂film 5 Polysilicon film with gate electrode