Mos device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a MOS type semiconductor device to which an interband tunneling phenomenon is applied.

【0002】

[Conventional technology]

Conventionally, in a MOS type semiconductor device, for example, a MOS type field effect transistor, there is a problem that if the scale of the element is reduced, the reliability of the element characteristics is lowered due to the hot carrier effect, the short channel effect, and the like. , LDD structure etc. was devised as a countermeasure for this problem. However, as long as the operating mechanism of the MOS field-effect transistor, that is, the operating mechanism of controlling the carrier in the channel region under the gate by the voltage applied to the gate, is used, the element characteristics are affected by the hot carrier effect and the short channel effect described above. There was a problem that a decrease in reliability was unavoidable. Further, as the gate length is reduced, there is a problem that it becomes difficult to create a complicated structure such as an LDD structure.

【0003】

Therefore, as a solution to these problems, A BAND TO BAND TUNNELING MOS DEVICE (B) by Eiji Takeda et al. Described in IEDM 88, pp402 ~ 405.²T-MOSFET) has been devised. A similar semiconductor device is also described in EUROPEAN PATENT 0399261.

【0004】

In this MOS field effect transistor (MOSFET), as shown in FIG. 10, the drain 2 is formed by the same conductive type (P type) high-concentration impurity diffusion layer as the substrate 1, and the source 3 is a conductive type different from the substrate 1. It was formed by a (N-type) high-concentration impurity diffusion layer, and the gate 4 was formed so that a part of the gate 4 overlapped with the gate oxide film 5.

【0005】

The operating mechanism of this MOSFET is, for example, when a P-type is used for the substrate 1, when a positive voltage Vg is applied to the gate 4 and a negative voltage Vd is applied to the drain 2, the drain region surface layer of the overlapping portion of the gate 4 and the drain 2 ( In the shaded area) 6, an electron-hole pair is generated by band-to-band tunneling, the hole moves to the drain 2, and the electron moves to the source terminal 3 to which a positive voltage is applied. Current flowing between this source and drain I_SD Is caused by electrons generated by interband tunneling, so it can be controlled by the potential difference between the gate and drain.

【0006】

The advantage of the operating mechanism of the MOS field-effect transistor is that there is almost no decrease in reliability due to the short-channel effect or hot carrier effect. From this, it is considered that the mechanism applying the inter-band tunneling phenomenon is suitable for miniaturization.

【0007】

[Problems to be Solved by the Invention]

However, the conventional MOS field effect transistor shown in FIG. 10 is configured as described above, and when the gate width is 100 μm, the current I flowing between the source and drain_SDThe size of is 10^-8It is about amperes, and this current I_SDThere was a problem that it was difficult to drive other devices.

【0008】

The present invention has been made to solve the above-mentioned problems, and is a MOS type semiconductor device capable of increasing the current flowing between the source and the drain and driving other devices by the current flowing between the source and the drain. The purpose is to provide.

【0009】

[Means for solving problems]

The present invention has been made in view of the above circumstances, and the MOS type semiconductor device according to the present invention includes a first conductive type semiconductor substrate, a drain region composed of a second conductive type high-concentration impurity diffusion layer, and a drain region. A source region composed of a first conductive type high concentration impurity diffusion layer, a second conductive type high concentration impurity diffusion layer region formed on a part of the source region on the substrate surface side, and a second conductive type high concentration impurity diffusion layer. It is characterized by including a concentration impurity diffusion layer region and a gate in which a part thereof overlaps with each other via a gate insulating film.

【0010】

[Action]

Based on the above configuration, in the MOS type semiconductor device according to the present invention, the second conductive type high concentration impurity diffusion layer region is provided in the region where the gate and the source region composed of the first conductive type high concentration impurity diffusion layer overlap. By providing the PN junction, the high-concentration impurity diffusion layer region and a part of the source region form a PN junction, and this PN junction increases the band bending, increases the probability of band-to-band tunneling, and flows between the source and drain. Increase the current.

【0011】

[Example]

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

【0012】

FIG. 1 is a cross-sectional view showing a MOS type semiconductor device according to an embodiment of the present invention, for example, a MOSFET.

【0013】

The MOSFET has a P-type silicon substrate 1, on which P-type impurities are diffused to form source regions 2a and 2b, and N-type impurities are diffused. The drain region 3 is formed. A surface diffusion layer 7 as an N-type high-concentration impurity diffusion layer region is formed on a part of the source regions 2a and 2b on the substrate surface side, and a gate insulating film is formed on the surface diffusion layer 7. A gate 4 is formed in which a part of the gate oxide film 5 overlaps the gate oxide film 5. Further, the surfaces of the source region 2a and the drain region 3 are covered with the protective oxide film 8, and field insulating films 9 are formed on both ends of the protective oxide film 8. The shaded area 6 is an area where the inter-band tunneling phenomenon occurs.

【0014】

Here, the formulation of the generation ratio of the interband tunnel electrons will be described.

【0015】

FIG. 2 is a schematic representation of the space charge density distribution (ρ (z)) near the substrate surface when used for the P-type substrate 1. The z-axis is in the depth direction, z = 0 is the surface, that is, the interface between the substrate and the gate oxide surface, z = a is the position of the PN junction, and the region of 0 <z <a is the N-type diffusion of the surface. The layer region (N-type impurity concentration Nn), the region a <z is the P-type diffusion layer region (P-type impurity concentration Np), and b is the voltage V between the gate and the substrate._GSIs the depth of the depleted region due to the application of. Then, the electric field potential is E (z), the electrostatic potential is V (z), and the dielectric constant of silicon is ε._Si, Silicon oxide film ε_OXThen, the depth b of this depletion region can be obtained by self-consistently solving the following four equations.

【0016】

E (z) = (1 / ε_Si) ρ (z) dz ... (1) V (z) =-E (z) dz ... (2) V_OX= (ε_Si/ ε_OX) T_OXE (0) ... (3) V (0) + V_OX= V_GS ...(Four) However, the integration range is from b to z.

【0017】

Furthermore, from these equations, the impurity concentration and oxide film thickness in each of the P-type and N-type regions, and the voltage V between the gate and the substrate_GSThe bending of the energy band when is given (-eV (z); e is an elementary charge) can also be obtained. However, here, E (b) = V (b) = 0 is set as a boundary condition so as not to lose generality. Then, if the solutions of these equations are obtained, the generation ratio of tunnel electrons is calculated as follows.

【0018】

The tunnel probability for a triangular potential barrier is as follows according to the calculation based on the WKB approximation.

【0019】

T (z) = AEa (z)²exp (-8π (2m)^*E_G³)^1/2/ 3ehEa (z)) ... (5) However, A is a constant of proportionality, m^*Is the effective mass of the electron, E_GIs the silicon forbidden bandgap and h is the Planck's constant.

【0020】

For Ea (z), the average value of the electric fields at the start point (z) and the end point (u) of the interband tunneling, that is, Ea (z) = (E (z) + E (u)) / 2 is used. However, the coordinates u of the end point with respect to the start point z can be obtained from the above band bending, that is, the electrostatic potential by the following equation.

【0021】

V (u)-V (z) = E_G ... (6) From the above, the generation ratio J of tunnel electrons can be calculated by the following equation.

【0022】

J = -eN_V T (z) dz ... (7) The integration range is from c to b, and N_VIs the effective electron density of the valence band at the starting point, and c represents the lower limit of the tunneling region, which can be obtained as a solution of the following equation.

【0023】

V (0)-V (c) = E_G ... (8) By using the above formula, the optimum conditions for maximizing the determined gate voltage, impurity distribution and PN junction depth within the controllable range, and the ratio of tunnel electron generation to the gate oxide film thickness are estimated. be able to.

【0024】

FIG. 3 is a diagram showing an example of the calculation result, and shows the dependence of the tunnel electron generation ratio J on the bonding depth a. However, V_GS12V, Nn 1.0E + 19 / cm³, Np 2.0E + 19 / cm³, T_OXWas set to 10 nm. Note that a = 0 corresponds to the case where a PN junction is not provided. Then, it is found that the optimum value of the junction depth a is about 6 nm, and the generation ratio of tunnel electrons at that time is about 20 times that in the case where the PN junction is not provided. From this, it can be seen that providing a PN junction in the interband tunneling region is effective for increasing the generation rate of tunnel current.

【0025】

Next, the manufacturing process of the MOSFET of this embodiment will be described.

【0026】

First, as shown in FIG. 4, SiO is formed on the silicon substrate 1 excluding the transistor element molding region by a selective oxidation method such as LOCOS.₂A field insulating film 9 made of the material is formed, and a sacrificial oxide film 10 is further formed by thermal oxidation treatment.

【0027】

The photoresist 11 is then applied to a predetermined pattern, the region causing the interband tunneling phenomenon is patterned as shown in FIG. 5, and the impurity concentration and PN junction depth determined using the above equation (eg,). Nn = 1.0E + 18 / cm³, Np = 2.0E + 19 / cm³, A = 6 nm), the impurity diffusion layer 7 and the source region 2b are formed by an ion implantation method, a gas phase diffusion method, or the like.

【0028】

Further, as shown in FIG. 6, a photoresist 12 is used to form a high-concentration impurity diffusion layer in the drain region 3 by an ion implantation method and thermal diffusion.

【0029】

Then, as shown in FIG. 7, the photoresist 13 is used to form the source region 2a by ion implantation and thermal diffusion.

【0030】

Then, as shown in FIG. 8, etching using the photoresist 14 as a mask is performed to pattern the gate 4.

【0031】

Then, as shown in FIG. 9, the protective oxide film 8 is formed by thermal oxidation and position, and contact holes corresponding to the source region 2a and the drain region 3 are formed in the protective oxide film 8 by etching, respectively. Electrodes are formed to form MOSFETs.

【0032】

In the above-described embodiment, the P-type substrate 1 has been used as the first conductive type semiconductor substrate, but the present invention is not limited to this, and some or all of the impurity types are reversed. It may be a mold.

【0033】

[Effect of the invention]

As described above, according to the present invention, a PN junction is provided in the region where the gate and the source overlap, and the band bending can be increased by this PN junction to increase the probability of tunneling between bands. The current gain can be increased, which allows other devices to be driven by the current flowing between the source and drain.

[Simple explanation of drawings]

[Figure 1]

It is sectional drawing which shows the MOS type semiconductor device by one Example of this invention.

[Figure 2]

It is a figure which shows the impurity distribution in the depth direction of the MOS type semiconductor device by one Example of this invention.

[Fig. 3]

It is a figure which shows the calculation result of the formula with respect to the generation ratio of the interband tunnel electron by one Example of this invention.

[Fig. 4]

It is a figure which shows the manufacturing process of the MOS type semiconductor device by one Example of this invention.

[Fig. 5]

It is a figure which shows the manufacturing process of the MOS type semiconductor device by one Example of this invention.

[Fig. 6]

It is a figure which shows the manufacturing process of the MOS type semiconductor device by one Example of this invention.

[Fig. 7]

It is a figure which shows the manufacturing process of the MOS type semiconductor device by one Example of this invention.

[Fig. 8]

It is a figure which shows the manufacturing process of the MOS type semiconductor device by one Example of this invention.

[Fig. 9]

It is a figure which shows the manufacturing process of the MOS type semiconductor device by one Example of this invention.

[Fig. 10]

It is sectional drawing which shows the conventional MOS type semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2a, 2b source area 3 drain area 4 gate 5 Gate oxide film 7 Surface diffusion layer