Manufacture of nonvolatile semiconductor storage device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a non-volatile semiconductor storage device, for example, a memory cell portion having two layers of electrodes of a floating gate and a control gate, and such a memory. The present invention relates to a method for manufacturing a non-volatile semiconductor storage device such as EPROM in which a peripheral transistor having one gate electrode layer for controlling a cell is formed on the same semiconductor substrate.

【0002】

[Conventional technology]

As the degree of integration of semiconductor storage devices has improved, miniaturization has progressed and the manufacturing process has become complicated. In the manufacture of non-volatile semiconductor storage devices, such as EPROMs, the manufacturing process has become complicated, increasingly sophisticated, and difficult due to the special structure of the MOS transistors manufactured therein. Unlike memory transistors used in ordinary static RAM (SRAM), EPROM has a two-layer structure consisting of a floating gate and a control gate, as will be described later.

【0003】

As a basic circuit of EPROM, for example, in Japanese Patent Publication No. 51-31073, a pair of Ps formed on the surface of an N-type silicon substrate.⁺A floating gate EPROM consisting of a floating gate electrode formed through a source / drain region of the shape and a gate insulating film having a thickness of 500 Å to 1000 Å and a silicon oxide surrounding the floating gate electrode is described. As an EPROM with a higher density of integration, a control gate formed on a floating gate is known (for example, Japanese Patent Application Laid-Open No. 1-30570). A method of manufacturing an EPROM in which a control gate is formed on a conventional floating gate will be described with reference to FIG.

【0004】

As illustrated in FIG. 9 (A), a plurality of memory cell MOS transistor regions 20 (only one memory cell MOS transistor region 20 is shown in relation to the illustration) and a plurality of memory cell MOS transistors controlling these memory cell MOS transistors. The peripheral MOS transistor region 10 (only one peripheral MOS transistor region 10 is shown for illustration purposes) is formed on the same silicon substrate 1. Therefore, silicon dioxide (SiO) on the silicon substrate 1₂) Gate oxide film 3 is formed, a tungsten (W) polyside layer (or polysilicon layer) 5 is formed on the gate oxide film 3, a silicon dioxide film 7 is further formed, and a W polyside layer is further formed on the gate oxide film 7. (Or polysilicon layer) 11 is formed. In order to form the gate electrode layer of the MOS transistor in the peripheral MOS transistor region 10, the photoresist film 15 is arranged above the gate forming region of the peripheral MOS transistor. Similarly, in order to form the control gate in the memory cell MOS transistor region 20, the photoresist film 17 is arranged above the control gate forming region.

【0005】

As illustrated in FIG. 9B, dry etching is performed on the resist film 15 and the resist film 17 as a whole. As a result, the W polyside layer 5 and the silicon dioxide film 7 excluding the region protected by the resist film 15 in the peripheral MOS transistor region 10 are removed. The remaining portion of the W polyside layer 5 becomes the peripheral MOS transistor gate portion 19. Also in the memory cell MOS transistor region 20, the W polyside layer 11 and the silicon dioxide film 7 except for the lower part of the resist film 17 are removed. The remaining W polyside layer 11 becomes the control gate portion 21. By dry etching, the head corners of the resist film 15 and the resist film 17 are considerably removed, and the head is rounded.

【0006】

As illustrated in FIG. 9 (C), the photoresist film 51 is further coated on the upper part. Etching is performed again from the upper part of the memory cell MOS transistor region 20 while leaving the peripheral MOS transistor region 10 as it is. As a result, the portion 17B shown by the broken line is removed from the resist film 51 in the memory cell MOS transistor region 20. As the etching progressed further, as shown in FIG. 9 (D), the W polyside layer 5 and the gate oxide film 3 below the resist film 17A of the memory cell MOS transistor region 20 were removed except for the resist film 17. The floating gate portion 27 is formed.

【0007】

After that, as shown in FIG. 10, the peripheral MOS transistor source region 31 and the drain region 32 are formed by LDD ion implantation, and the side walls 37A and 37B of silicon dioxide are formed in the peripheral MOS transistor gate portion 19, and the peripheral MOS is formed. A peripheral MOS transistor having a gate portion 19, a source region 31 and a drain region 32 is formed in the transistor region 10. Also in the memory cell MOS transistor region 20, the cell MOS transistor source region 33 and the drain region 34 are formed by LDD ion implantation to form the side walls 38A and 38B of silicon dioxide, and the memory cell MOS transistor region 20 is formed. A memory cell having a source area 33, a drain area 34, a floating gate part 27, and a control gate part 21 is formed. After that, an insulating film, contacts, etc. are formed on the upper layer of the partial cross section of the EPROM illustrated in FIG. 10, and the EPROM is completed.

【0008】

[Problems to be Solved by the Invention]

As illustrated in FIG. 9C, the resist film 17 on the upper part of the control gate portion 21 is considerably removed in the etching of the memory cell MOS transistor region 20. In FIG. 9C, the resist film 17, which was originally up to the resist film 17B shown by the broken line, becomes thinner than the above etching to the thickness of the resist film 17A shown by the solid line. Further, as illustrated in FIGS. 9 (D) and 10, at the stage of forming the floating gate portion 27, the thickness of the control gate portion 21 is also the thickness of the control gate portion 21A only by removing the control gate portion 21B shown by the broken line. Decreases to. That is, the control gate portion 21 above the floating gate portion 27 is etched in the etching process, and the thickness thereof becomes thin, so that the desired thickness cannot be maintained.

【0009】

The problem described above is the peripheral MOS transistor gate portion 19 as one electrode layer of the peripheral MOS transistor region 10, the floating gate portion 27 formed of the same layer as the peripheral MOS transistor gate portion 19, and the control gate in the upper layer thereof. This is due to the fact that the part 21 and the memory cell part having two layers of electrodes are processed on the same silicon substrate 1 by the same process.

【0010】

The above example exemplifies EPROM as a non-volatile semiconductor storage device, but it is not limited to EPROM and non-volatile semiconductor storage devices, but it is a case where electrodes of multiple layers are formed on the same semiconductor substrate by the same process, and it is partially In the case of a semiconductor device that forms electrode regions of different layers while sharing an electrode layer, the same problem as described above is encountered. Therefore, in the present invention, for example, for a non-volatile semiconductor storage device such as EPROM, a circuit having the above-mentioned two-layer electrodes and a transistor in which a gate is formed in the same layer as the above-mentioned two layers on the same semiconductor substrate. The purpose is to solve the problem when the transistors are formed by the same process and to make it possible to manufacture high-quality non-volatile semiconductor storage devices such as EPROM. Another object of the present invention is to make it possible to form a semiconductor device having a plurality of electrode layers in which different electrode regions are formed depending on the region, similar to the above-mentioned non-volatile semiconductor storage device.

【0011】

[Means for solving problems]

In order to solve the above problem, according to the first aspect of the present invention, it has a memory cell having two electrode layers and a gate electrode layer having a layer common to any one of the two electrode layers. In the method for manufacturing a non-volatile semiconductor storage device in which peripheral transistors are formed on the same semiconductor substrate, at least when the electrode layer above the memory cell is formed, the peripheral transistor portion is coated with a titanium film or a titanium silicide film. A method for manufacturing a non-volatile semiconductor storage device is provided. Preferably, a titanium silicide film is formed on the upper part of the source and drain regions of the memory cell portion.

【0012】

Further, according to the second aspect of the present invention, the memory cell having two electrode layers and the peripheral transistor having a gate electrode layer in common with any one of the two electrode layers are the same semiconductor. In the method for manufacturing a non-volatile semiconductor storage device in which a substrate is formed, at least when the electrode layer above the memory cell is formed, the peripheral transistor portion is covered with a tungsten film. A manufacturing method is provided.

【0013】

Specifically, the non-volatile semiconductor storage device is an EPROM, the memory cell has a control gate as an upper electrode layer, a floating gate as a lower electrode layer, and the peripheral transistor is a transistor that controls the operation of the memory cell. The gate electrode is the gate layer of the transistor.

【0014】

[Action]

For example, when patterning the control gate of an EPROM memory cell by etching, the titanium film or titanium silicide film, or the tungsten film is formed of the same material as the control gate, and the gate portion of the peripheral transistor and the peripheral transistor. It is used as a protective film that protects the source and drain of the source and drain from etching. As a result, a control gate can be formed in a simple process without damaging the peripheral transistors. That is, when a titanium layer, a titanium silicide layer, or a tungsten film is used as a protective film, it is easy to remove after use and the selectivity is improved. Titanium silicide is formed on the source and drain of peripheral transistors to reduce the resistance value and improve the operating speed. If a titanium silicide film is formed on the source and drain of the transistor of the memory cell, the operating speed of the memory cell is also improved. The non-volatile semiconductor storage device is preferably EPROM.

【0015】

[Example]

An EPROM manufacturing method will be illustrated as a first embodiment of the manufacturing method of the non-volatile semiconductor storage device of the present invention. An example of this example and an example of using a titanium or titanium silicide film as a protective film are shown. FIGS. 1 to 3 are manufacturing process diagrams illustrating a manufacturing method of EPROM. FIG. 3 shows a partial cross-sectional view of the EPROM, especially in the near-final manufacturing stage. The partial cross-sectional configuration of the EPROM shown in FIG. 3 is illustrated, and is one typical peripheral MOS transistor region 10 among a plurality of peripheral MOS transistor regions and one typical memory among a plurality of memory cells MOS transistor regions. The cell MOS transistor region 20 is shown. The LOCOS area 36 shown in FIG. 10 is not shown due to the illustration.

【0016】

After forming the element separation (LOCOS) region 36 as shown in FIG. 10 on the silicon substrate 1, the EPROM forms the peripheral MOS transistor region 10 and the memory cell MOS transistor region 20 with the LOCOS region 36 as a boundary. The memory cell MOS transistor region 20 includes a memory cell MOS transistor source region 33 and a drain region 34 formed on the silicon substrate 1, a gate oxide film 3 formed on the silicon substrate 1, and a gate oxide film 3 formed on the silicon substrate 1. Floating gate portion 27, silicon dioxide film 7, control gate portion 21, these gate oxide films 3, floating gate portion 27, silicon dioxide film 7, and silicon oxide side walls 38A, 38B formed on the side walls of the control gate portion 21. have. The upper part of the control gate portion 21 is titanium silicide (TiSi).₂) Titanium silicide films 69A and 69C are also formed on the upper parts of the films 69B, the source region 33 and the drain region 34.

【0017】

The peripheral MOS transistor region 10 is a source region 31 and a drain region 32 formed under the titanium silicide films 67A'and 67B', respectively, and a gate oxide film 3 formed on the silicon substrate 1 in the silicon substrate 1. It has a gate portion 19 formed on the gate oxide film 3, and silicon dioxide side walls 37A and 37B formed on the side wall of the gate portion 19. A titanium silicide film 65'is formed on the peripheral MOS transistor gate portion 19. An insulating layer, an electrode layer connected via contacts, and the like are formed above the peripheral MOS transistor region 10 and the memory cell MOS transistor region 20, but they are not directly related to the present invention, so illustrations are omitted. There is.

【0018】

The EPROM manufacturing method will be described with reference to FIGS. 1 to 3. Figures 1 to 3 illustrate the continuous manufacturing method, but the drawings are divided due to the illustration. As shown in FIG. 1 (A), a gate oxide film 3 is formed on the silicon substrate 1 as a whole, and a polysilicon layer 5 serving as a peripheral MOS transistor gate portion 19 and a floating gate portion 27 is formed on the gate oxide film 3. .. For the peripheral MOS transistor region 10, the gate portion 19, the silicon dioxide side walls 37A and 37B are formed, and the source region 31 and the drain region 32 are formed in the LDD structure. For the memory cell MOS transistor region 20, a silicon dioxide film 7 serving as a gate oxide film of the control gate portion 21 is formed on the polysilicon layer 5.

【0019】

As shown in Fig. 1 (B), the titanium film 25 is deposited as a whole. Examples of deposition conditions for the titanium film 25 are argon gas (Ar) 50 sccm, 3.5 Torr, DC power 4 KW, 200 degrees Celsius, and deposit thickness 300 Å by sputtering. Then, as shown in FIG. 1 (C), titanium in contact with silicon is reacted by a two-step annealing method to silicide to form a titanium silicide film. As a result, titanium silicide films 67A, 67B, 67C are formed on the peripheral MOS transistor source region 31, the gate portion 19, and the drain region 32. Since the peripheral MOS transistor region 10 is covered with the silicon dioxide film 7, no titanium silicide film is formed.

【0020】

As shown in FIG. 1 (D), the polysilicon layer 11 serving as the control gate portion 21 is deposited on the upper part of the peripheral MOS transistor region 10 and the upper part of the silicon dioxide film 7 of the memory cell MOS transistor region 20. Further, the phosphate film 17 is arranged on the upper part of the portion where the control gate portion 21 is formed.

【0021】

As shown in FIG. 2 (A), the control gate portion 21 is patterned. The etching method in this patterning is preferably suitable for etching the polysilicon layer 5 (SF).₆+ C₂Cl₃F₃) Perform dry etching using gas. To give an example of the etching conditions, SF₆/ C₂Cl₃F₃Dry etching at = 75sccm / 8sccm, 50mTorr, 1350W. When the control gate portion 21 is formed, the polysilicon layer 11 above the peripheral MOS transistor region 10 is also removed by etching, but the peripheral MOS transistor source region 31, the gate portion 19 and the drain region 32 are formed of the titanium silicide film 67A, Since it is coated with 65,67B, it will not be damaged by the above etching.

【0022】

As shown in FIG. 2 (B), dry etching is further performed to pattern the floating gate portion 27. Even in this etching, the peripheral MOS transistor gate portion 19, the source region 31, and the drain region 32 are protected by the titanium silicide films 67A, 65, 67B, and the peripheral MOS transistor portion is not damaged. However, in the etching process, the titanium silicide films 67A, 65, 67B are somewhat damaged and become somewhat thinner, as shown by the thinned titanium silicide films 67A', 65', 67B'. In the conventional method, in this patterning, it is necessary to dispose a resist in order to protect the memory cell MOS transistor region 20, but this is not necessary in this embodiment, and the process is simplified. Titanium silicide (TiSi)₂) Is difficult to etch with a fluorine-based gas, so it has a selectivity of 10 or more compared to silicon-based materials and is excellent in selectivity. In this way, by using the titanium film 25, only the control gate portion 21 and the floating gate portion 27 in the memory cell MOS transistor region 20 can be selectively and effectively etched by self-alignment.

【0023】

As shown in FIG. 2 (C), silicon dioxide is deposited on the entire surface, and then the entire surface is etched back, and the silicon dioxide side wall 38A, on the side wall of the control gate 21 and the floating gate 27 of the memory cell MOS transistor region 20. Form 38B.

【0024】

Preferably, the titanium film 69 is further deposited as shown in FIG. 2 (D). After that, it is annealed to form titanium silicide films 69A, 69B, 69C on the source region 33, the control gate portion 21, and the drain region 34 of the memory cell MOS transistor region 20, and the unnecessary titanium films are removed. .. As a result, the peripheral MOS transistor region 10 and the memory cell MOS transistor region 20 having the structure shown in FIG. 3 are formed. After that, LDD implantation, LDD side wall formation, source / drain / ion implantation treatment, etc. are performed. After that, the EPROM is completed by further performing processes such as forming an insulating tank, drilling contact holes, and connecting electrodes.

【0025】

As described above, in the first embodiment, the titanium silicide films 67A, 65, 67B formed on the upper part of the peripheral MOS transistor gate part 19, the source area 31 and the upper part of the drain area 32 when the control gate part 21 is formed are the control gates. It acts as a protective film against etching at the time of part 21 and prevents damage to the peripheral MOS transistor region 10. Further, according to this embodiment, the problem that the thickness of the control gate portion 21 becomes thin does not occur. Peripheral MOS Transistors The titanium silicide films 67A'and 67B'formed above the source region 31 and the drain region 32 lower the resistance values of the source region 31 and the drain region 32 and improve the operating speed of the peripheral MOS transistors. The titanium film 69 shown in FIG. 2 (D) is formed, and the titanium silicide films 69A and 69C are formed above the source region 33 and the drain region 34 of the memory cell MOS transistor region 20 to reduce the resistance value therein. As a result, the operating speed of the memory cell MOS transistor is also improved. That is, the operating speed of EPROM becomes faster.

【0026】

For example, a nitride film can be used instead of the titanium film 25 as the protective film of the memory cell MOS transistor region 20 described above, but after use, a chlorine-based gas is used to remove the film. , Silicon, polyside, tungsten polyside, etc. will be etched at the same time, which is not preferable. On the other hand, in this embodiment, only the titanium film can be easily selectively removed, which has an advantage that the selection ratio becomes large. The advantage of using the titanium film 25 instead of the nitride film is that the film thickness can be made as thin as possible. When making a gate mask, patterning is performed by hot resist in advance, but if the gate mask is thick, a difference in patterning change is likely to occur between the resist patterning and the shape after etching. For example, a nitride film has a tapered shape because the gate mask thickness is thick, and when a patterning of 0.5 μm is made when the gate mask thickness is 0.4 μm, the gate mask width is 0.65 μm. Therefore, it is preferable that the thickness of the gate mask is as thin as possible, and when the titanium film of this example is used, the selection ratio between the mask material and the gate electrode material is sufficiently large. There is.

【0027】

Various modifications can be taken with respect to the above-described embodiment. For example, in the above embodiment, the gate portion 19 of the peripheral MOS transistor region 10 is formed in the same layer as the floating gate portion 27 of the memory cell MOS transistor region 20, but the gate portion 19 is formed in the same layer as the control gate portion 21. You can also do it.

【0028】

Further, in the above embodiment, an example in which polysilicon is used as a forming material for the control gate portion 21, the floating gate portion 27, and the peripheral MOS transistor gate portion 19, respectively, has been described, but other suitable materials as the electrode material, for example, Tungsten (W) polyside, which has a lower resistance than polysilicon, can be used. As a second embodiment of the non-volatile semiconductor storage device of the present invention, examples of a method for manufacturing an EPROM using tungsten polyside for the control gate portion 121 and the floating gate portion 127 are shown in FIGS. 4 to 6. Since this second embodiment is almost the same as the first embodiment described above, detailed description is omitted, but in FIG. 4A, the layers to be the peripheral MOS transistor gate portion 119 and the floating gate portion 127 are made of tungsten poly. It is formed by the side layer 105, and in FIG. 4 (D), the layer to be the control gate portion 121 is formed by the tungsten polyside layer 111. The gas for dry etching the control gate portion 121 of the tungsten polyside layer 111 and the floating gate portion 127 of the tungsten polyside layer 105 is preferably the same as the etching of the polysilicon film described above (SF).₆+ C₂Cl₃F₃) Use gas. FIG. 6 shows a partial cross section of the EPROM corresponding to FIG.

【0029】

Also in this second embodiment, the peripheral MOS transistor region 10 is not damaged in the process of forming the control gate portion 12, and the control gate portion 21 is not thinned. In addition, the same effect as that of the first embodiment can be obtained in the second embodiment. In the second embodiment, the control gate portion 21 is formed of a tungsten polyside layer having a resistance lower than that of polysilicon, and the operating speed is improved. However, from the viewpoint of improving the operating speed, it is not necessary to form the floating gate portion 127 particularly with the tungsten polyside layer 105, and the floating gate portion 27 can be formed with the polysilicon layer 5 as in the first embodiment. ..

【0030】

As a third embodiment of the non-volatile semiconductor storage device of the present invention, the EPROM manufacturing process will be described with reference to FIGS. 7 to 8. This example shows an example in which tungsten (W) is used as the protective film instead of the above-mentioned titanium. The manufacturing process shown in FIG. 7 (A) is the same as the manufacturing process shown in FIG. 1 (A). As shown in FIG. 7 (B), tungsten films 125A, 125B, 125C are formed on the gate portion 19, the source region 31, and the drain region 32 of the peripheral MOS transistor region 10 by the CVD selective tungsten growth method. Since the memory cell MOS transistor region 20 is covered with the silicon dioxide film 7, the tungsten film is not formed. As a CVD selective tungsten growth condition, WF₆/ SiH₄CVD selective growth was performed at = 10 sccm / 8 sccm and film formation temperature 250 degrees Celsius. These tungsten films 125A, 125B, 125C are the protective films of the peripheral MOS transistor region 10 like the titanium silicide films 67A (67A'), 65 (65'), 67B (67B') in the first and second examples described above. Functions as.

【0031】

The processes shown in FIGS. 7 (C) and 8 (A) to (C) are the same as the processes of the first and second embodiments described above. However, the process shown in Fig. 2 (D) and Fig. 5 (D) is omitted. As a result, the EPROM shown in Fig. 8 (C) is formed. In this EPROM, the gate portion 19, the source region 31 and the drain region 32 of the peripheral MOS transistor region 10 are protected by tungsten films 125A, 125B and 125C.

【0032】

Also in this third embodiment, the tungsten polyside layer 111 can be used instead of the polysilicon layer 11. Further, the tungsten polyside layer 105 can be used instead of the polysilicon layer 5.

【0033】

In the above examples, an example in which titanium and tungsten are used as the protective film of the peripheral MOS transistor region 10 has been described, but the gate film, particularly the control gate portion 21, is etched (SF).₆+ C₂Cl₃F₃) Other materials that are not affected by etching gas such as gas can be used.

【0034】

In the above examples, EPROM is exemplified as a non-volatile semiconductor storage device, but the present invention is not limited to a non-volatile semiconductor storage device such as EPROM, and when a plurality of electrode layers are formed on the same semiconductor substrate, the layers are partially formed. It can also be applied to semiconductor devices having different layers, for example, two layers in one part and three layers in another part. The present invention can also be applied to the case of forming a plurality of electrode layers in a three-dimensional semiconductor device or the like.

【0035】

[Effect of the invention]

As is clear from the above examples, according to the present invention in which a titanium film (titanium silicide film) or a tungsten film is used as a protective film for peripheral transistors, an electrode layer is formed by a simple process without damaging the electrode layer. it can. Further, according to the present invention, the operating speed of the non-volatile semiconductor storage device can be improved.

[Simple explanation of drawings]

[Figure 1]

It is 1st partial figure which shows the manufacturing method of EPROM of 1st Example of the non-volatile semiconductor storage device of this invention.

[Figure 2]

It is a 2nd partial figure which shows the manufacturing method of EPROM of 1st Example of the non-volatile semiconductor storage device of this invention.

[Fig. 3]

It is a 3rd partial figure which shows the manufacturing method of EPROM of 1st Example of the non-volatile semiconductor storage device of this invention.

[Fig. 4]

It is a 1st partial view which shows the manufacturing method of EPROM of the 2nd Example of the non-volatile semiconductor storage device of this invention.

[Fig. 5]

It is a 2nd partial figure which shows the manufacturing method of EPROM of the 2nd Example of the non-volatile semiconductor storage device of this invention.

[Fig. 6]

It is a 3rd partial figure which shows the manufacturing method of EPROM of the 2nd Example of the non-volatile semiconductor storage device of this invention.

[Fig. 7]

It is 1st partial figure which shows the manufacturing method of EPROM of the 3rd Example of the non-volatile semiconductor storage device of this invention.

[Fig. 8]

It is a 2nd partial figure which shows the manufacturing method of EPROM of the 3rd Example of the non-volatile semiconductor storage device of this invention.

[Fig. 9]

It is a figure which illustrates the manufacturing method of the conventional EPROM.

[Fig. 10]

It is a partial cross-sectional view of EPROM manufactured by the manufacturing method shown in FIG.

[Explanation of symbols]

1 ... Silicon substrate, 3 ... Gate oxide film, 5 ... Polysilicon layer, 7 ... Silicon dioxide film, 10 ... Peripheral MOS transistor area, 11 ... Polysilicon layer, 15,17 ... Resist film, 19 ... Peripheral MOS transistor gate, 20 ... Memory cell MOS transistor area, 21,121 ... Control gate, 23 ... Silicon dioxide film, 25 ... Titanium film, 27,127 ... Floating gate, 31 ... Peripheral MOS transistor source area, 32 ... Peripheral MOS transistor drain area, 33 ... Memory cell MOS transistor source area, 34 ... Memory cell MOS transistor drain area, 36 ... LOCOS area, 37A, 37B ... Silicon dioxide side wall, 38A, 38B ... Silicon dioxide side wall, 65 ... Titanium silicide film, 65' Titanium silicide film, 67,67A, 67B ... Titanium silicide film, 69 ... Titanium film, 69A, 69B, 69C ... Titanium silicide film, 105 ... Tungsten polyside layer, 111 ... Tungsten polyside layer, 125A ~ 125C ... Tungsten film.