Manufacture of semiconductor device

[Detailed Description of the Invention]

[Industrial Application] This invention relates to the manufacturing method of a semiconductor device. [Description of the Prior Art] Conventionally, in MO3FET structure, in order to make resistance of a sauce Dorain field low, forming a metal membrane in the upper part of a sauce Dorain semiconductor field is performed. the [ under the present circumstances, ] -- the time of high concentration impurities addition semiconductor layer 2 being formed in the upper part of semiconductor substrate l, and patterning the sauce Dorain semiconductor field of the semiconductor layers 2 concerned, and metal membrane 3 on it in predetermined shape, as shown ino [ 1 ] figure, After etching metal membrane 3 unnecessary as a mask for photoresist film 4, high concentration impurities addition semiconductor layer 2 unnecessary as it is is etched. [Problem(s) to be Solved by the Invention] However, after patterning metal membrane 3 and forming sauce metal membrane 3a and the Dorain metal membrane 3b, in order not to leave unnecessary high concentration impurities addition semiconductor layer 2 to the field used as a channel, Since there is no metal membrane 3 with a high concentration impurities addition semiconductor layer and equal Etching rate when etching, As shown in Drawing 11, when Etching rate of metal membrane 3 is smaller than Etching rate of a high concentration impurities addition semiconductor layer, since a cave produces under metal membrane 3, a crack goes into the gate dielectric film which forms membranes next easily, and it reduces gate electric strength. As shown in Drawing 12, when Etching rate of metal membrane 3 is larger than Etching rate of a high concentration impurities addition semiconductor layer, while etching a high concentration impurities addition semiconductor layer, metal membrane 3 is etched into a transverse direction, and the characteristic of a semiconductor device shows variation. The object of this invention is to provide the manufacturing method of the semiconductor device which can make stair-like easily section shape of a high concentration impurities addition semiconductor layer and a metal membrane, and can raise step coverage. [Means for solving problem] A thing which is characterized by that the present invention comprises the following and which makes a manufacturing method of a semiconductor device the gist. The 1st process of forming a high concentration impurities addition semiconductor layer in the upper part of a semiconductor substrate, The 2nd process of depositing a metal membrane on the upper surface of the above-mentioned high concentration impurities addition semiconductor layer, The 3rd process of arranging a photoresist film on the upper surface of the above-mentioned metal membrane, and patterning the above-mentioned metal membrane by using the photoresist film concerned as a mask, The 4th process of mobilizing a photoresist film and covering the side of the above-mentioned Accessory membrane by heat-treating the above-mentioned photoresist film, and the 5th process of etching the above-mentioned high concentration impurities addition semiconductor layer by using the above-mentioned photoresist film as a mask. [Function] A high concentration impurities addition semiconductor layer is formed in the upper part of a semiconductor substrate of the 1st process, a metal membrane accumulates on the upper surface of a high concentration impurities addition semiconductor layer according to the 2nd process, a photoresist film is arranged by the 3rd process on the upper surface of a metal membrane, and a metal membrane is patterned by using the photoresist film concerned as a mask. And when a photoresist film is heat-treated by the 4th process, a photoresist film is mobilized, the side of a metal membrane is covered, and a high concentration impurities addition semiconductor layer is etched by using a photoresist film as a mask by the 5th process. At this time, since the metal membrane is covered by the photoresist film, only a high concentration impurities addition semiconductor layer is etched, and a high concentration impurities addition semiconductor layer and a metal membrane become stair-like [ that section shape ]. [Example] Hereinafter, one example which materialized this invention is described according to a drawing. It is a sectional view to which Drawing 7 meets the top view of MOSFET of an example, and Drawing 8 meets the A-A line of Drawing 7. 1st [ The ] figure~figure 6 is a figure showing the manufacturing process. As shown in Drawing 1, while forming high concentration impurities addition silicon layer 11 in the upper part of silicon substrate 10, metal membrane 12 is deposited on the upper surface. And as shown in Drawing 2, photoresist film 13 is arranged on the upper surface of metal membrane 12, patterning of the metal membrane 12 is carried out to it, and sauce metal membrane 12a and the Dorain metal membrane 12b are formed in it. Next, as shown in Drawing 3, by heat-treating photoresist film 13, sagging is mobilized and carried out and the side of metal membranes 12a and 12b and the partial surface of high concentration impurities addition silicon layer 11 are covered. The heat treatment at this time should just be more than the temperature from which photoresist film 13 produces sagging, and processing time is arbitrary. For example, the quantity of resist sagging shown by Ll can be about 0*5 micrometers among the 3rd figure by carrying out for [ 15 minutes ] grade heat treatment by 180 degreeC. The same effect is acquired also by pressurizing resist during heat treatment. Then, as shown in Drawing 4, etching removal of the high concentration impurities addition silicon layer 11 unnecessary as a mask is carried out for this photoresist film 13, and it is sauce silicon field 11a. Train silicon field 11b is formed. Then, as shown in Drawing 5, photoresist film 13 is removed. At this time, the interval (silicon field 11a, the level difference of llb and metal membranes 12a and 12b) shown by L2 becomes almost equal to the interval shown by Ll in the 3rd figure among the 5th figure. Next, as shown in Drawing 6, gate dielectric film 14 is formed, and as shown in Drawing 8, MOSFET is manufactured by forming each electrode (sauce metal electrode 15a, the Dorain metal electrode 15b, gate metal electrode 15c). Thus, in this example, high concentration impurities addition silicon layer 11 is formed in the upper part of silicon substrate 10, and it is the 1st process of To, Metal membrane 12 is deposited on the upper surface of high concentration impurities addition silicon layer 11, and it is the 2nd process of To, By arranging photoresist film 13 on the upper surface of metal membrane 12, patterning metal membrane 12 by using the photoresist film 13 concerned as a mask, and heat-treating the 3rd process of To, and photoresist film 13, photoresist film 13 is mobilized and the side of metal membranes 12a and 12b is covered (the 4th process). And high concentration impurities addition silicon layer 11 was etched by using photoresist film 13 as a mask (the 5th process). As a result, metal membranes 12a and 12b are covered by photoresist film 13, and only high concentration impurities addition silicon layer 11 is etched, The stage shape of sauce Dorain metal membranes 12a and 12b and high concentration impurities addition silicon layer 11 (sauce Dorain silicon field 11a, 1 lb), i.e., L2 in the inside of the 5th figure, is easily controllable by the conditions (temperature and time) to which sagging of the photoresist film 13 is carried out. Thus, the step coverage of gate dielectric film 14 can be raised, and gate electric strength can eventually be made to improve. This invention is not limited to the above-mentioned example, and as shown in Drawing 9, it can be used also for the thin film transistor (TPT) which is one form of MOSFET, for example. That is, it may apply to a means to form the sauce field and the Dorain field in the case of creating a semiconductor device on insulating board 16. A semiconductor substrate and a high concentration impurities addition semiconductor layer may not be limited to silicon, and, otherwise, may be germanium, GaAs, SiC, etc. [Effect of the Invention] As explained in full detail above, according to this invention, the outstanding effect which can make stair-like easily section shape of a high concentration impurities addition semiconductor layer and a metal membrane, and can raise step coverage is demonstrated.

[Brief Description of the Drawings]

the [ the sectional view to which the figure and Drawing 7 in which 1st / The / figure~figure 6 shows the manufacturing process of MOSFET of an example meet the top view of MOSFET of an example, and Drawing 8 meets the A-A line of Drawing 7, the section construction drawing of a thin film transistor where Drawing 9 is separate, and ] -- theta [ 1 ] figure~figure 12 is a sectional view for explaining conventional technology. As for a high concentration impurities addition semiconductor (silicon) layer and 12, in a semiconductor (silicon) board and 11, a metal membrane and 13 are [ lO ] photoresist films. Applicant for a patent The Japan, Inc. autoparts research institute cost Reason People Patent attorney Drawing 7 of obligation 1 Hironori (one others) the -- 8E lI4 figure Drawing 5 The 6th Figure