Pll controller

[Detailed Description of the Invention]

[Industrial Application] The present invention relates to a phase lock Droop (PLL) control device.

Art of [former] Be shown in Drawing 5 as a means to expand the capture range of a PLL device conventionally, It changes until it becomes carrying out said [ of the self-propelled oscillating frequency (below free-oscillating frequency) of a variable frequency oscillator (VCO) ] to reference frequency, and the free oscillating frequency output condition of a lock state is latched, and it is made to hold. As shown in Drawing 6, the free oscillating frequency of VCO is first united with outline reference frequency by AFC, applying automatic frequency adjustment (henceforth, AFC) simultaneously with 1 phase comparison, and there is a thing of performing PLL control after that. Hereinafter, operation of the device of each figure is explained. In the device of Drawing 5, as shown in Drawing 3 based on the output of flip-flop (FF)3~6 for which current switch 8 inputs the output of counter l as data Di~D4, current is outputted. It is I sin so that the free oscillating frequency of VCO9 can certainly oscillate reference frequency with the current value of I win to I tax at this time. I wax is set up. ! If it detects having Response(ed) on the current which steps up on stairs as shown in @3 figure, and VCO oscillating frequency having also changed, and having become turning with reference frequency in frequency comparator (FC) 16, Supply of a clock is stopped to switch 7 or Hutobufu rope (FF)3~6 by frequency comparison Base output, and the state is held. And it is carried out from this state in control by the PLL control device which comprises VCO9, phase comparator 10, crystal oscillator 2, and LPFIm. In the device of Drawing 6, frequency-voltage conversion of the oscillating frequency of VCO9 and the reference frequency is carried out, respectively with mono-multi vibrator (henceforth, MM) 17 and 18 and smooth filters (LPF) 19 and 20, They are the voltage or the composition of applying feedback to VCO9 so that it may become equal.

[an invention or the issue which it is going to solve] -- however, in the account conventional example of inside-"-, it is in the following problems. ■ Since In the device of the 5th illustration is performing digital drawing frequency Search, it is needed in frequency comparator 16, and invites increase of a circuit scale, and complication. ■ As shown in Drawing 6, in performing Analog AFC, in order to construct the control loop of AFC in addition to the control loop of PLL, it increases in chic quantity. Swarming by carrying out, the object of the present invention is an easy circuit Constructing capture range or a large and extremely stable thing which a PLL system m system Equipment. With the means and the operation Co present invention for solving L subject, Composition which distinguishes change of error voltage when it goes into a capture range by a means for Because which looks for frequency which goes into a capture range in PLL control not to have, and to distinguish change of error voltage of PLL, One step which memorizes self-propelled oscillating frequency (free oscillating frequency) of vCO which constitutes PLL, and f-stage which changes free oscillating frequency of VCO are provided. Therefore, large circuit scale increase is avoided and it can do [ obtaining stable PLL control or ].

[Example] The PLL system m system Place block diagram of one example of the present invention is shown in Drawing 1. The reset circuit where 1, a counter, and 2 reset counter l and Hutobufu rope (FF)3~6 in Drawing 1 at the time of power turn-on ON, etc., The current switch which switch 28 for which 7 carries out clock supply to FF3~6 17 m changes a current value, and it outputs, LPF which 9 makes a voltage variable oscillator (following VCO), and 10 makes a phase comparator and to which 1N carries out smooth [ of the phase comparator lO specific output error voltage ], Voltage which 12 transforms into the current according to the output voltage of LPFII -> below Current converter VI converter, 13 is a reference voltage machine (Vr)! The comparator with which 4 measures the output of LPFII and the output of reference voltage machine 13, and 15 are timing circuits which create the control signal of switch 7 by the output of comparator 14. Lock range f11 and capture range t'c which are defined as Drawing 2 from the frequency-error voltage characteristic in PLL control are shown. In Drawing 1, if first supplied in a power supply, counter l and FF3~6 will be reset by reset signal R of reset circuit 2, and the output of counter 1 and the output of FF3~6 will be set to rOJ. As shown in Drawing 3 for every cycle of arbitrary clocks CK inputted into the counter after the end of reset, it is outputted from the current or current switch 8 of a relation. It sets up to become the low frequency which the free oscillation cycle of VCO9 by 110, the circuit, or the constituent child did variation Well-considered at this time, and shifted from the capture range of PLL, I Set wax as the value which changes oscillating frequency of VCO9 into the error voltage shown in Drawing 2 (1), or the frequency which may change from minus to a plus direction. By setting up the output of current switch 8 as mentioned above, it sets to the present invention, At the time of power turn-on ON, by the free oscillating frequency of Ah Li and VCO9, or the output of current switch 8, PLL is gone up to the state where it shifted rather than the lock state, stair-like, as shown in Drawing 3, and it goes into a capture range soon, and PLL will be in a lock state. If the output current of current switch 8 is further raised, error voltage will rise as it was shown in Drawing 2. Reference voltage machine (Vr) 13 outputs the potential of VRO to LPFII by high impedance, and it outputs potential called VR of VRO-△V to comparator 14. △V is comparator 14 or the offset voltage attached so that a comparator output might be certainly set to Hi at the time of PLL non-Lock. It is obtained in PLL lock In state error voltage or a comparator output when it goes up, as shown in Drawing 4 with comparator 14, Timing circuit 15 outputs the control signal of switch 7 by the output of comparator 14, the clock supply to FF3~6 is stopped, and data D1~D4 of counter l is made to latch to FF3~6. It is ■C by above-mentioned operation. It is fixed to the value approaching the oscillating frequency of outline Xta or, and free oscillating frequency will be in the circuit state which only PLL control is committing. If it can respond to wide range frequency, without taking a capture range by constituting as mentioned above more than needed and puts in another way, it can do [ obtaining a stable synchronous oscillator with less Gitta than Because which may narrow a capture range, or ]. In this example, whether the number of FF (3~6) being four and its number can be arbitrarily designed by how many good frequency variable step width (inside of current variable) is taken as Tattoo which goes.

Effect Co of [invention As explained above, when changing the self-propelled oscillating frequency of a variable frequency, it is change of the error voltage of a phase comparison means, When it detects that PLL control went into the lock state from the non-Lock state and error voltage keeps the self-propelled oscillating frequency at the time of the control state near reference voltage, it can do [ obtaining stable The and the large PLL control device of a capture range by easy composition, or ].

[Brief Description of the Drawings]

The graph which shows the relation [ in which Drawing 1 shows the example of the present invention / the block diagram and Drawing 2 ] of the error voltage and frequency of a phase comparator to PLL control, The graph Drawing 3 indicates the relation between the output of FF3~6 of the 1st illustration and the output of current switch 8 to be, the graph which shows the error voltage characteristic [ in / in Drawing 4 / the present invention ] and the relation of a control signal, Drawing 5, and wII6 figure are block diagrams showing the composition of the PLL control device of conventional technology. 1 ... Counter 3~6 ... Flip-flop (FF) 9 ... Voltage variable oscillator (VCO) 10 ... Phase comparator 11 ... LPF 14 ... Drawing 1 of a comparator Applicant for a patent Canon incorporated company 7 three representative Marushima matter-[Nishiyama [ D 2 Nono Megumi ] 2nd [ The ] figure fc Drawing 6 of Tooth timing circuit 15 output