Orthogonal transformation arithmetic unit

[Detailed Description of the Invention]

(Field of the Invention) The present invention is a digital still video camera, a facsimile, and a color copy, It is used for a TV phone etc. and related with the arithmetic unit which performs rectangular conversion of the discrete cosine transform (following DCT or DCT conversion I mean) for performing compression and extension of a color picture, discrete sign conversion (it is called following DST or DST conversion), etc. (Conventional work $1) Rectangular conversion operations, such as DCT and DST, are known as one of the conversion encoding methods for information compression. The example which performs a data compression through DCT processing is shown in Drawing 14. The picture information read with CCD reading element 150 is changed into a digital signal with A/D conversion machine 152, and one screen is memorized by frame memory 154 temporarily. DCT conversion is carried out by DCT processing circuit 156, it is quantized in quantization circuit 158, Huffman conversion is carried out in Huffman encoding time 8160, and the data of frame memory 154 is memorized by storage device 162. When the data memorized by storage device 162 is reproduced by the picture, after being decrypted by the Huffman decryption circuit 164 and passing through dequantization circuit 166, it is returned to image data by IDCT circuit 168, and is changed and outputted to an analog signal with D/A converter 170. When the case where divide into the block which constitutes a picture from (NXN) a pixel, and two-dimensional DCT conversion of that the block of each is carried out is explained, a two-dimensional DCT operation is C(U) =17f2 at a formula at the time of -cos(2j+1) (Vpi/2N)-=-(1) Ll=0. It is C(upsilon) = 1 at the time of U!=0. C(V)=1f (x+j) is data of a pixel at the time of C(V) = 1/fi■!=O at the time of v=o. A two-dimensional DCT operation should just perform a one-dimensional DCT operation also about i, after performing a one-dimensional DCT operation about j. If a one-dimensional DCT computing equation is transformed into a vector calculation equation about the case of N= 8, it will become the following (2) equations. It is here and is alpha=cos(2/8) pi. beta =cos (1/8A pi) Delta=sin(1/8) pi lambda= eos pi (1/16) mu= sin pi (3/16) Gamma=cos (3/16) pi It is nu= sin pi (1/16). If graphical-data-compression processing is performed through a DCT operation, in extension operation of returning the compressed picture to the original data, the IDCT operation (Inverse D CT operation) which is twist operations of a DCT operation will be performed. I It will become the following formula if a DCT operation is expressed by a formula. - Time [ of cos (2j+1) (Vpi/2N), -, and (3) U=O ] C (U) = 1/, After a dimension IDCT operation performs a one-dimensional IDCT operation to C(V)= about ■ at the time of C(■) =1-/J'''2■!=0 at the time of C(U) =1■=0 at the time of /"iU!=0, A one-dimensional IDCT operation may be performed also about U, and a - dimension IDCT operation is expressed like the following (4) equations, when it expresses by a vector calculation formula. (2) If it is going to calculate the vector calculation equation of an equation or (4) equations, it is necessary to perform multiplication with a conversion factor, and data X and 2. (1) the two-dimensional DCT computing unit which performs a formula is shown in Drawing 15 -- as (NXN) Conversion pixel F (U, V) is obtained by [ which hang conversion procession 132 of conversion factor W (1, j) to picture 130 of the origin which comprises a pixel ] calculating by collapsing and applying coefficient 4 C(U) C(V)/N2 to it. When this operation is performed with a multiplier and an adding machine, as shown in Drawing 16, multiplier 36-1~36-N2 [ N2 piece ] and multiplier 140 which hangs N2 bit adding machine 138 and coefficient 4 C(U) C(V)/N" are needed. There is the ROM look-up table method which uses a ROM table instead of a multiplier although multiplied. For example, if it tries to perform vector calculation of (2) types, as shown in Drawing 17, ROM102 holding the data corresponding to the product of each conversion factor and input data may be prepared, and ROM 102 may be read by making conversion factor data and input data into an address. 104 is an address generator. Multiple conversion factor data and input data are inputted into address generator 104 in a bit, respectively. (Object of the Invention) If the one-dimensional IDCT operation for the one-dimensional DCT operation for graphical data compression and its extension divided the picture into the block constituted from a pixel (8X8), for example, it needs to perform 64 multiplication and 56 addition. Therefore, since DCT processing time and IDCT processing time become long and a circuit scale becomes large, integrated-circuit-izing becomes difficult. Also when replacing with a DCT operation as rectangular conversion and performing a DST operation, the problem to which processing time becomes long similarly and one circuit scale becomes large arises. In the ROM look-up table method, when input data is made into m kinds of n bit and conversion factor, the address space of ROMIO2 becomes mX2." If this is applied when performing DCT conversion of (SXS), the conversion factor shall be fixed by eight kinds, since the number of 8-bit pixels is eight, input data will be set to n= 64, and an address space will become 8X2." It is difficult to realize such large-scale capacity. An object of the present invention is to make it possible to simplify composition of a DCT computing unit or a DST computing unit, and to integrated-circuit-ize it. An object of the present invention when realizing rectangular conversion operations, such as DCT, by the ROM look-up table method is to make capacity of ROM small. (Means for solving problem) Drawing 1 showing an example explains the present invention. The present invention is with one-dimensional rectangular cross conversion computing units 4, such as the 1st one-dimensional DCT computing unit, Storage device 2 which memorizes the output temporarily, and one-dimensional rectangular cross conversion computing units 6, such as the 2nd one-dimensional DCT computing unit that considers the output of storage device 2 as an input, While addressing storage device 2, it has address generator 8 with which a line address and a sequence address are replaced according to the writing of storage device 2, and the change of operation of read-out. 10 is an address decoder and 12 is read-out and a write control part. in order to carry out high-speed operation, it is shown in Drawing 5 of an example -- as -- memory fellows M2 -- 2a versus 1 -- it being 2b provided and passing changeover switch circuit 20.22 for 1st one-dimensional rectangular cross conversion computing unit 4 and 2nd one-dimensional rectangular cross conversion computing unit 6, respectively -- both storage device i2 a. Changeover switch circuit 20.22 is switched so that 2nd one-dimensional rectangular cross conversion computing unit 6 may be connected to storage device 2b (or 2a) of another side, when it connects with 2b and 1st one-dimensional rectangular cross conversion computing unit 4 is connected to one storage device 2a (or 2b). In the present invention, while address generator 8 addresses storage device 2 in Drawing 1, operation which replaces a line address and a sequence address according to execution of the operation of 1st one-dimensional rectangular cross conversion computing unit 4 and 2nd one-dimensional rectangular cross conversion computing unit 6 is performed again, Read-out and write control part 12 can perform operation which writes the new operation result of 1st one-dimensional rectangular cross conversion computing unit 4 in the same address, after reading and acting as Ro of the one data of storage device 2. In the present invention, the pretreatment circuit which performs the addition and subtraction between input data so that a part of coefficient may be set to O again in the case of the rectangular conversion process which performs a discrete cosine transform or discrete sign conversion is provided, The rectangular conversion process circuit can perform multiplication with the coefficient which is not 0, and addition of the multiplication result about the data added or subtracted in the above-mentioned pretreatment circuit. In the present invention, rectangular conversion by the ROM look-up table method for using a ROM table is performed further, Let the conversion factor data (every 1 bit and two or more bits) of input data be an address, The data read from the ROM table is shifted in a higher rank or the direction of a low rank according to the bit position in the input data of the address, and it can add about all the bits of input image data. In the present invention, it may have a pretreatment circuit which performs the addition and subtraction between input data so that a part of conversion factor may become the preceding paragraph of a rectangular conversion circuit at O in the case of a rectangular conversion process in the ROM look-up table method. (OPERATION) In the present invention, 1 set of one-dimensional rectangular cross conversion computing units realize a two-dimensional rectangular cross conversion operation. It divides into the block which constitutes a picture from (NxN) a pixel, and explains the case where two-dimensional DCT conversion of that the block of each is carried out. It becomes (1) type which already said that a two-dimensional DCT operation is expressed by a formula. (1) When a formula is transformed, it is -cos (2i+1) (Upi/2N). = sigma(2C (U) /N) F (i, V) and cos (2i+1) (Upi/2N) ..... (2C(V)/N) (5) prize F(i, V) = sigmaf cos (i, j) (2j+1) (V pi/2N) --- (6) It is set to J= 0. Here, (5) types express the - dimension DCT operation of F (i, V), and (6) types express the - dimension DCT operation of f (IIj). Therefore, the two-dimensional DCT operation of N taps (NXN) can perform a - dimension DCT operation (6) type about a line (or sequence), and can obtain the result of a two-dimensional DCT operation by performing a - dimension DCT operation (5) type about a sequence (or line) continuously. 2nd one-dimensional DCT computing unit 6 reads that by which 1st one-dimensional DCT computing unit 4 wrote data in for whereabouts or the column direction of storage device 2 in Drawing 1 for a column direction or whereabouts, and it performs a DCT operation. Although the above is explanation about compression, the extension which is a reverse action can be processed by the same method only by a conversion type changing. Two-dimensional I D CT of extension It is set to (3) which already said that (Inverse DCT) an operation is expressed by a formula. - cos (2i+1) (lx/2N) It becomes. Here, (7) types express the - dimension ■DCT operation of f (V, i), and (8) types express the - dimension IDCT operation of F (U, V). Therefore, the two-dimensional IDCT operation of N taps (NXN) can perform a - dimension IDCT operation (8) type about a line (or sequence), and can obtain the result of a two-dimensional IDCT operation by performing a - dimension IDCT operation (7) type about a sequence (or line) continuously. It is also the same as when using DST conversion as a rectangular conversion operation. When the present invention performs the DCT operation of (8x8), the number of the kinds of conversion factor is eight, and since every 1 bit of each pixel is calculated about 8-pixel input data, it is set to n= 8, and a required address space is set to 8x28. If it is a scale of this level, it will become possible to integrated-circuit-ize. It is if it pretreats using the symmetry of a conversion factor matrix and is made for a part of conversion factor to be set to O, About 4-pixel input data, since operation Suddenly comes to be good, every 1 bit of each pixel is set to n= 4, required address spaces decrease in number to 8X24, and also realization becomes easy. A pretreatment circuit performs the following operation. It divides into the block which constitutes a picture from a pixel (8X8), and explains the case where one-dimensional DCT conversion of that the block of each is carried out. In a pretreatment circuit, it is input data Xo and X0.""" X7 CX2+X5t CX2+X5t(X10 Xl)+ (X3+X4) (it changes into XOX7L (X2-x), (xl-x6), and (xa -x4).) + If the DCT conversion type of (2) types is expressed so that the data changed in the pretreatment circuit may be made into a variable. It becomes the following (9) types. In an extension process, the formula of an IDCT operation turns into the following (10) equations. Here a =cos (1/4) pi b =cos(1/8)x d =sin(1/8) 7C e =cos (1/16) pi f =cos(3/16) x g "5inch(1/16) pi h =sin (3/16) It is yt. (9) According to the formula, the half of a conversion factor is set to O. A coefficient does not need to multiply about the portion of O. (10) After the IDCT operation by a formula (they are X, xl, and "'x about xo+X7L (X2+XS) l (xx"xs)+(X3+X4) * (Xo Xv') t (Xz Xs)+ (x, -xG) and (x3x4).), Post-processing to return is performed. (EXAMPLE) Drawing 1 expresses one example. 2 is a storage device for transport and is RAM of a NxN word. If N is set to 8, it will have the capacity of 64 words. 4 and 6 are one-dimensional DCT computing units, and it has them N pieces at a time, respectively. N will be 8 if the block of a unit which performs a DCT operation is made into a pixel (8X8). - In order to specify the address at the time of writing the operation result of dimension DCT computing unit 4 in storage device 2 and to specify the address for reading the data written in storage device 2 to one-dimensional DC and T computing unit 6, address generator 8 is formed. If storage device 2 considers it as 64 words, a 6-bit address will occur from address generator 8 as an address. 1o is an address decoder which inputs the address and addresses storage device 2. 12 is read-out and the write control part for controlling the writing and read-out in storage device 2. An example of address generator 8 is shown in Drawing 2. Since a 6-bit address is generated, two 3 focus counters 14.16 are formed, and a 6-bit address is constituted combining each every 3 bits output. From counter 14, the 3-bit address of (AO, aluminum, A2) shall be outputted, and the 3-bit address of (A3.A4.A5) shall be outputted from counter 16. A 6-bit address is constituted combining this every 3 bits address. 18 is a switch circuit which switches the combination of an every 3 bits address, and if this switch circuit 18 is switched to one side, an address will become (AO, aluminum, and A2.A3 *A4.A5), and will become switching to another side (A3 *A4.A5.AO, aluminum, A2). The relation of these switched addresses is equivalent to what replaced the line address and sequence address in storage device 2. Switch circuit 18 is switched in conjunction with read-out and write-in operation. It is switched so that an address may progress for whereabouts at the time of writing, and it is switched so that it may go to a column direction at the time of read-out. Or it is switched to the contrary so that an address may go to a column direction at the time of writing, and it is switched so that it may progress for whereabouts at the time of read-out. Next, Drawing 3 and Drawing 4 explain operation of this example. Drawing 3 expresses the address in storage device 2. An address shall be given so that an address may progress for whereabouts at the time of writing, namely, so that it may progress in order of (0, O), (1, O), (2*0), (3, O), and ...... (N-1, N-1). Thereby, the operation result of one-dimensional DCT computing unit 4 is written in according to the address for the whereabouts of storage device 2. This is written in as shown by the arrow of a dashed line in Drawing 4. Next, operational mode changes to read-out, switch circuit 18 of an address generator is switched, and a line address and a sequence address are switched. Thereby, as addressing by memory Wear N2 is shown by the solid line in Drawing 4, it changes to a column direction in order of (0, O), (0*1), (0, 2), (0, 3), and - (N-1*N-1), and the data of storage device 2 is read to one-dimensional DCT computing unit 6. (N-1, N-1) After read-out to an address finishes, it changes to a write mode again, and it is switched so that an address may progress for whereabouts again. Thus, the DCT operation is repeated. The writing in storage device 2 is performed to a column direction, and it may be made to read it for whereabouts. In other examples, it is read-out and write control part 12, and is shown, for example in Drawing 5, In the specified address, the data of the address is read to one-dimensional DCT computing unit 6 in Loule Bell of 1 cycle of clock CK, and it controls to write the operation result of one-dimensional DCT computing unit 4 in the same address in the high-level period of the cycle. Next, Drawing 3 and Drawing 6 explain operation of this example. An address is given so that introduction and an address may progress for whereabouts, namely, so that it may progress in Drawing 3 in order of (0, O), (L O), (2 *O), (3, O), and ...... (N-1, N-1). Thereby, the operation result of one-dimensional DCT computing unit 4 is written in according to the address for the whereabouts of storage device 2. This is written in as shown by the arrow of a dashed line in Drawing 6. Next, switch circuit 18 of an address generator is switched and a line address and a sequence address are switched. Thereby, addressing with storage device 2 changes in Drawing 3 in order of ((0, O), (0, 1), 0*2), (0, 3), and ...... (N-1, N-1). First, the data of (0 or 0) address is read to one-dimensional DCT computing unit 6, and the operation result of one-dimensional DCT computing unit 4 is continuously written in the same (0, O) address as data after that. Next, a memory address changes to (0, 1), - dimension DCT computing unit 6 reads the data of the address, and the operation result of one-dimensional DCT computing unit 4 is continuously written in the (0, 1) address as data. The arrow of the column direction shown as the solid line in Drawing 6 expresses the direction of the 1st read-out operation, and the arrow of the column direction of one point m and W+ expresses the direction of the 2nd write-in operation. If this operation is repeated and it performs to a memory address (N-1, N-1), the line address and sequence address of a memory address will be switched again, Shortly, it meets for whereabouts, continues with read-out of the data based on one-dimensional DCT computing unit 6, and the writing of the operation result from one-dimensional DCT computing unit 4 to the same address is performed to an address (N-1, N-1). Drawing 7 expresses the example of further others. In this example, a pair of storage devices 2a and 2b for transport which become in RAM are formed. They are a switch circuit which 20 switches one-dimensional DCT computing unit 4 to storage devices 2a and 2b, and it connects, and a switch circuit which 22 switches one-dimensional DCT computing unit 6 to storage devices 2a and 2b, and it connects. Although illustration is omitted, the address generator, the address decoder, and read-out and a write control part are connected to storage device f2a and 2b like Drawing 1. Operation of the example of Drawing 7 is explained. When switch circuit 20.22 is in the state of a figure. In storage device 2a, the operation result of one-dimensional DCT computing unit 4 is written in for whereabouts, and - dimension DCT computing unit 6 reads the data currently written in storage device 2b to the column direction. After the writing of storage device 2a and read-out of storage device 2b finish, switch circuit 20.22 is switched. The operation result of one-dimensional DCT computing unit 4 is shortly written in storage device 2b for whereabouts, and - dimension DCT computing unit 6 reads the data currently written in storage device 2a to the column direction. Thus, with the storage device of another side, it reads simultaneously, writing in with the storage device of a direction. This is repeated while switching switch circuit 20.22. In Drawing 7, a two-dimensional DCT operation can be performed to Drawing 1 at twice as many The [ as this ] speed to a ratio. Drawing 8 and Drawing 9 explain the device which calculates the 1st one-dimensional DCT operation and the 2nd one-dimensional DCT operation one by one. Drawing 8 illustrates a principle. First, as shown in (A), it is conversion factor wi for whereabouts (j) (=cos (2j+1) (Vpi/2N)) to pixel f of the original picture (i+j) to the j-th cycle. It hangs, and it does for whereabouts and unites, The - dimension DCT operation for the whereabouts which hang coefficient 2C(V)/N on it is given, conversion pixel F for whereabouts (i, V) is calculated, and F (i+1.V) is similarly calculated to a cycle (i+1) eye. When the - dimension DCT operation for whereabouts of N cycles is completed, it goes into a column direction-dimension DCT operation and is shown in (B), Conversion pixel F (U, V) is computed, column direction conversion factor wv(i) (=cos (2i+1) (Upi/2N)) of a pixel (U, V) being hung to pixel F (i, V) to be changed, and doing to a column direction, uniting with it, and applying coefficient 2C(U)/N to That 9. Drawing 9 expresses the device which performs this example. Pixels f (i, O) and f of one line of the original picture (i, 1) .. It is a pixel (U.) to f (i, N-1), respectively. ■ In order to hang conversion factor wi for the whereabouts which are) (j), N multiplier 54-1~54-N is provided. 56 is an adding machine adding the operation result of those multiplier 54-1~54-N, and 58 is a multiplier which hangs coefficient 2C(V)/N on the added result. Thereby, a whereabouts-oriented one-dimensional DCT operation is performed. Next, in order to perform the one-dimensional DCT operation of a column direction, N multiplier 62-1~62-N is provided. Between multiplier 58 and multiplier 62-1~62-N, selector switch 60-1~60-N is provided, respectively, a selector switch corresponding by position i of a line is turned ON alternatively, and conversion factor wv(0)~wv (N-1) is hung by each multiplier 62-1~62-N. 64 is an adding machine adding the multiplication result by multiplier 62-1~62-N, 66 is a multiplier which applies coefficient 2C(U)/N to the addition result, and conversion pixel F (U, V) is computed by the multiplication result. Drawing 10 expresses the example provided with the pretreatment circuit, and expresses the case where divide a picture into the block of a pixel (X[ 8 ] 8) as an example, and a DCT operation is performed. 32-O~32-7 is input data X, respectively. It is the shift register and latch circuitry which Stepping and hold ~x7 in the timing of clock CLOCK 1. 34-1~34-4 is an addition subtraction circuit which takes in two predetermined data held in a shift register and latch circuitry 32-0~32-7, and performs addition or subtraction according to a select signal. 36-1~36-4.38-1~38-4 is the shift register and latch circuitry which Stepping and hold the data calculated in addition subtraction circuit 34-1~34-4 in the timing of clock CLOCK 2. 40 is coefficients a and b, in order to perform the multiplication and addition which are DCT processing circuits and were expressed by (9) formulas. dr 8'+fy gv h was held and it has the adding machine for performing 31 addition with the multiplier for performing 32 multiplication. It becomes circuit composition with the same said of the arithmetic unit which performs an IDCT operation. It becomes composition with the same said of the arithmetic unit which performs a DST operation and ID5T operation. Drawing 11 expresses the ROM look-up table circuit equivalent to one multiplication with the one-dimensional DCT operation in the DCT conversion device of the example by the ROM look-up table method. 76 is an address generator and a bits [ two or more ] conversion factor data and every 1 bit input data are inputted as an address. If it is considered as eight kinds of conversion factor, conversion factor data will be 3 bit data. 1 bit of input data is inputted at a time sequentially from the maximum bit (LSB) or the minimum bit (M S B). 78 is ROM holding data. When input data is 411 I+, conversion factor data is made into the address of ROM78, and when input data is "0'', 0 is used as an address of ROM78. The register in which 80 holds an adding machine and 82 holds the data from adding machine 80 temporarily, 84 shifts the bit position of the data held at register 84 in the direction of a higher rank, when the data of register 82 is inputted into input data from the maximum bit, When input data is inputted from the minimum bit, it is 1 bit Shifter which shifts the bit position of the data held at register 82 in the direction of a low rank. The data by which 1 bit shift was carried out in the direction of a higher rank or the direction of a low rank by 1 bit Shifter 84, and the data from ROM78 are added to adding machine 8o. If input data explains as what is inputted 1 bit at a time from the maximum bit, ROM78 will be first accessed to the 1-bit input data and conversion factor data of the maximum bit n as an address of ROM78, and data Dn will be obtained. Data Dn is held through adding machine 80 at register 82. What was held at register 82 is made into Output. Next, ROM78 is accessed to the 1-bit data and conversion factor data of a bit (n-1) eye of input data as an address of ROM78, and data Dn-□ is outputted from ROM78. In adding machine 80, in order to double this data Dn-0 and data D of register 82, the data by which 1 bit shift was carried out is added in the direction of a higher rank by 1 bit Shifter 84, that added thing is held at register 82, and Output is updated. Final Output is obtained by repeating this operation until input data becomes the minimum bit. In this case, the capacity of ROM78 is set to several meters (this example 8) of the kind of conversion factor. An example of the DCT processing circuit in the case of performing the one-dimensional DCT operation expressed with (2) types by Drawing 12 is expressed. The shift register to which the data for one line containing eight pixels as which 86 was expressed by 8 bits is sent, and 88 are each every 8 bits pixel X. - It is the latch holding Xt. 90 is a DCT processing circuit by the ROM look-up table method, and the adding machine with which the circuit shown in Drawing 1 adds the output of every eight pieces and those eight circuits to each DCT processing circuit 90 is contained. In each DCT processing circuit 90, it is input data X. -although x7 [ 1-bit ] is inputted at a time in order from the minimum bit or -- from the maximum bit and is not shown in a figure, the operation which conversion factor data was also inputted and was shown in Drawing 11 is performed. The output of each DCT processing circuit 90 is 8-bit output data 2 *-77. 92 is a shift register, arranges 2o-27 in order and outputs it. In Drawing 12, ROM capacity required in order to obtain the output data of 2 *-77 is 8x28. Drawing 13 expresses the example for performing the operation expressed by (9) formulas using the symmetry of the DCT conversion factor, in order to make capacity of a ROM table still smaller. Shift register 88 and DCT processing circuit 90a. Pretreatment circuit 94 is provided between 90b. Since four conversion factors of the second half are 0 in four DcT processing circuits 90a which obtain output z, z2. z, and zG by a conversion factor matrix's being arranged by pretreatment circuit 94 like (9) types, and setting a half to 0, The input data to which such 0 and credit perform Calculation becomes unnecessary, and every 1 bit each 4 bits from input data (XO+Xt) r (Xt+X6) t (xz+Xs) r (X3+X4) are inputted into four DCT processing circuits 90a. Since four conversion factors of the first half are 0 in four DCT processing circuits 90b which obtain output Z Engineering, Z3. ZS, and Z, the input data to which such 0 and credit perform Calculation becomes unnecessary -- four DCT processing circuits 90b -- input data (xO-X 7) r (X 1xt)+ (X2 Xi) l (X3 X4) from -- every 1 bit each 4 bits are inputted. Each DCT processing circuit 90a and 90b is provided with the adding machine which adds the output of every four pieces and those four circuits for the circuit of Drawing 11. In Drawing 13, ROM capacity required in order to obtain the output data of zI and ~z7 decreases to 8x24. (EFFECT OF THE INVENTION) If 1 set of one-dimensional rectangular cross conversion computing units realize a two-dimensional rectangular cross conversion operation by the present invention, If the number of required multipliers considers the unit of 1, for example, a rectangular conversion operation, as the block of a pixel (8X8), by the present invention, an 8+8=16 piece multiplier will be sufficient, and the conventional method will enable it for a device to become easy and to integrated-circuit-ize, while 64 multipliers are required. In the storage device which memorizes the operation result of the 1st one-dimensional DCT computing unit temporarily, While reading to a column direction what was written in for whereabouts, new data is written in a column direction, If addressing, and read-out and write-in control are performed so that data new for whereabouts may be written in while reading for whereabouts the data written in the column direction, The capacity of a required storage device has been a 1-block thing of a word enough, if the block of an operation unit makes it (NXN) a pixel (N X N). As a result, while there is little memory capacity and it ends, high-speed operation can be made to perform. High-speed operation is attained by making a storage device into one pair and being made to read the writing of one storage device, and the storage device of another side simultaneously. If it has a pretreatment circuit of input data which sets some [ in a two-dimensional DCT operation or a two-dimensional DST operation ] coefficients to O, the number of the multiplier of a DCT processing circuit or a DST processing circuit and adding machines will decrease, and a process speed will become quick so much. It becomes easy for a circuit scale to also become small and to integrated-circuit-ize it. By using 1 bit of input data at a time for an address, when realizing a rectangular conversion process by the ROM look-up table method, a rectangular conversion process can be realized now with small ROM capacity. ROM capacity can be decreased, if it has a pretreatment circuit using the symmetry of the conversion factor and a part of conversion factor is set to 0.

[Brief Description of the Drawings]

In Drawings 2, Drawing 1 is a block diagram showing one example, and a block diagram showing an example of the address generator in the example, In Drawings 5, the figure showing the address of a storage device [ in / in Drawing 3 / the example ] and Drawing 4 are Drawing 1 showing the addressing method of a storage device which shows operation of the example, and a timing diagram showing operation of read-out and the write control part of other examples, Drawing 6 is a figure showing the addressing method of a storage device which shows operation of the example, In Drawings 8, Drawing 7 is a block diagram showing the example of further others, and a figure showing the concept of the operation of the example of further others, In Drawings 9, Drawing 10 is a circuit diagram of the example, and a block diagram showing the DCT arithmetic unit of the example of further others, The block diagram and Drawings 12 and 13 showing one multiplier equivalent portion of the ROM look-up table method in the example of further others [ Drawing / 11 ] are a block diagram showing the DCT arithmetic unit in an example, respectively. The block diagram in which Drawing 14 shows a data compression and an extension system, the key map with which Drawing 15 expresses the conventional two-dimensional DCT operation, and Drawing 16 are a circuit diagram of the conventional example, and a block diagram showing one multiplier equivalent portion of the ROM look-up table method by the method of the former [ Drawing / 17 ]. 2.2a, 2b ...... A storage device, 4, 6 ...... - A dimension DCT computing unit, 8 ...... An address generator, 12 ...... Read-out and a write control part, a 14.16....3-bit counter, 18, 20.22 ...... A changeover switch circuit, 32-O~32-7 ...... A shift register, latch circuitry, 34-1~34-4 ...... An addition subtraction circuit, 36-1~36-4, 38-1~38-4 ...... A shift register, latch circuitry, 40 ...... - A dimension DCT processing circuit, 76 ...... An address generator, 78 ...... [ ...... 1 bit Shifter, 86 / ..... A shift register, 88 / ...... DC by a latch, 90 and 90a, and the 90 b.....ROM look-up table method T processing circuit ] ROM, 80 ...... An adding machine, 82 ..... A register, 84