Display device

[Detailed Description of the Invention]

Field of the Invention The present invention relates to displays, such as a liquid crystal display which drive the picture matter arranged in the shape of a matrix one by one, and displayed the picture. PRIOR ART Drawing 9 is a top view showing the rough composition of the liquid crystal display of the conventional passive-matrix drive system. Liquid crystal panel 1 makes a liquid crystal layer intervene between two or more common electrodes Y and two or more segment electrodes X which were arranged in the direction which crosses mutually, and is constituted, and the liquid crystal layer of the portion which each common electrode Y and segment electrode X intersect serves as each picture matter. That is, a plurality of picture matter is arranged by liquid crystal panel 1 in the shape of a matrix. Segment drive circuits 2A and 2B for supplying the drive signal corresponding to display data to each sequence tviX of picture matter, i.e., each segment, are arranged at the up-and-down both-ends, i.e., end of sequence of picture matter, side of liquid crystal panel 1. These segment drive circuits 2A and 2B comprise a plurality of tape carriers (it is also hereafter called TAB for short) 3 and printed wiring boards (it is hereafter called PWB for short) 4 by which the large scale integration circuit (it is hereafter called LSI for short) chip was mounted on the plastic film, respectively. That is, the input side terminals of the LSI chip of TAB3 which the other end side of each TAB3 is connected to liquid crystal panel 1 at the PWB4 side, and the one end side of each TAB3 adjoins via the printed wiring on PWBJ are electrically connected. The output terminal of the LSI chip of each TAB3 is connected to two or more segment electrodes X in which liquid crystal panel 1 corresponds, respectively. Also about the composition of common drive circuit 5 arranged at the right end side of liquid crystal panel 1, It is constituted by a plurality of TAB6 and PWB7 like the case of the above-mentioned segment drive circuits 2A and 2B, The input side terminals of the LSI chip of each TAB6 are electrically connected via the printed wiring on P W B T, and the output terminal of the LSI chip of each TAB6 is connected to two or more common electrodes Y in which liquid crystal panel 1 corresponds, respectively. On above-mentioned P W B V, it is segment drive circuit 2A further, Connector 9 for inputting a signal and a power supply from power supply bias circuit 8 and the exterior which generate the bias of the multiple level impressed to segment electrode X and common electrode Y of a liquid crystal panel] from the LSI chip of T A B3.6 in 2B or common drive circuit 5, etc. are mounted. It is electrically connected via jumper line 10 between PWB4 by the side of Segumen l-drive time 12A and 2B, and PWB 7 by the side of common drive circuit 5. Object of the Invention However, in the conventional liquid crystal display mentioned above, PWB 4 and 7 other than TAB3.6 is needed for constituting segment drive circuits 2A and 2B and common drive circuit 5, and it has the problem that part mark increase. Therefore, the object of the present invention is to provide the display which can reduce part mark. The means for solving section pressure The line of picture matter is specified one by one in the line drive circuit which consists of a plurality of tape carriers who have an integrated circuit chip matched with two or more lines as which the present invention arranged a plurality of picture matter in the shape of a matrix to the display panel, and was connected to this display panel, and picture matter was determined, respectively, The signal corresponding to display data is given to each sequence of picture matter in the sequence drive circuit which consists of a plurality of tape carriers who have an integrated circuit chip matched with two or more rows as which it was connected to the above-mentioned display panel, and picture matter was determined, respectively, In the display which drives the picture matter of the specified line one by one and on which made it make a display panel display a picture, Among the terminals in both a line drive circuit and a sequence drive circuit, or one tape carrier of each, The terminal which it should connect for each other between [ adjoining ] tape carriers is divided into two places for every terminal in each tape carrier, and it forms, and connects the divided terminal to the terminal in which the next tape carrier corresponds in piles, It is a display connecting between each tape carrier's terminals. OPERATION Since connection between terminals between [ which constitute a line drive circuit and a sequence drive circuit / adjoining / a plurality of ] tape carriers can be made, without making p W B intervene if the present invention is followed, PwB can be omitted in a line drive circuit or a sequence drive circuit, and part mark are reduced. EXAMPLE Drawing 1 is a top view showing the rough composition of the liquid crystal display of the passive-matrix drive system which is one example of the present invention. Two or more common electrodes Y and two or more segment t' which arranged liquid crystal panel 11 in the direction which crosses mutually! A liquid crystal layer is made to intervene between IMX(s), it is constituted, and the liquid crystal layer of the portion which each common electrode Y and segment electrode X intersect serves as each picture matter. That is, a plurality of picture matter is arranged by liquid crystal panel 11 in the shape of a matrix. Segment drive circuits 12A and 12B for supplying the drive signal corresponding to display data, each sequence X, i.e., each segment electrode, of picture matter, divide into a upper end [ of liquid crystal panel 11 ], and lower end side, i.e., the one end side and the other end side of a sequence of picture matter, and it is arranged. That is, both segment drive circuit 12A by the side of the upper end of liquid crystal panel 11 and segment drive circuit 12B by the side of a lower end comprise a plurality of TAB 13 which mounted the LSI chip on the plastic film, Those TAB 13 adjoining comrades pile up the side piece part mutually, and are arranged. Common drive circuit 15 arranged at the right end side of liquid crystal panel 11 as well as the above-mentioned segment drive circuits 12A and 12B comprises a plurality of TAB 16, and those TAB 16 adjoining comrades pile up the side piece part mutually, and are arranged. Drawing 2 is a block diagram showing roughly the circuit composition of the above-mentioned liquid crystal display. LSI chip 16a 16b expresses the LSI chip which constitutes common drive circuit 15 and which is mounted for every TAB16, and in order to explain simply here, it shows the case where common drive circuit 15 consists of two TAB16. These LSI chips 16a and 16b are circuits which bear the function to specify each line of picture matter, i.e., each common t8 i!Y, as line sequential, contain the bidirectional register, and are connected to common electrode Y in which liquid crystal panel 11 corresponds with a plurality of output terminal y1~yn(s), respectively. The above-mentioned LSI chips 16a and 16b have two shift data input/output terminal DIOLDIO2, respectively, By connecting data input/output terminal DIOI of LSI chip 16b of another side with shift data input/output terminal Dr02 of one LSI chip 16a, Cascade connection of such LSI chip 16a16b is made. On the other hand, LSI chips 13a and 13b express the LSI chip which constitutes segment drive circuit 12B and which is mounted for every TABI3, and in order to explain simply here, they show the case where segment drive circuit 12B consists of two TAB13. Since the same may be said of the circuit composition of segment drive circuit 12A in Drawing 1, explanation of segment drive circuit 12A is omitted here. These LSI chips 13a and 13b are circuits which bear the function which supplies the drive signal corresponding to display data DO~D3, and contain the bidirectional register in each sequence X, i.e., each segment electrode, of picture matter, It is connected to segment electrode X in which liquid crystal panel 11 corresponds with a plurality of output terminal X1~xm(s), respectively. The above-mentioned LSI chips 13a and 13b are also two shift data input/output terminals EIOI, respectively. They are these LSI chips 13a by having EIO2 and connecting data input/output terminal EIOI of LSI chip 13b of another side with shift data input/output terminal EIO2 of one LSI chip 13a. Cascade connection of the 13b is made. Segment drive circuit 12B denoted by LSI chips 13a and 13b and common drive circuit 15 denoted by LSI chips 16a and 16b are connected to display control circuit 17 which controls these circuits. Namely, output terminal S of display control circuit 17 which outputs the scanning data for specifying each common Electricity tIilY of liquid crystal panel 11 It is connected to shift data input/output terminal DIOL of LSI chip t6a for a common drive, Clock output terminal CP1 of display control circuit 17 which outputs the clock which makes a cycle the scanning period which scans the picture matter for one line, Clock input terminal CK of LSI chips 16a and 16b for a common drive, and LSI chip 13a for a segment drive, Clock output terminal CP2 [ another ] of display control circuit 17 which outputs the clock which makes a cycle the period which was connected to latch pulse input terminal LP gas of 13b, and carried out the rate of the scanning period several minutes is LSI chip 13a for a segment drive. It is connected to clock input terminal XCK of 13b. The exchange-ized signal outputted from output terminal FR of display control circuit 17, being given to LSI chips 13a and 13b for a segment drive, and LSI chips 16a and 16b for a common drive -- a display system -- a teacher -- display data DO~D3 by which the data output terminal of circuit 17 is Output(ed) is given to LSI chips 13a and 13b for a segment drive. The above-mentioned LSI chips 13a and 13b for a segment drive, and LSI chips 16a and 16b for a common drive, It has input terminal SHL which inputs the signal which specifies the shift direction of the bidirectional shift register contained in them, respectively, High-level potential VDD is given to LSI chips 13a and 13b for a segment drive as the shift direction specification signal, and potential VSS of a low level is given to LSI chips 16a and 16b for a common drive. In the bidirectional shift register of LSI chips 16a and 16b for a common drive, a shift direction is defined in the direction which goes to output terminal y1 ->yn, DIOL is provided in an input and, as for a shift data input/output terminal, DIO2 is provided in an output by this. LSI chip 13a for a segment drive In 13b, the shift direction of a bidirectional shift register is defined in the direction which goes to output terminal x 1-+x m, and, as for a shift data input/output terminal, an input and EIO2 are provided for E 101 in an output. A high is carried out and potential VDD of a bell is given to CIF 1~data input/output terminal E IOl of top LSI chip 13a for a segment drive as shift data. Power supply bias circuit 18 is a circuit which supplies bias VO~■5 of the multiple level for liquid crystal panel 11 drive to LSI chips 13a and 13b for a segment drive, and LSI chips 16a and 16b for a common drive. Drawing 3 is a top view showing the facies which expanded one TAB 13 in segment drive circuits 12A and 12B, and Drawing 4 is a top view showing the facies which expanded one TAB16 in common drive circuit 15. As for these TAB13.16, facies are on one reverse T character-like plastic film, One LSI chips 13a and 13b for a segment drive and LSI chip 16a for a common drive which were shown in Drawing 2, 16b is closed and mounted by resin, and the pattern of the terminal connected to the electrode in which each output terminal 11 of an LSI chip, i.e., a liquid crystal panel, corresponds is extended and allocated in narrow end 19a on the plastic film 19, Shift data input/output terminal EIO1 [ in / in double width end 19b on plastic film 19 / the input side terminal, i.e., Drawing 2, of an LSI chip ], EIO2, DIOI, The pattern of terminals, such as DIO2, clock input terminal CK, XCK, input terminal SHL for shift direction specification, and an input terminal for bias vO~V5, extends, and is allocated. That is, in an LSI chip, the same input side terminal is divided and provided in two places, those extended patterns are divided into the right and left of double width end 19b, and it is Arrangement! It is carried out. furthermore -- dividing into double width end 19b of the above-mentioned plastic film 19 at right and left -- two slits 20 -- each above-mentioned input side terminal and To intersect -- it is formed like. Drawing 5 is a figure showing the terminal arrangement in LSI chip 13a13b for a segment drive, and Drawing 6 is a figure showing the terminal arrangement in LSI chip 16for common drive 'a, and 16b. It is liquid crystal Pao to the end to which it turns to the narrow end 19a side in Drawing 3 with LSI chips 13a and 13b for a segment drive, Output terminal x1~xm connected to segment electrode X of Le 11 is arranged, and at the end suitable for the double width end 19b side in Drawing 3, the input side terminals, such as shift data input/output terminal ElO1.EIO2, divide into two places of right and left [ the same thing ], and are arranged. Output terminal y1~yn similarly connected to common electrode Y of liquid crystal panel 11 about LSI chips 16a and 16b for a common drive at the end suitable for the narrow end 19a side in Drawing 4 is arranged, At the end suitable for the double width end 19b side in Drawing 4, the input side terminals, such as shift data input/output terminal DIO1.DI02, divide into two places of right and left [ the same thing ], and are arranged. Drawing 7 (a) and (b) is the elements on larger scale of TAB13 for a segment drive shown in Drawing 3. Before long, Drawing 7 (a) is a top view expanding and showing left one side of double width end 19b in TAB 13, and Drawing 7 (b) is a top view expanding and showing right one side of double width end 19b in TAB13. At left one side of Drawing 7 (a), they are shift data input/output terminal EIO2 from the left-hand side, and power supply terminal V[lD, for example, The input side terminals, such as VSS and bias input terminal V2.V3.\15. power supply terminal ■DD, are arranged in these order, and it is at right one side of Drawing 7 (b), The input side terminals, such as source terminal VDD, bias input terminal V 5, V 3, y 2, power supply terminal VSS, VDD, and shift data input/output terminal EIOI, are arranged in these order in shift data input/output terminal EIO2 from right-hand side. As a result, it is in the state piled up as right one side of another TAB 13 which adjoins left one side and right-hand side of one TAB 13, and is arranged showed in Drawing 1, For example, shift data input/output terminal EIOI of one TAB13 overlaps with shift data input/output terminal EIO2 of TAB13 of another side via slit 20, and is power supply terminal VDD. The things with VSS, bias input terminal V2.VB, V5 [ same ], etc. will overlap via slit 20. By soldering these terminals that overlap mutually and connecting, it is the 2nd (between the terminals of LSI chip 13a which adjoins as shown in 21, and 13b is connected.). About shift data input/output terminal EIO1 and EIO2, it is in Drawing 7 (a) and (b), Pattern partial EIOla over slit 20 used as a portion, EIO2a, EIO2b, and the portion directly connected to LSI chips 13a and 13b dissociate slightly, and it is formed with Handa. At left one side of TABI3 of a head [ in / for example / by this / Drawing 1 ], It is connected to power supply terminal VDD with Handa instead of being kept dissociated from separation pattern partial Er02a as it is, since the connection with the next TAB13 was unnecessary when the shift data input/output terminal EI02 was chosen as an input side. The voltage of power supply terminal VDD in this case is given as shift data to shift data input/output terminal EI02 of top LSI chip 13a, as mentioned previously. The same may be said of the case of shift data input/output terminal E IOI of another side. Theandl currently formed in each input side terminal or a Split layer pattern portion, and l~21 are used for connecting the capacitor for power supply noise reduction to TAB13. Drawing 8 (a) and (b) is the elements on larger scale of TAB 16 for a common drive shown in Drawing 4. Before long, Drawing 8 (a) is a top view expanding and showing left one side of double width end 19b in TAB 16, and Drawing 8 (b) is a top view expanding and showing right one side of double width end 19b in TAB 16. At left one side of Drawing 8 (a), they are shift data input/output terminal DIO2 from the left-hand side, and power supply terminal VDD, for example, The input side terminals, such as VSS, bias input terminal Vl, and V4.V5, are arranged in these order, and it is at right one side of Drawing 8 (b), Shift data input/output terminal DIO2, bias input terminal V5.V4.Vl, power supply terminal VSS, VDD, and shift data input/output terminal DI01 etc. is arranged in these order from right-hand side. Also in this case, it is in the state piled up as right one side of another TAB16 which adjoins left one side and right-hand side of one TAB 16, and is arranged showed in Drawing 1, For example, shift data input/output terminal DIO1 of one TAB16 overlaps with shift data input/output terminal DI02 of TAB 16 of another side via slit 20, The same things will overlap via slit 20, power supply terminal VDD, VSS, and bias input terminal V1.V4.V5 etc. solders these terminals that overlap mutually, and it connects, Between the terminals of LSI chip 16a which adjoins as shown in Drawing 2, and 16b is connected. For example, separation pattern partial DIO2a is formed about shift data input/output terminal DIO2, Connection with shift data input/output terminal DIOL of another TAB16 is chosen, or the composition which enabled it to choose connection with power supply terminal VDD is the same as that of the case of TAB 13 by the side of the segment mentioned above. Rough operation of the above-mentioned liquid crystal display is explained below according to the block diagram showing in Drawing 2. It synchronizes with the clock outputted from output terminal CPI of display control circuit 17, In common drive circuit 15 inside, the scanning data similarly outputted from display control circuit 17 is shifted from the shift data input/output terminal DIO1 side of LSI chip 16a to shift data input/output terminal Dr0211 of LSI chip 16b. According to the shift of scanning data, the voltage signal generated based on bias vO~v5 which Supplies, drive signal 18, i.e., the power supply bias circuit, which specify common electrode Y of liquid crystal panel 11, from output terminal y1~yn of LSI chips 16a and 16b corresponding to the shift position is outputted. On the other hand, it synchronizes with the clock outputted from output terminal CP2 of display control circuit 17, Inside segment drive circuit 12B, a shift action is performed by using potential VDD as shift data to the shift data input/output terminal EIO2 side of LSI chip 13b from the shift data input/output terminal EIO1 side of LSI chip 13a. LSI chip 13a corresponding to the shift position according to the shift of shift data, If display data DO~D3 outputted to each bit of the register in 13b one by one from display control circuit 17 is taken in and the display data corresponding to the picture matter for one line is taken in, Lunch of these display data is carried out in the timing of the clock outputted from output terminal CPI of display control circuit 17, The voltage signal generated based on bias V Q~■5 supplied from drive signal 18 corresponding to each display data, i.e., a power supply bias circuit, is given to segment electrode X of liquid crystal panel 11 from output terminal x1~xm to which LSI chips 13a and 13b correspond. By the above-mentioned operation of common drive circuit 15 and segment drive circuit 12B, the picture matter of liquid crystal panel 11 drives according to the order-of-rows foreword, and the picture corresponding to display data is displayed on liquid crystal panel 11. Although what [ two ] is the same as an input side terminal was divided into right and left, and was arranged in the LSI chip of TAB13.16 and the case where distribution formation of the extended pattern of those input side terminal was carried out on one side of plastic film 19 from there at right and left was shown in addition in the above-mentioned example, Not only this but the composition which does not divide the input side terminal into two places with an LSI chip is possible. That is, an extended pattern is arranged for example, in left one side by the surface side of one plastic film from the input side [ one place ] terminal of an LSI chip in this case, It is good also as double-sided wiring to make the back side of one plastic film face the same input side terminal by through hole wiring, and form an extended pattern from the back side to the position of right one side. By constituting in this way, it can wire easily, without making the pattern distributed to right and left produce intersection. In the above-mentioned example, although the case of the liquid crystal display of a passive-matrix drive system was shown, it is applicable not only to it but other displays, such as a liquid crystal display of other methods, and also an EL display. EFFECT OF THE INVENTION As mentioned above, inside [ according to the display of the present invention ] of the terminal in both a line drive circuit and a sequence drive circuit, or one tape carrier of each, The terminal which it should connect for each other between [ adjoining ] tape carriers is divided into two places for every terminal in each tape carrier, and it forms, and connects the divided terminal to the terminal in which the next tape carrier corresponds in piles. Since it constitutes so that between each tape carrier's terminals may be connected, connection between terminals between [ which constitute a line drive circuit and a sequence drive circuit / adjoining / a plurality of ] tape carriers can be made, without making P W B intervene, PWB is omitted in a line drive circuit or a sequence drive circuit -- it thing food * comes and can reduce part mark.

[Brief Description of the Drawings]

Drawing 1 is a top view showing the rough composition of the liquid crystal display which is one example of the present invention, Drawing 2 is a block diagram showing the rough circuit composition of the liquid crystal display, Drawings 3 and 4 are top views showing the facies of TAB for a segment drive of the liquid crystal display, and TAB for a common drive, respectively. Drawing 5 is a figure showing the terminal arrangement in the LSI chip of the TAB for a segment drive, Drawing 6 is a figure showing the terminal arrangement in the LSI chip of the TAB for a common drive, The top view which Drawing 7 expands a part of the TAB for a segment drive, and is shown, the top view which Drawing 8 expands a part of the TAB for a common drive, and is shown, and Drawing 9 are top views showing the rough composition of the conventional liquid crystal table water device. 11 .. a liquid crystal panel and 12A, 12 B .. segment drive circuit, 13 ... TAB for a segment drive, 13a, 13b [ Patent attorney Stroke count Keiichi part ] ... The LIS chip for a segment drive, 15 and a common drive circuit, 16 ... TAB for a common drive, 16a, 16b ... LSI chip representative for a common drive