Data sink

[Detailed Description of the Invention]

[0001]

[Industrial Application]

This invention relates to a data receiver, especially the data receiver which can prevent the quality fall of receiving information in signal transmission of digital numerals.

[0002]

[Description of the Prior Art]

Also when a bit crack occurs under the influence of a noise in a transmission signal (henceforth a bit serial signal), as a method read comparatively correctly, multiple sampling points are established, for example in 1 bit, 1 bit is read many times, and the method of judging a bit by majority judging is known well. Drawing 7 is a block diagram showing such a conventional data receiver shown in JP,57-053169,A.

[0003]

1 is an input terminal and a bit serial signal is inputted. Input terminal 1 is connected to serial signal input circuit 2. One output of this serial signal input circuit 2 is sent out to data input terminal D of the 1st shift register 3, and the output of another side is sent out to sampling pulse generating circuit 6. The output of sampling pulse generating circuit 6 is sent out to the 1st reading terminal T and part circumference way 7 of shift register 3. Output terminal Q1~Q9 of this 1st shift register 3 is connected to input terminal D of the 2nd shift register 4 via majority circuit 8. The output of part circumference way 7 is sent out to reading terminal T of the 2nd shift register 4. The output of the 2nd shift register 4 is outputted as a signal of a bit parallel from output terminal 5-1~5-3.

[0004]

Next, the time chart of Drawing 8 is used together and explained about operation. Drawing 8 (a) shows an example of the bit serial signal equivalent to one character inputted from input terminal 1 of Drawing 7, S1 shows a start bit (1 bit), P shows a parity bit (1 bit), and S2 shows a stop bit (2 bits). (S1 of Drawing 8 (d), P, and S2 are the same definitions). Drawing 8 (a) shows the state where cathode noise 9-1, and 9-2 and anode noise 10-1~10-3 are mixed in a bit sequence.

[0005]

If serial signal input circuit 2 of Drawing 7 sends out a start signal to sampling pulse generating circuit 6 and this start signal is inputted into sampling pulse generating circuit 6 in falling of the front tip of start bit S1 of Drawing 8 (a), Sampling pulse generating circuit 6 generates two or more sampling pulses per bit at an interval for a predetermined period, as shown in Drawing 8 (b). In this example, nine sampling pulses are generated among 1 bit.

[0006]

Since output terminal Q1~Q9 of the 1st shift register 3 is connected to majority circuit 8, If the number of times of being [ cathode noise 9-1, and 9-2 and anode noise 10-1~10-3 mix into 1 bit and / a noise at the sampling time in 1 bit ] detection is smaller than the number of times of regular signal detection as shown in Drawing 8 (a), In order to carry out majority, the regular signal which the noise was disregarded and was determined by majority is outputted to the input terminal of shift register 4.

[0007]

Whenever part circumference way 7 calculates the pulse which sampling pulse generating circuit 6 generated and calculates it nine pieces, it sends out the data reading command pulses shown in Drawing 8 (c) to reading terminal T of the 2nd shift register 4. The 2nd shift register 4 reads and stores data from input terminal D based on the data reading command pulses inputted into reading terminal T, and outputs it as a bit parallel signal from output terminal 5-1~5-3.

[0008]

[Problem(s) to be Solved by the Invention]

Since the conventional data receiver is constituted as mentioned above, if an error occurs more than the majority of the bit signal with which it was sampled by the sampling pulse which occurs within a time [ 1-bit ], an error will be produced to the bit signal determined by majority, There was a problem that the quality of receiving information deteriorated. This invention was made in order to cancel the above problems, and an object of an invention is to obtain the data receiver which lessens the error of the received data and can improve the quality of receiving information.

[0009]

[Means for Solving the Problem]

An invention concerning Claim 1 performs a sampling for each bit of a bit sequence including bit error detection information transmitted serially two or more times, Two or more sampling data are obtained for every bit, and from these sampling data, a two or more rows receiving bit sequence corresponding to a bit sequence is generated, and it is made to make a logic judgment of corrigenda for every receiving bit sequence based on bit error detection information included for every receiving bit sequence.

[0010]

As for an invention concerning Claim 2, the number of predetermined rows summarizes a bit sequence in Claim 1, and it constitutes 1 block, Block error detection information is added for every block to make a block bit sequence, A sampling is performed for each bit of a block bit sequence transmitted serially two or more times, Two or more sampling data are obtained for every bit, and a two or more rows receiving block sequence corresponding to a receiving bit sequence corresponding to a bit sequence and a block bit sequence is generated from these sampling data, While making a logic judgment of corrigenda for every receiving bit sequence based on bit error detection information, based on block error detection information, it is made to make a logic judgment of corrigenda for every receiving block bit sequence.

[0011]

[Function]

A two or more rows receiving bit sequence is generated, a logic judgment of corrigenda is made based on bit error detection information for every receiving bit sequence of this, and it enables it to choose the right thing from a two or more rows receiving bit sequence in the invention concerning Claim 1.

[0012]

In addition to logic judgment of the receiving bit sequence unit concerning Claim 1 of corrigenda, based on block error detection information, a logic judgment of corrigenda is made per block, and it enables it to choose the right thing from a two or more rows receiving block bit sequence in the invention concerning Claim 2.

[0013]

[Example]

Example 1. Drawing 1 is a block diagram showing one example of this invention, in the figure, 11 is a microprocessor (henceforth CPU) and ROM12 and RAM13 are connected to CPU11. The operation (after-mentioned) which a program is stored in ROM12 and shown in Drawing 3 is made to perform to CPU11. RAM13 is a memory which stores data. The output of serial signal input circuit 2 is inputted into CPU11 in the form of the bit sequence of the logic signal shown in Drawing 2 (a). CPU11 generates in a program the sampling pulse (outside, not outputted) shown in Drawing 2 (b), takes in data, and stores it in RAM13.

[0014]

Hereinafter, operation is explained based on the flow chart of Drawing 3. In Step 51, start bit S1 (1 bit), stop bit S2 (2 bits), and parity check bit P (1 bit) that is bit error detection information are added to 7 bits of character data parts, and the reading number of bits as the predetermined number of bits of unit information is set to 11. A timing reading data storage place which is data of the first time which detects falling of start signal S1 in Step 52, and when falling of start signal S1 is detected is specified (Step 53), After setting number of times N of a sampling per bit (Step 54), only sampling interval time deltat carries out waiting for time (Step 55).

[0015]

Next, data is read in the timing of t1A shown in Drawing 2 (b), and it stores in RAM13 (Step 56). Next, data is read to the timing t-hour after [ t1B ] delta, and it stores in RAM13. The data to the timing of repetition t1N is read N times, and the same sampling operation is stored in RAM13 (Step 55~58). the read data is shown in Drawing 4 -- as -- receiving bit sequence 31~3N -- the 1st bit is memorized as S1. An end of the sampling (N times) of the 1st bit will advance one calculation of the number of bits (Step 59) (Step 58) All the bits which constitute unit information are read repeatedly (Step 60) until reading for 11 bits is completed, and receiving bit sequence 31~3N of bit length 11 shown in Drawing (a) (c) 3 ~ as memory data of RAM13 is generated (repetition of Step 53~60).

[0016]

Next, it goes into logic of-corrigenda judgment operation of receiving bit sequence 31~3N. If a start, a stop bit check, and a parity check are performed (Step 61) and receiving bit sequence 31 which is A timing reading data is judged with it being right, receiving bit sequence 31 will be stored in RAM13 (Step 66), and reception will be ended. the case where there is an error by the judgment (Step 61) of receiving bit sequence 31 of A timing reading data -- the judgment of receiving bit sequence 32 of B timing reading data -- the judgment of receiving bit sequence 3N of ...... and N timing reading data is operated (Step 62).

[0017]

When the judgment (Step 62) of receiving bit sequence 3N of N timing reading data also has an error, a receiving bit sequence is generated by the majority for every bit (Step 63), The of-corrigenda judging of this majority generation bit sequence is carried out (Step 65), if right, data is stored in RAM13 (Step 66), if it is an error, an error set will be performed (Step 67) and reception operation will be ended. That is, start bit 41-1 (S1) is generated by the majority of 31-1~3N-1, and the following bit 41-2 is generated by the majority of 31-2~3N-2. Thus, receiving bit sequence 41 generated by majority is shown in Drawing 4 (c).

[0018]

Although what stores the sampling data for every bit in the storing place for receiving data row 31~3N one by one, goes in the one above-mentioned example, and generates receiving bit sequence 31~3N was shown, All the sampling data are memorized collectively, and afterwards, the data corresponding to each bit may be extracted from these sampling data, and it may combine, and may generate a receiving bit sequence. It may be [ a 1st / the / of bit / 1st / sampling data, the 5th / bit / 2nd /, and bit / 3rd ] arbitrary the sampling data of what position in each bit are extracted and combined so that No. 2 may be made into one receiving bit sequence combining the thing of ......, for example.

[0019]

Example 2. Drawing 5 is a flow chart which shows operation of other examples of this invention. Although the composition of a device is the same as that of one example of Drawing 1, it differs in the contents of the program which CPU11 is made to run, constitutes 1 block in every [ other than the check for every character shown in Drawing 3 ] 1 word (two or more characters), and weights the check for every block. Hereinafter, the flow chart of Drawing 5 explains operation. The same numerals are attached about the step which performs the same operation as the flow chart shown in Drawing 3, and explanation is omitted.

[0020]

In Step 71, the bit of block check bit C which is block error detection information, a block, and bit S3 is added to the number M of characters of 1 word which is the block as one transmission unit as one character, and M+1 receiving character is set up. Next, the receiving bit sequence for every character is generated the same with Step 51~60 having been shown in the flow chart of Drawing 3. An end of bit reading for one character will advance calculation of a receiving character one (Step 72) (Step 60) It returns to Step 51 again and bit reading of the following character is performed, and Step 51~73 is repeated until it reads M+1 character equivalent to 1 word (it receives), Drawing 6 (a) Receiving block bit sequence 81~8N which consists of a bit sequence for M+1 character equivalent to 1 word shown in ~ (c) is generated.

[0021]

If reception of the number of characters which is equivalent to 1 word as mentioned above is finished, A, B, and ... judging first whether the bit data read into N timing are right based on parity check bit P for every character Finally based on block check bit C, a 1-word logic judgment of corrigenda is made in order (Steps 74 and 75), and if right, a receiving block bit sequence is stored in RAM13 (Step 66). When all of N receiving block bit sequences which sampled to A~N timing are errors (Step 75), a bit is determined by majority for every bit, and a receiving block sequence is generated (Step 76), A judgment of this receiving block bit sequence of corrigenda is made (Step 77), and to a memory, if right, if it is storing (Step 66) and an error, error information will be set and it will end (Step 67).

[0022]

Although the example of Drawing 5 showed the example which receives 1 word of wording of a telegram which can be divided into the character unit which has a start bit and a stop bit as one block, it has the same effect, when starting reception by synchronized signals other than this wording of a telegram and number[ of regulations ]-receiving the continuous bit.

[0023]

The number of bits of the data (character) portion in each example of Drawing 4 and Drawing 6, Start bit S1, stop bit S2, parity check bit P Bit length composition, such as block check bit C, may be arbitrarily constituted so that the object of this invention may be met, and even if it uses constant mark numerals, a Hamming code, etc. instead of parity check bit P and block check bit C, it has the same effect.

[0024]

[Effect of the Invention]

According to the invention concerning Claim 1, since a plurality of receiving bit sequences are generated, a judgment of corrigenda is made for every bit sequence and it enabled it to choose the right thing, the quality of receiving information can be improved.

[0025]

According to the invention concerning Claim 2, since block check information is added for every number of predetermined sequences of a receiving bit sequence in addition to the judgment of corrigenda for every receiving bit sequence concerning Claim 1 and it was made to make a judgment of corrigenda also per block, the quality of receiving information can be improved further.

[Brief Description of the Drawings]

[Drawing 1]

It is a block diagram showing the composition of one example of this invention.

[Drawing 2]

It is a time chart explaining operation of one example of this invention.

[Drawing 3]

It is a flow chart explaining operation of one example of this invention.

[Drawing 4]

It is a memory figure explaining operation of one example of this invention.

[Drawing 5]

It is a flow chart explaining operation of other examples of this invention.

[Drawing 6]

It is a memory figure explaining operation of other examples of this invention.

[Drawing 7]

It is a block diagram showing the composition of the conventional data receiver.

[Drawing 8]

It is a time chart explaining operation of the conventional data receiver.

[Description of Notations]

1 Input Terminal 2 Serial Signal Input Circuit 11 CPU 12 ROM 13 RAM