Autoadaptive amplitude equalizing apparatus for digital microwave links
Abstract
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Expired 4 February 2004, 22.6 years ago.
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4 claims: 4 independent, 0 dependent
- 1【特許請求の範囲】 1 直列に接続された、中間周波数信号入力と入力信号の振幅ひずみを補正する遅延線フイルタとこの遅延線フイルタを制御する第1装置とを有し、この第1制御装置は、並列に接続され且つ受信中間周波数信号の中心周波数に対して対称的な2つの周波数を夫々中心とする2つの周波数選択検出器と、この2つの周波数選択検出器の出力信号の差を表わす信号を遅延線フイルタに供給する増幅器とより成るデジタルラジオリンクの自動適応振幅等化装置において、遅延線フイルタは、2つの段を有し、中間周波数信号入力に対し、Kを正の整数としFcを中間周波数信号の中心周波数とした場合に(2K-1)/4Fcに等しい遅れTを与える遅延回路と、入力がこの遅延回路の出力と中間周波数信号の入力に夫々接続された第1および第2増倍回路と、この第1および第2増倍回路の出力に接続された加算器とより成り、前記の第1増倍回路は増幅器で、その利得の自動制御は、第1制御装置の増幅器の出力信号により行われることを特徴とするデジタルラジオリンクの自動適応振幅等化装置。
- 22 第1増倍回路は、第1定利得増幅器と第1デジタル制御減衰器の直列接続より成り、この減衰器の入力は、第1制御装置の増幅器の出力に接続された第1零比較器で制御される第1アツプ/ダウンカウンタの各計数出力に接続された特許請求の範囲第1項記載の装置。
- 33 遅延線フイルタの加算器の出力に接続され、直列な整流器と積分器より成るこのフイルタの第2制御装置を有し、前記の積分器の出力信号は、自動利得制御信号として、第2増倍回路を形成する増幅回路に加えられる特許請求の範囲第1項または第2項記載の装置。
- 44 第2増倍回路は第2定利得増幅器と第2デジタル制御減衰器の直列接続より成り、装置は、遅延線フイルタの加算器の出力に接続され、整流器と積分器と第2零比較器と第2アツプ/ダウンカウンタとの直列接続より成る前記フイルタの第2制御装置を有し、前記カウンタの計数出力は第2デジタル制御減衰器の夫々の制御入力に接続された特許請求の範囲第1項または第2項記載の装置。
Independent claims4
4 paragraphs, as filed
[Detailed Description of the Invention]
The present invention relates to the automatic adaptation amplitude equalization device of a digital radio link. It sets to a very sensitive digital radio link to selective fading, If selective fading does not break out in the zone of a transmission signal by making especially firm reproduction perform notably from a carrier's, and extending the eye opening (eye-opening) of an abnormal-conditions signal, intermediate frequency amplitude equalization improves performance remarkably. The equalization apparatus of 1981 [ three ] "revue Technique Thompson CSF" ("Revue Technigue Thomson-CSF") which attains such an object will be No. 1 per month, Paper "Egarizi yell by 135 - 138-page Py Gerard (P. germanium'rard) of 13 volumes Auto adapter Tape daughter chewed pool Hue Saw Erzwien Numeric" ("Egaliseur) autoadaptatif d'amplitude It is indicated to pour faisceaux hertziens nume'riques." The object of the present invention has the performance which is equal to a thing given [ above-mentioned ] in a paper, and there is in moreover obtaining an easy equalization apparatus rather than it. According to the present invention, it has the 1st device that controls the intermediate frequency signal input and the delay line filter which amends the amplitude distortion of an input signal which were connected in series, and this delay line filter, Two frequency-selective detectors which this 1st control device is connected in parallel, and center on two symmetrical frequency to the center frequency of a received intermediate frequency signal, respectively, In the automatic adaptation amplitude equalization device of the digital radio link which comprises the amplifier which supplies the signal showing the difference of the output signal of these two frequency-selective detectors to a delay line filter, a delay line filter has two stages, K is made into a positive integer to an intermediate frequency signal input, and it is F.<sub>c</sub>When it is considered as the center frequency of an intermediate frequency signal, it is (2K-1) / 4F.<sub>c</sub>The delay circuit which is alike and gives equal delay T, and the 1st and 2nd Multiplication circuit where the input was connected to the output of this delay circuit, and the input of an output intermediate frequency signal, respectively, The adding machine connected to the output of this 1st and 2nd Multiplication circuit is comprised, the above-mentioned 1st Multiplication circuit is an amplifier, and the automatic control of that profit is performed by the output signal of the 1st control device. the 1st Up / down counter by which the 1st Multiplication circuit comprises the series connection of the 1st Sadatoshi profitable amplifier and the 1st digital control attenuation machine, and the input of this attenuation machine is controlled by modification of the present invention with the 1st zero comparison machine connected to the output of the amplifier of the 1st control device -- each -- calculation -- it is connected to an output. The example of a drawing explains the present invention in detail below. The amplification equalization apparatus of Drawing 1 is a two-step delay line filter type thing, and has a delay line filter for amending intermediate frequency signal input 10 and the amplitude distortion of an input signal, and a control device of this filter. The above-mentioned filter makes K a positive integer, and is F.<sub>c</sub>When it is considered as the center frequency of an intermediate frequency signal, it is (2K-1) / 4F.<sub>c</sub>Delay circuit 20 which is alike and gives equal delay T, and two Multiplication circuits 30 and 40 where the input was connected to delay circuit 20 and signal input 10, and the output was connected to two inputs of adding machine 50, respectively are comprised. Control of a delay line filter is performed by two frequency-selective detectors which are connected in parallel and center on two symmetrical frequency to the center frequency of a received signal, respectively. If it says in detail, the above-mentioned control device has narrow bandwidth, and it is center frequency F of an intermediate frequency signal.<sub>c</sub>It is alike, it receives and they are two symmetrical frequency F.<sub>1</sub>F<sub>2</sub>each -- it has two zone filters 110 and 120 made into a center. Two rectifiers 130 and 140 and two integration machines 150 and 160 are connected to the above-mentioned filters 110 and 120 which were connected to the output of adding machine 50, and were connected to two different parallel channels at series, respectively, and it is F about a center by outputs, such as it.<sub>1</sub>And F<sub>2</sub>The electric power of a signal is obtained in each two zone to carry out. The output of integration machines 150 and 160 is applied to each input of differential amplifier 170, this amplifier detects the electric power difference of the two above-mentioned frequency bands, and that output signal is applied to the 1st Multiplication circuit 30 formed as a variable profit analog amplifier here as an automatic-gain-control signal. the example of Drawing 2 -- the 1st Multiplication circuit -- already -- Ya -- not a single variable gain amplifier but Sadatoshi profitable amplifier 31, and calculation -- being formed by the series circuit of control attenuation machine 32 -- the control input of this circuit, each calculation of Up / down counter 190 controlled by zero comparison machine 180 connected to the output of differential amplifier 170 -- it is connected to the output. The above-mentioned comparison machine 180 will receive clock signal H (T') at a rate decided by periodic T' (if this rate is necessary). Since it follows well by channel change, even if it changes according to the increase speed or reduction speed of channel change, good Up / down counter 190 are delayed in consideration of the stabilization time of a comparison machine in delay circuit 200, and acquires and kicks the above-mentioned clock signal. Unlike the equalization apparatus given [ above-mentioned ] in a paper which comprises the delay line filter which has an alignment phase to all the frequency, the equalization apparatus with the structure explained in the two above-mentioned examples does not have fixed group delay time. This group delay time D (omega) is denoted by the following formula in practice. D(omega) =bT(b+acosomegaT)/a<sup>2</sup>+b<sup>2</sup>+2abcosomegaT In this case, it is the delay by which a and b are added to the multiplication factor of a delay line filter, and T is added to the input signal of that filter, and is change of the suddenly of D (omega), It is observed near frequency like omega=pi (2K-1)/T, and K is a positive integer here (in the case of the delay line filter of an equalization apparatus given [ above-mentioned ] in a paper, refer to the 3rd figure which showed the same curve as a dashed line again as a line which continued the curve to change of D (omega)). However, if the narrow zone centering on such frequency corresponding to omega=pi/T, omega=3 pi/T, etc. is removed, group delay time is constant in practice. The curve (refer to the 4th figure) (|H (omega)) which expresses an electric power transfer operation of the device of the present invention with careful attention to this observation<sup>2</sup>|=a<sup>2</sup>+b<sup>2</sup>+it expresses with 2abcosomegaT -- having -- |H(omega) | corresponding to frequency [ like omega=pi (2K-1) / 2K (K is a positive integer) ] whose frequency of a carrier is when it also cares about resembling extremely the electric power transfer operation relevant to an equalization apparatus given [ above-mentioned ] in a paper<sup>2</sup>of pivoting point (pivoting points) P<sub>1</sub>,P<sub>2</sub>When in agreement with one of the And so on, the adaptive equalization device of Drawings 1 or 2 does not change the phase response of a channel (change of the suddenly of group delay time maintained outside a use zone). from the narrow zone which such change produces, so that a carrier approaches such a Pipotting point -- many -- him -- that is so right increasingly that it is in the few he equal distance -- since structure is easy, an equalization apparatus given [ above-mentioned ] in a paper can be replaced for advantageous. The present invention is not limited to the above example and it is not necessary to say that there is other change and there is in the range which does not deviate from the gist of the present invention based on examples, such as this. It may be made for especially the device of the present invention to have two incomes with another device of a delay line filter for the object of automatic gain control. This control device shown in Drawing 5 is located also in the output of adding machine 50 of a delay line filter, and has rectifier 230 and integration machine 250 which were arranged in series, and the output signal of this integration machine is applied to 2nd Multiplication circuit 40. The variable profit analog amplifier with which that automatic-gain-control signal is formed of the output signal from integration machine 250 in this case may be sufficient as this circuit 40, Or as mentioned above again, it forms from the series circuit of a Sadatoshi profitable amplifier and a digital control attenuation machine, and it may be made to be controlled by the output of integration (receiving above-mentioned and clock signal of the same kind) machine 250 by the zero comparison machine, and Up / down counter.
[Brief Description of the Drawings]
The phase assistant control device with which the block diagram and Drawings 3 and 4 in which Drawings 1 and 2 show the example from which the equalization apparatus of the present invention differs can have two incomes with the curve of the group delay time of the equalization apparatus of the present invention and the curve of an electric power transfer operation, and Drawing 5 can have two incomes with the equalization apparatus of the present invention is shown. 20,200 ...... A delay circuit, 30, 40 ...... A Multiplication circuit, 50 [ ...... An integration machine 170 / ...... A differential amplifier, 180 / ...... A zero comparison machine, 190 / ...... Up / down counter. ] ...... An adding machine, 110,140 ...... A zone filter, 130,140 ...... A rectifier, 150,160
11 members in 7 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 8301867 | France | A | |
| 8301867 | – | – | – |
| FR19830001867 | – | – | – |
Members11
| Document | Office | Kind | |
|---|---|---|---|
| FR2540692A1 | France | A1 | |
| AU2422184A | Australia | A | |
| JPS59147548A | Japan | A | |
| EP0116990A1 | European Patent Office (EPO) | A1 | |
| FR2540692B1 | France | B1 | |
| US4559635A | United States of America | A | |
| CA1208716A | Canada | A | |
| EP0116990B1 | European Patent Office (EPO) | B1 | |
| DE3461976D1 | Germany | D1 | |
| AU563129B2 | Australia | B2 | |
| JPH0349218B2This record | Japan | B2 |
Numbers
- Publication, DOCDB
- H0349218
- Publication, EPODOC
- JPH0349218B
- Application
- 59017680
- Application, DOCDB
- 1768084
- Application, EPODOC
- JP19840017680
Classification
- CPC, 1
- H04B7/015
- IPC, 4
- H03H21 00
- H04B3 04
- H04B7 005
- H04B7 015