Modulating and demodulating apparatus and signal processing method of the same

[Detailed Description of the Invention]

A. Field of the Invention The present invention relates to the minute tap interval equalizer (fractional tap-spacing equalizer:FSE) from which the tap interval was chosen below as the frequency of the data signal by which a sample is carried out with the degree of fixed-speed twice the reciprocal of the highest. It is related with a system with the low drift continuous between the local sauce of sample timing, and the sign received after training in detail. B. Conventional technology and its problem There are the following as a publicly known adaptation equalizer with a minute tap interval. : (1)G.l]ngerboeck.Fractional Tap-Spacing Equalizers And Consequences For Clock Reecoyery In Date Modems ,IEEE Trans. On CoIImunications. Vol. Cow. 24No.8, August .1976, Pages 856-864; (2) United States patent No. 4.343.759: Training processing before data communications with this actual The optimal tap coefficient is established in the optimal tap location. The tap location of a coefficient is fixed after training, and an actual data sign is received. In order that a coefficient value may make the minimum the square average error under output of an equalizer in this mode as compared with an ideal sign level, it is carried out m ready immediately after Acceptance F of each sign. The synchronization with a sampling process and the source of transmission is aimed at, and sample timing is also adjusted between reception after training in order to make generating of the error in a receiving process the minimum thing. The Osh Leh evening of comparatively expensive many is needed for adjustment of sample timing. Many Osh Leh evenings are needed in the case of transmission especially with the high Pau speed. A very difficult communication situation also has 4A Adjustment of sample timing. (Refer to simultaneous U.S. Serial Number 227832) The details are given below. C. The outline of an invention In order to compensate the continuous low drift between the local sauce of sample timing described above in the present invention, and the sign received after training, an equalization coefficient is monitored periodically, and in order to correct the recognized deviation, it minute-tap-Distance-w/i-excels and rotates (rotation). In itself [ this / rotation ], the phase of the sum of the calculated product relevant to equalization is shifted, and it acts so that the error which is not preferred may be led to equalization data. In order to avoid this, the calculation processing following each rotation has timing readjusted according to the flow of the new data sample which enters a calculation network. The distortion effect accompanying rotation is made with the minimum by this. The right and left tap rotation generate a respectively different distortion effect. This is based on whether the adjustment [ which ] in a relative calculation phase is introduced now. The calculation following right rotation / shift delays a phase, and the calculation following left rotation / shift makes it follow a phase. Other reference articles related to the present invention are enumerated below. 3) Covan C.F.N.. Grant P. M. "191 154 Rabiner L.R., Gold B" Theory And Application of [ Adaptive Ftlters''.Prentice-HalI Inc .. ] [ .. ] Digital Signal Processtng".Prentice-Hall,1975 5) }Iartman P.,Bynam B.."Adaptive Equallzation For Digital Microwave Radio Systems''.IEEE International Conference on Communications.Paper 8.5.19JllO6 Taylor N.G.+"Adapt[ve Antennas'', SpecialIssue, Proceeding of IEE Vol 130 No 1, pp l-55.Jan.1983 7) Makhoul J..Vtshvanathan.R .. "Adaptive Lattice Methods For Linear PredIctLon''.Proceedings of ICASSP 1987,pp83-868) Bolt L.,Stueflotten S-+''A Nev Digital Echo Canceler For Two Wire Subscriber Lines ,[EEE Trans. COM-29.No 1),pp 1573-158L November 1981 9) Haykin S., Cadzov J.A., "Spectral EsttmatiOn''.Spec[al Issue.Proceedtng ofIEE.Vol 70, No 9, Sept 1982 10) Ungerboeck G.,"Adaptive Equalization Techniques In Voice-band Data Transmission''.Proceedings of Intel Conf on Communications, June 1980 buttons pp and 8.4.1-8.4.6D. example With reference to Drawing 1, it is combined with timing circuit 2 and crystal control oscillator 1 supplies a plurality of fixed-speed degree clocks 3-5 containing sample loading clock 4 ("Lo cak") about adaptation equalization processing. Data signal 8 of analog format is A/D. A sample is carried out all over circuit (analog-to-digital conversion) 9 by the receiving clock ("RcvClk") signal of the degree of fixed-speed transmitted to control human power 10 in A/D circuit 9 from output 3 of timing circuit 2. Output 1 of A/D circuit 9 showing a quantization Recording sample is supplied to processing circuit (proc) 12 realizable by a micro program-ized digital data processor (refer to above-mentioned U.S. Serial Number 227832). As number l3 shows, processing 11 various digital filtering about a data sample, equalization, a recovery, etc. perform 11, and circuit 12 pulls out the digital data which expresses a transmission character or other signs directly. The signal showing such data is a sake of data processing. USART It can transmit to a digital computer system via circuit (Universal Synchronous-Asynchronous Receive Transmit== universal and synchronous 1 asynchronous reception transmission) 14. Especially an important thing is equalization processing here. The functional element which is needed for the processing in circuit 12 includes data delay network 16, calculation network 17, and coefficient shift / rotation (rotation) network 18, as number 15 is shown. The data sample in network 16 is supplied to calculation network 17, in order to multiply with the coefficient of the correspondence position in network 18. A multiplication result (product) is added so that output sample Yn may be raw-Commandment(ed). a slicer element (not shown) -- it judges how much the deviation from an ideal sign level has appeared in the value of Yn, and renewal of a coefficient value required in order to correct this deviation is performed. The updated coefficient value is calculated so that an average error may be made into the minimum the square to an ideal sign level according to conventional technology (refer to above-mentioned reference literature (1). (2)). Only two positions are shifted to the right and, as for the data after calculation of each Yn, and in network 16, a new data sample is shifted to two> positions of Left end of the empty of network 16 via gate circuit 19. Ld by which loading is transmitted to gate control human power 20 from timer port 4 (Fig.1) It is controlled by a Clk signal. Usual [ which is not related to the important section of the present invention ] should training hand M Come, and boil the values and those relative tap locations of a coefficient in circuit 18 is determined first. Typically, the most important coefficient value (mostsignificant coefficient) determined in training procedure exists within a 1-tap interval from the standard tap location as which a center tap may be sufficient, or there (refer to U.S. Pat. No. 4,343.759). In the processing described below, a primary importance coefficient is symmetrically positioned about a center tap, and actual data is assumed to supply the digital data sample by which was received and pretreated and the filter was carried out to gate circuit l9. After calculation of the sum (Yn) of a product and renewal of a coefficient are performed, respectively, the coefficient in coefficient shift / rotation network 18 is monitored by coefficient monitor circuit 21, but it is for detecting whether the position of a primary importance coefficient has shifted this to a standard / center tap location. The sign and Ld which are transmitted Since both are having timing adjusted by the crystal control Osh Leh evening as for Clk, this shift takes place slowly. Therefore, it is understood that the drift of the 1-tap space to the right or the left of a center and change of sufficient coefficient value to require updating operation also take place only after many cycles of Yn calculation. Compensation the right or a shift to the left is performed, and a shift in the optimal coefficient position is Rumi so that it may be a portion corrected in relation to the present invention and a primary importance coefficient may be re-aligned with a standard / center tap for this reason. The form of rotation in the meaning of moving the leftmost coefficient to the rightmost position, or making the leftmost position move the rightmost coefficient after a shift to the right after a shift to the left may be sufficient as this re-alignment shift. Or when very small to #, a zero value is shifted to an empty position, and a coefficient value is a vine. Therefore, if coefficient monitor circuit 21 detects the irregular sequence of the coefficient to the left-hand side of a center tap, a * * right rotation * control signal will be supplied to signal way 22, and only 1 tap location will carry out the shift to the right of the coefficient in coefficient shift / rotation (rotation) network 18. On the other hand, when coefficient monitor circuit 21 detects the irregular sequence of the coefficient to the right-hand side of a center tap, a "left rotation ' * control signal is supplied to signal way 23, and only 1 tap location is made to left-He shift the coefficient in coefficient shift / rotation (rotation) network 18. If it has aligned correctly in the coefficient, *-'-Shibuto-less * control signal will be supplied to {No. 3 way 24. The output of 2 l. of coefficient monitor circuits is sent to logic circuit 25, and the timing of the equalization calculation processing performed by a means to mention below here is determined. * * right rotation -- " -- and only *-*-shift-less ' * output is used for this determination in 1 Contact. However, since that * right rotation * and *-*-shift-less *' output do not exist shows that a * left rotation * * signal exists tacitly, this signal participates in this determination indirectly. The *' calculation permission * output of output '#I26 of calculation control logic 25 is supplied to input 27 of calculation circuit 17, and controls the cycle which calculates the sum of a next product. Drawing 2 shows the logic mechanism in which the Loading exception of the irregular sequence from the center of the coefficient in coefficient monitor circuit 21 is performed, and has circuit PL.P2 which compares the value of each coefficient value raise in basic wages, and passes the larger one of raise in basic wages as an output to a way next time, .., and Pm... P1 receives leftmost coefficient values C1 and C2, and P2 thinks 03 to be an output (CI.C2 is large -- it crawls) of P1. P1 to Pm-2 receives the coefficient value on the left-hand side of a center tap, and they are Pm-1, Pm, and p m+. 1 s receives the coefficient value on the right-hand side of a center. Comparison circuit 30 compares three states of coefficient value a+b * c which show the output of Pm-2, Cm, and Pm-1 respectively. When the coefficient is positioned correctly and the center gap is not caused, Cm must be size from the coefficient of all the lefts and rights (for example, b is size from a and C). At this time, output 31 of comparison circuit 30 shows that rotation of *-*-shift-less "and a coefficient tap is unnecessary. However, when the coefficient value has caused the center gap to left-hand side, a becomes large from b.c, * * right rotation * * output 32 of comparison circuit 30 arises, and it is shown that the 1-tap distance to the right needs to be rotation amended. When an irregular sequence is on the right of a center similarly, C is size from b.a. It is shown that output 33[*" left rotation * is required for 1-tap distance rotation amendment to the left. Three coefficients C m which have these coefficients in the center if it is once positioned correctly and a center gap is lost l * C m+C m+ It is maintained only by monitoring 1. Thus, between the processings under a state in which it does not train, coefficient monitor circuit 21 excels comparison circuit 30, and it usually only Or motion. such tap rotation without other operations -- the -- distortion is brought about to calculation of the sum of a product so that I may be understood from the timing diagram showing inA [ 4 ] figure. the --A [ 4 ] figure shows the relative timing of the operation which loads new data to network 16 (Drawing 1) when, the coefficient has aligned correctly to the center tap location, and peace calculation operation of the product in circuit 17 (Drawing 1). Whenever [ from which two new data is shifted to a network in this state ] (2 Ld Clk pulse one calculation is performed under control of the calculation permissible signal head Calculation control signal respectively shown by numbers 35 and 36.]) It is premised on T/2 of tap spaces as well as this. T is the Pau space between two signs transmitted continuously here. In other spaces, the ratio from which loading/calculation cycle differs is needed. the [ next, ] -- with reference toB [ 4 ] figure, operation in case right rotation processing is performed is described. number 37 shows the determination of the right rotation -- as -- * calculation permission * * -- the near Final binding part of the period of active or a high -- 1 -- Te -- it is divided. The active state of the next * * calculation permission * is assumed that generating was permitted in the usual phase position 38. Under this state, a coefficient is shifted to the right only a space 1 tap, Since calculation should be performed after data is shifted to 2 space Take Right, the data used by this calculation should become that to which only 1st place M was displaced on the right to the position which it had to the coefficient at the time of previous calculation. This Fruitfulness and an equalization output should occur in the middle of the sign peak which number 37 precedes, and the following sign peak (a sign peak occurs at the Pau speed and it generates once every two shifts of the data to a coefficient in this example). Generally, when calculated among both peaks, an equalization output serves as an invalid value or a low transitional level, and the result which cannot be predicted as a result of mistaking will be given. therefore, number 38.39 shows -- as -- this -- * * -- it is avoidable by excelling during the l load and delaying following calculation permission * *. That is, about data, after a coefficient shifts to 1 space right, when only three spaces permit a shift on the right, the phase Nu] displacement of data to the coefficient in the next calculation becomes the usual thing shifted to the right two times. the same -- the -- a phenomenon when the left rotation of a tap is not corrected with reference toC [ 4 ] figure is explained. While data goes to the right 1 tap after this rotation shown by number 40, a coefficient is 1 position Only to the left, Since it shifts, as for data, only two positions will be displaced to the right to a coefficient, and data and a coefficient will be placed on the proper position for the next calculation in the usual order of 2 loading per 1 calculation by this. Thus, the present calculation will follow previous calculation immediately by advancing following * * calculation permission * *, as shown in number 41. The data loss which takes place when it appears by this, and calculation does not move forward and it approves in loading of additional data before the present calculation is avoidable. If required, it is also possible to perform the coefficient shift of two or more tap locations by extending the above-mentioned technique. Thus, ' * calculation permission * * is delayed during the 1 load for every shift to the right of 1 tap location, and advancing * calculation permission * during the 1 load for every shift to the left of 1 tap location is performed. The constitutional diagram showing the logic which moves forward * * calculation permission * after delay of * calculation permission * * after right tap team Translate or the left rotation in Drawing 3 and in which showing the sequence of the processing state is shown in Drawing 5. Although the individual logic element (AND, OR, flip-flop) is shown here in order to understand easily, * The function to perform a function, calculation of Yn, a monitor / updating / rotation of a coefficient, etc. which generates calculation permission * * can be efficiently processed by the microprocessor which operates under control of a micro program command. In Drawing 3, it is Ld. Clk is supplied to the * * clock * * (CLK) input of D type flip prop 60.61, and, thereby, D input state is transmitted to each output (60Q0, 61 Ql(s)) in each flip flop. The state (States) where it is transmitted is decided by the state of AND circuits 62 and 63, NAND circuit 64, AND circuit 65, and NOR circuit 67. When QO and Q1 both are active, "* calculation permission * * of AND circuit 62 becomes active. * When active, as for NAND circuit 64 and AND circuit 65, a condition is attached to * calculation permission * * via circuit 66. fll! If tap rotation is not demanded when the calculation result of Yn of In comes out, *-*-shift-less "input of AND circuit 65 becomes active, validation of this circuit is completed, and an invalid state is transmitted to flip prop 60 via NOR circuit 67. Thereby, it is the next Ld. QO A drop at Clk time. since this repeals AND time g862 -- * * calculation permission * -- " -- it is not outputted but continuation of the next calculation is stopped. This also repeals AND circuit 65 again, raises the output of NOR circuit 67, and also attaches a condition to NAND circuit 64 partially, and raises an output (> which is because a * * right rotation ' * signal is also un-active at this time.). Since a condition is attached to D human power of both flip flops 60.61, this is the next Ld. It becomes again active [ QO and Q1 ] at the time of Clk. In this way, * calculation permission * * signals are two Ld(s) so that it may be needed for the usual Ynt+ Calculation. It will be generated by No. 2 Huge of a Clk data shift. * When * * right rotation * becomes active after * calculation permission *, 1 human power of NAND circuit 64 falls, send an invalid state to flip flop 61, and Q1 is the next Ld. It acts so that it may drop in the case of Clk. QO is maintaining the high state -- an extra and state [ where it does not calculate ] * *01 -- " -- it starts. In this state, the output of AND circuit 63 is a high and sends an invalid input to flip flop 60 via NOR circuit 67. Although NAND circuit 64 is cancelled and QO drops it with the time of the next LdClk by this, it serves as a high again by Q1, and makes the usual state where it does not calculate start simultaneously. At this time, D input to both flip flops 60.61 becomes active, therefore is the next Ld. At the time of Clk, QO.Q1 becomes a high and it permits other Yn calculations. Since this calculation follows one additional data load shift action, while a coefficient is shifted to the right only one position, data is efficiently shifted to the right only M about 3 tap. That is, as for data, 2 position Only displacement of usual is carried out to a coefficient. * * right rotation * * also has no * * shift -- " -- it is not, either (namely, * * left rotation * *) -- if a thing follows ' * calculation permission * *, a condition will be immediately attached to D input of flip flop 60.61 The next Ld QO.Q1 both maintain a high state at the time of Clk, and calculation permission maintains an active state. Thus, other Yn calculations are performed rather than what kind of other data shifts before. That is, data carries out 1 position Only shift on the right, and after a coefficient excels in the left 1 tap and shifts to it, the relative shift of two positions required as a result will be reflected one. The ellipse of ' * load & calculation ' * (state 1) which is the constitutional diagram in which Drawing 5 showed the state sequence of the logic mechanism of Drawing 3 on the high level logically is linked to usual '' data load processing * * (state 10), when "-shift-less * follows LdClk. State 10 is the next Ld. It has a link which returns to state l1 at the time of Clk, and two data samples are shifted by this all over a calculation network for every usual (a coefficient is not shifted) loading and calculation operation. State 1 is Ld. When Clk and * * right rotation * arises, it links to * * extra load processing * * (state 01). On the other hand, state 01 is the next Ld. It links to state 10 at the time of Clk. A state f@10 is the next Ld. It links to state 1 at the time of Clk. Thus, before the next Yn calculation, 3 data sample is shifted all over a calculation network for every right tap rotation of a coefficient. 2 position shift of data to a coefficient is Or(ed) now. Finally, state 1 is linked to itself, when * * left rotation ' * follows Yn calculation. Although the specific example has been used for explanation of the present invention, it is clear that various modes are realized in the range of the concept of the present invention. For example, the present invention is applicable to the passband which has a complex number or a coefficient of real number form, and a data sample, or a base band equalizer. The number of taps in a calculation network, a tap interval, and the sampling speed can consider various modification. The position which shifted from the center position also in the symmetrical center position according to the characteristic of the communication channel which is an object by which equalization is carried out may be sufficient as the standard tap used as the target for a coefficient to be shifted correctly. A means to determine the case where a shift is needed may differ from what was mentioned above (reference literature 1 is showing some of means which determine the position of the sign peak in an equalizer). Coefficient monitoring for a potential shift is not required at each [ by which a coefficient is updated ] time, and does not need to perform a certain thing of these functions irrespective of the contents of Drawing 4 at the time of the sample/loading of a sign. It is also possible to have a lattice and an inductive filter all over a delay network with a tap, or to connect a FIR filter suitably. The concept of the present invention is applicable also to an adaptation lattice and an inductive filter using an easy conversion method (the inductive filter device which uses a delay circuit with a tap for 40~43 pages of above-mentioned reference literature 3 shown). The conversion process between a lattice and delay circuit filter structure with a multiplex tap is shown in 93~98 pages of reference literature 4. Although the adaptation equalizer in modem reception of a voice band was shown in the example, it is applicable to various apparatus if needed. For example, the relative shift of the information flow of the present invention and calculation operation are applied to reference literature 10, and other examples of the vine adaptation filter are shown. E. EFFECT OF THE INVENTION if the present invention is followed like Above -- efficient equalization processing -- Perfection -- having .

[Brief Description of the Drawings]

Drawing 1 is a lineblock diagram showing the adaptation equalizer in the modem which materialized the present invention, The lineblock diagram in which Drawing 2 shows the details of the coefficient monitor logic in the 1st figure, and Drawing 3 are logic lineblock diagrams for adjusting the relative timing of the equalization calculation which amends the distortion effect of tap rotation, the -- the [ 4 8 figure thru/or ] -- the timing diagram in whichC [ 4 ] figure shows the timing of equalization calculation processing in coefficient tap rotation of rotation nothing, the right rotation, and the left rotation, respectively, and Drawing 5 -- the -- the [ 4 8 figure thru/or ] -- it is a constitutional diagram showing the logic composition in Drawing 3 for providing the state by which it is shown inc [ 4 ] figure with a constitutional diagram. 1- . Oscillator 2.1 Timing Circuit 9 Person Output Circuit 16 and Delay Network 17 1 Calculation Network 18 -. Coefficient Shift / Rotation Network 21 -. and Coefficient Monitor Circuit 25 1 Coefficient Control Logic