Control adapter for input/output device

[Detailed Description of the Invention]

[Industrial Application] The present invention is used for hardware data transfer. The present invention relates to the adapter for input/output device control which performs data transfer. [Summary of the Invention] In the present invention, in an input/output device control adapter which performs data transfer with a hardware data transfer method, when data transfer has been terminated with data length shorter than data length beforehand set up from the input/output device side, directions which are final data are given to a bus controlling part synchronizing with final data. Therefore, the necessity of performing compulsory close processing to a bus controlling part and a hardware transmission control circuit by a microprocessor is abolished, and it is made to lessen an increase in A \-Dwarf. [Description of the Prior Art] The crowd power adapter which controls an input/output device is 71-Dwarf data transfer (not being a method which transmits data with firmware). - 1-Dwarf controls until it will end, if degree data transfer is started, When holding the data transfer method which does not need control of firmware in the meantime, it is common to set up beforehand the data length transmitted to the /XI A control part and input/output device of an adapter, and to start data transfer after that. In this case, a bus controlling part and a crowd force control device recognize the end of data transfer in the place which subtracted the given data length with transmission execution of data and where the remainder of data length became 0, and start end processing. For example, a microprocessor is in an adapter, if a microprocessor recognizes the end signal of data transfer from an input/output device in being a method which controls an input/output device, post-processing will be performed and the end of data transfer will be notified to an upper device. A microprocessor will deter operation of the hardware which clears the register which shows starting of data transfer promptly, and controls data transfer, if the end of data transfer is usually recognized. [Problem(s) to be Solved by the Invention] Although hardware transmission will be completed when transmission for the data length set up before usually starting data transfer is completed as mentioned above, When considering it as the direction Human power direction of data transfer from an input/output device to an upper device depending on the case, the input/output device side may close data transfer at a count shorter than the data length beforehand set up by the situation by the side of an input/output device. In this case, since residual data length is not 0, the hardware by the side of an adapter, a bus controlling part, etc. will make the preparations which receive the following data, and will be in the waiting state. Although a microprocessor will recognize an end signal and will start end processing, if the end signal of data transfer is sent out from an input/output device in this state, Since the hardware which performs data transfer control, such as a bus controlling part, is in the data waiting state, the microprocessor must direct the close of data transfer by a certain means. When the end signal of transmission is sent out from an input/output device depending on the situation of an upper device, there is a possibility that data remains in the first-in first-out buffer and bus controlling part in an adapter, and the timing of the close directions by a microprocessor also poses a problem. In order to avoid such complicatedness, the memory which can store the data for 1 time of transmission length is prepared in an adapter, - Data sent by a series of data transfer of a time If all will be once stored in an adapter, even if data length is smaller than the first set-up value, the data transfer between an adapter and an upper device will be started with the actually sent data length, but by this method, many memories are needed and the amount of hardwares increases. There is a fault to keep. The present invention removes such a fault, and even when data transfer has been terminated with data length shorter than the data length beforehand set up from the input/output device side, synchronizing with a bus controlling part, final data directions are given for final data, It is not necessary to perform compulsory close processing by a microprocessor, and aims at providing the adapter which can lessen an increased part of hardware. [Means for Solving the Problem] A first-in first-out buffer to which the present invention considers a data bus between input/output devices as an input, In an input/output device control adapter by which a bus controlling part which controls data transfer with an upper device, and a control means which controls data transfer with the input/output device were connected to an internal bus, When data with the effective above-mentioned first-in first-out buffer does not exist 1 word, It is constituted when effective data exists 1 word, and so that a case where 2 words or more of effective data exist can be distinguished, When 2-word or more data exists in the first-in first-out buffer to a data request from the bus controlling part, it points to outputting data to the bus controlling part, An end signal of data transfer from the input/output device is effective, and when effective data exists in the first-in first-out buffer only 1 word, it points to it being final data to the bus controlling part, And it had independently a means to direct to output data to the bus controlling part from the first-in first-out buffer, as /"%-Dwarf. [Function] The case where 1 word does not have effective data, either, the case where 1 word exists, and the case where 2 words or more exist are distinguished, When 2-word or more data exists in a first-in first-out buffer to the data request from a bus controlling part, it points to data output, When the end signal of the data transfer from an input/output device is effective and 1-word data exists in a first-in first-out buffer, while directing that it is final data to a bus controlling part, it directs to output the final data. Even when data transfer has been terminated by this with data length shorter than the data length beforehand set up from the input/output device side, final data directions can be given to a bus controlling part synchronizing with final data, It is not necessary to perform compulsory close processing to a bus controlling part and a hardware transmission control circuit, and can lessen an increased part of hardware by a microprocessor after that. [Example] Next, a present invention example is described based on a drawing. A figure is a block diagram showing the composition of a present invention example. First-in first-out buffer 410 to which a present invention example considers data bus 500 connected to the input/output device outside a figure as an input, Bus controlling part 100 which controls data transfer with the upper device outside a figure, and microprocessor 200 which controls data transfer with an input/output device are connected to internal bus 110, When data with effective first-in first-out buffer 410 does not exist 1 word, It is constituted when effective data exists 1 word, and so that the case where 2 words or more of effective data exist can be distinguished, When 2-word or more data exists in first-in first-out buffer 410 to the data request from bus controlling part 100, it points to outputting data to bus controlling part 100, The end signal of data transfer from an input/output device is effective, and when effective data exists in first-in first-out buffer 410 only 1 word, it points to it being final data to bus controlling part 100, And it has gateway 03.04.05.06 which constitutes a means to direct to output bus controlling part 100 Heta from first-in first-out buffer 410. Bus controlling part 100 controls data transfer with the upper device outside a figure. Microprocessor 200 validates a hardware transmission-related circuit by setting register mouth 310. After that, the command to the input/output device outside a figure is set to register CM mouth 300 by microprocessor 200, it is sent out through data bus 500 to an input/output device, and, subsequently data transfer is performed. In the case of the data transfer of the direction of human power, synchronizing with human power data effective signal 501, data goes into register zero R400 from first-in first-out buffer 410 by data bus 500 course, and it is sent to bus controlling part 100 via internal bus 110. Gate old~06 manages the existence of the data in register zero R400 and first-in first-out buffer 410, Data request signal RQ from bus controlling part 100 and end signal 5'02 of transmission from a crowd force apparatus are considered as an input, and data receipt indication signal AC and final data indication signal LT are outputted to bus controlling part 100. Next, operation of each part constituted in this way is explained. First, microprocessor 200 will set register D310 via internal bus 110, if data transfer is needed. When register 0310 is set to 1, it is output IRDY from first-in first-out buffer 410. Signals, such as 0RDY, become effective and it becomes effective [ operation of each gate 01~06 ] (not shown in particular). Hereinafter, first-in first-out buffer 410, register zero R400, and gate old~06 etc. explains operation as a thing used as the effective mode. Microprocessor 200 writes the command (accompanied by data length) to the input/output device outside a figure in register CMD300 by internal bus 110 Out. A command is sent to an input/output device by this and data transfer is started. If the data transfer from an input/output device is started when data transfer is the direction of human power (the direction of [ from an input/output device ] an upper device), synchronizing with human power data effective signal 501, data will be sent in from data bus 500. Output signal IRDYI of first-in first-out buffer 410 (input Ready) When it is 1, it is shown that it is vacant in first-in first-out buffer 410, and there is area, In this case, a clock goes into input [N1 of first-in first-out buffer 410, the data from an input/output device is full for first-in first-out buffer 410, and the input clock of first-in first-out buffer 410 is made by gate 01. The data from an input/output device is full for first-in first-out buffer 410 like the following at the time of output signal IRDY 1 = 1. When 1-word or more data exists in first-in first-out buffer 410, When output 0RDY 1 (output Ready) of first-in first-out buffer 410 turns into 1 and there is no data effective in output signal IRDY O= 1 [ zero R400 ] of register zero R400, i.e., a register, When input 180 of register zero R400 becomes effective, data is taken into register zero R400, at the same time a clock goes into human power 0[IT 1 of first-in first-out buffer 410 and data is outputted from first-in first-out buffer 410, Human power ISO of 0IJT 1 of the input of first-in first-out buffer 410 and register zero R400 is made by gate 02. When data goes into register zero R400, it is shown that output 0RDY O of register zero R400 is set to one, and data effective in register zero R400 exists. First-in first-out buffer 410 can hold register zero R400 1 word, although a plurality of data is stored. If register D310 is set to 1, bus controlling part 100 will prepare a data receipt, and if it becomes good [ a receipt ], data request signal RQ will be validated. In the state where first-in first-out buffer 410 has data, data exists also in register QR400, If data request signal RQ is set to one in this state, signal OMIT O of register zero R400 will become effective through gates 05 and 06 for RQ=1 by output 0RDY l = 1 of first-in first-out buffer 410, Bus controlling part 1000 Human talent is sent for the contents of register zero R400 through internal bus 110 by becoming effective [ data receipt indication signal AC to bus controlling part 100 ] simultaneously. Thereby, [1ROY (since l is set to 0 and set to IROY O= 1, first-in first-out buffer 410 has data, and when it is 0RDY l = 1, data is similarly sent to register zero R400 from first-in first-out buffer 410 by the output of gate 02.) of the output of register zero R400 Like the following, in the state of going into register zero R400 and first-in first-out buffer 410, the data from an input/output device returns data receipt indication signal AC to data request signal RQ from bus controlling part 100, and passes data to bus controlling part 100 from register zero R400. Although data is sent out to the data request from bus controlling part 100 between output 0RDY 1 = 1 of first-in first-out buffer 410 if the input/output device side should make it end and final data shall have validated end signal 502 of sending-out machine transmission for data transfer after that at a certain time, If the data in first-in first-out buffer 410 is lost, it will be set to 0RDY 1 = 0, and will be in the state of 0RDY O= 1, i.e., the state where there is no data in first-in first-out buffer 410, and register zero R400 has 1-word data. If end signal 502 of transmission from an input/output device is set to 1 in this state and also data request signal RQ is set to one, Final data indication signal LT is inputted into bus controlling part 100 by gate 03.04, and also it lets gate 05.06 pass, and input OUT O of data receipt indication signal AC and register zero R400 is an effective next door. Final data is sent out by this to bus controlling part 100, it is set to output 0RDY O= 0 of register zero R400, and data transfer is completed. [Effect of the Invention] As explained above, according to the present invention, synchronizing with final data, even when data transfer has been terminated with data length shorter than the data length beforehand set up from the input/output device side, final data directions can be given to a bus controlling part, It is not necessary to perform compulsory close processing to a bus controlling part and a hardware transmission control circuit by a microprocessor after that and also and there is an effect which can lessen an increased part of hardware.

[Brief Description of the Drawings]

A figure is a block diagram showing the composition of a present invention example. 01.02.03.04.05.06 ... A gate, 100 ... Bus controlling part 110 ... internal bus, 200 ... microprocessor, 300 ... register CMD and 310 [ ... Data bus ] ... Register D1400 ... Register OR, 410 ... A first-in first-out buffer, 500