Time slot assignment facilities
Abstract
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Term
Term ended
Expired 12 October 2003, 23 years ago.
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9 claims: 9 independent, 0 dependent
- 1[Claim(s)] 【特許請求の範囲】 1 It is a Circuit for Controlling and Setting Up Communication Connection between Selected Port Circuits in a PCM Exchange Method, and is Then, a series -- periodic -- To repeat -- a time -- a slot -- As -- plurality -- the most important -- a time -- a slot -- generating -- a generator --;-- each -- it -- carrying -- having had -- N -- a piece -- a port -- a circuit -- having -- M -- a piece -- a port -- a board -- the -- one -- the -- two -- the -- three -- and -- the -- four -- a group -- containing -- control -- possible -- communication -- connection -- setting up -- a circuit -- setting The circuit receives a circuit board which performs circuit operation, and a port board and a circuit board, N pairs of a time slot are given to each board of the 1st and 2nd groups so that each port circuit of a board may receive most important pair of a time slot, ;holder, a port board, and a circuit board give the 1st time slot of the most important pairs of a time slot to each of a port circuit which forms the 1st half of the 3rd and 4th groups of a port circuit including a holder constituted so that communications service of the 1st type might be given, To each corresponding thing of a port circuit which forms the 2nd half of the 3rd and 4th groups of a port circuit for each 2nd time slot [ a pair of ] of these intermediary To have [ as ] which provides communications service of the 2nd type by giving -- a circuit which sets communication connection to enabled control characterized by things. 1 PCM交換方式において、選択されたポート回路の間で通信接続を制御して設定するための回路であつて、一連の周期的にくりかえすタイムスロツトとして複数個の一義的タイムスロツトを発生する発生器と;各々がそれに搭載されたN個のポート回路を有するM個のポートボードの第1、第2、第3および第4のグループを含む制御可能に通信接続を設定する回路において、該回路は回路動作を実行する回路ボードと、ポートボードと回路ボードを受け、ボードの各ポート回路はタイムスロツトの一義的な対を受けるように第1および第2のグループの各ボードに対してタイムスロツトのN個の対を与えることによつて、第1のタイプの通信サービスを与えるように構成されたホルダを含み;ホルダ、ポートボードおよび回路ボードはポート回路の第3および第4のグループの第1の半分を形成するポート回路の各々に対してタイムスロツトの一義的な対の内の第1のタイムスロツトを与え、これらの対の各々の第2のタイムスロツトをポート回路の第3および第4のグループの第2の半分を形成するポート回路の各々の対応するものに与えることによつて第2のタイプの通信サービスを提供するようになつていることを特徴とする制御可能に通信接続を設定する回路。
- 22 In a Circuit of a Statement, Each Time Slot of a Pair of Has Given a Time Slot Number of Odd and Even number to the 1st Paragraph of a Claim, A circuit which sets communication connection to enabled control when a circuit board is provided [ service of the 2nd type ], wherein it gives a time slot of No. odd to a port circuit which forms the 2nd half in a port circuit which forms the 1st half for a time slot of No. even. 2 特許請求の範囲第1項に記載の回路において、各々の対のタイムスロツトは奇および偶のタイムスロツト番号を与えられており、回路ボードは第2のタイプのサービスを提供するときには、第1の半分を形成するポート回路には偶数番のタイムスロツトを第2の半分を形成するポート回路には奇数番のタイムスロツトを与えることを特徴とする制御可能に通信接続を設定する回路。
- 33 a claim -- the -- two -- a paragraph -- a statement -- a circuit -- setting -- a circuit -- a board -- the -- two -- a half -- forming -- a port -- a circuit -- receiving -- a time -- a slot -- giving -- before -- odd -- No. -- a time -- a slot -- even -- No. -- a time -- a slot -- translating -- things -- the feature -- carrying out -- control -- possible -- communication -- connection -- setting up -- a circuit . 3 特許請求の範囲第2項に記載の回路において、回路ボードは第2の半分を形成するポート回路に対してタイムスロツトを与える前に、奇数番のタイムスロツトを偶数番のタイムスロツトに翻訳することを特徴とする制御可能に通信接続を設定する回路。
- 44 a claim -- the -- one -- a paragraph -- a statement -- a circuit -- setting -- a circuit -- a port -- a board -- the -- one -- and -- the -- two -- a group -- a port -- a circuit -- one -- a pair -- a terminal -- a device -- connecting -- things -- the feature -- carrying out -- control -- possible -- communication -- connection -- setting up -- a circuit . 4 特許請求の範囲第1項に記載の回路において、回路はポートボードの第1および第2のグループのポート回路を1対の端末デバイスに接続することを特徴とする制御可能に通信接続を設定する回路。
- 55 It is the Method of Operating a PCM Exchange System so that Communication Connection May be Set to Enabled Control between Those as which it was Chosen of Two or More Port Circuits, and is Then, In a way the system contains a generator which generates two or more most important time slots as a To repeat time slot periodically [ a series ], and a system includes a port circuit of the further 1st and the 2nd group, The method (1) In order to provide communications service of the 1st type, most important time slot is given to each port circuit of the 1st group, (2) Give a pair of 1st most important time slot from which each time slot differs to a port circuit which forms the 1st half of the 2nd group of a port circuit, An operation method of a PCM exchange method including a stage of giving each 2nd time slot [ a pair of ] of these to that to which a port circuit which forms the 2nd half of a port circuit corresponds. 5 複数個のポート回路の内の選択されたものの間で通信接続を制御可能に設定するようにPCM交換システムを動作する方法であつて、該システムは一連の周期的にくりかえすタイムスロツトとして複数個の一義的タイムスロツトを発生する発生器を含み、システムはさらに第1と第2のグループのポート回路を含む方法において、該方法は(1) 第1のタイプの通信サービスを提供するために第1のグループの各々のポート回路に対して一義的なタイムスロツトを与え、(2) ポート回路の第2のグループの第1の半分を形成するポート回路に対して各々のタイムスロツトの異る一義的な対の第1のタイムスロツトを与え、これらの対の各々の第2のタイムスロツトをポート回路の第2の半分を形成するポート回路の対応するものに与える段階を含むことを特徴とするPCM交換方式の動作方法。
- 66 A Time Slot Number of Even number and Odd is Assigned to Then and Each Time Slot of a Pair of by a Method Given in the 5th Paragraph of a Claim, The method is (1) further. When service of the 2nd type is provided, a time slot of No. even is given to a port circuit which forms the 1st half, (2) An operation method of a PCM exchange method including a stage of giving a time slot of No. odd, to a port circuit which forms the 2nd half. 6 特許請求の範囲第5項に記載の方法であつて、各々の対のタイムスロツトには偶および奇のタイムスロツト番号が割当てられており、該方法はさらに(1) 第2のタイプのサービスを提供するときには第1の半分を形成するポート回路に対して偶数番のタイムスロツトを与え、(2) 第2の半分を形成するポート回路に対しては奇数番のタイムスロツトを与える段階を含むことを特徴とするPCM交換方式の動作方法。
- 77 An operation method of a PCM exchange method, wherein the method includes a stage of changing a time slot of No. odd into a time slot of No. even before giving a port circuit which forms the 2nd half further, in a method given in the 6th paragraph of a claim. 7 特許請求の範囲第6項に記載の方法において、該方法はさらに第2の半分を形成するポート回路に与える前に奇数番のタイムスロツトを偶数番のタイムスロツトに変換する段階を含むことを特徴とするPCM交換方式の動作方法。
- 88 An operation method of a PCM exchange method combining with a method of connecting each of a port circuit of the 1st group to a pair of a terminal device in a method given in the 5th paragraph of a claim when service of the 1st type is provided. 8 特許請求の範囲第5項に記載の方法において、第1のタイプのサービスを提供するときには、第1のグループのポート回路の各々を端末デバイスの対に接続する方法と組合わされたことを特徴とするPCM交換方式の動作方法。
- 99 An operation method of a PCM exchange method, wherein one side of a terminal device is a data terminal in a method given in the 8th paragraph of a claim and another side of a device is telephone Set. 9 特許請求の範囲第8項に記載の方法において、端末デバイスの一方はデータ端末であり、デバイスの他方は電話機セツトであることを特徴とするPCM交換方式の動作方法。
Independent claims9
4 paragraphs, as filed
[Detailed Description of the Invention]
Technical field The present invention relates to the circuit which controls and sets up communication connection between the port circuits selected in the PCM exchange method. This circuit contains the group of the board of generator [ which generates two or more most important time slots in the series of the time slot repeated periodically ], 1st [ in which each has N port circuits put on it ], 2nd, 3rd, and 4th M ports. The background of an invention In an electronic time sharing exchange method like PBX, it is mounted on a print Wiring board, this is inserted in the device called a port carrier or a carrier next, and the line circuit or port circuit of a system is electrically connected. The port carrier has the slot or dent which can insert a board in it, and does interconnection to the point of contact of a board which swerves from a carrier's back face cloth line, and has two incomes at the back of a career electrically. According to the present semiconductor technology, each port circuit is comparatively small and can mount four pieces or eight port circuits in a single board in Source form. Each port circuit is assigned to a different system time slot, and while the time slot assigned to it occurs, the exchange network and signal of a system are delivered [ each port circuit ] and received through a network bus, moreover -- obtaining A call in handling by delivering and receiving the processor or controller, and signal of a system through an input-and-output bus -- . each port circuit letting a related transmission way pass, and obtaining a terminal unit like telephone in handling -- . ing which has both a data device like a data terminal, and telephone in each dual-use mobile phone in the system which unifies and provides the sound and data service which are proposed these days. This is shown in the paper which entitles the international-telecommunications meeting in 1979 "frame mode customer access to a local synthesis voice data digital network" of Achalino of page 38.5 / 1-7 others. in this paper, the method of obtaining both the sound of telephone and a terminal in handling using a single transmission way is described by by using the signal coded in frame form. Each frame has the field of two PCM (pulse code modulation) samples. One side of these fields relates to telephone, and another side relates to the data terminal. The transmission way from each of such a dual-use mobile phone is connected to the single port circuit of an exchange system. frame form which was stated to the above-mentioned paper -- Use -- the advantageous method of using a single port circuit for that which obtains two terminal units in handling by a single transmission way is the method of assigning two system time slots to each port circuit. Each of two assigned time slots relates to that from which two PCM sample frames stated to the previous paper differ. The audio signal from telephone is received by the 1st thing of the PCM sample field by this composition. The required call connection which passes along PBX for an audio signal breaks in handling between the 1st thing of the two system time slots assigned to the port circuit. The signal which occurred with the data terminal is received by the port circuit in the PCM sample field of another side. Required data call connection breaks in handling between the time slots of another side assigned to the same port circuit. the time sharing exchange method of PCM is usually designed so that the carrier with whom a predetermined number of time slots are also called a hair drier also as Had been which obtains in handling the port circuit of the type with which carriers differ, and has capability may be given. The system which provides the integrated voice data service proposed in the above-mentioned paper has 64 port circuits on each carrier, for example. These 64 port circuits [ four ] per board can be carried, therefore each carrier will have 16 boards. This board is also called a port board. two different system time slots are assigned to each of 64 port boards of a carrier, each carrier receives 128 PCM time slots and input-and-output signals, the 64 port circuit is obtained in handling, and things are required so that it may provide voice-data service. When the system mentioned above uses a easier port circuit, audio service can be provided and eight port circuits per board or 128 port circuits per carrier will exist in this case. Each port circuit needs only a time slot single for voice service. Since each carrier distributes 128 time slots and input-and-output signals to the port circuit which needs it also in this case, as far as a system time slot and a carrier are concerned, the system operates by the same method as having mentioned above. using a time slot and an input-and-output bus to the service request of the customer who changes to versatility as effectively as possible is wished by a time sharing exchange method. In the system provided to voice services, since the carrier who is seemingly new is not added when an intact time slot and a port circuit exist in the existing carrier, an input-and-output bus is usually used well. if it puts in another way, a customer's service request will change also about voice service, but such a changing demand adds a port circuit board to the existing carrier if needed, or by handling Ivy squirrel To, it is obtained in handling and can do things. The carrier who is seemingly new will be added at the time of It was which all the port circuits on the existing carrier's port board are assigned to the existing terminal, and is carried out and for which it waits. In the system which provides voice-data service by the method shown in the above-mentioned paper, the problem which efficiency improves use of a time slot and an input-and-output bus becomes more complicated. Each terminal has both telephone and a data terminal, and only when two time slots assigned to each port circuit are used, the time slot of a system is used well. A service request changes sharply, and in a certain kind of case, a problem is produced at the time of Noodle so that many terminals may receive single service only like a telephone. Under such conditions, since two time slots are too assigned to each port circuit, it can be said that no time slots are used effectively. This problem becomes more serious and eventually makes the efficiency of service fall under the conditions in which many of such terminals have provided only telephone or a data terminal. According to this situation, although an intact time slot exists in the existing carrier, what must extend an additional carrier will arise. In order to extend a module in order for a time slot to exist about the 1st module, and to add a carrier although it is intact in being extreme, and to satisfy a service standard, a time Multiplex switch may have to be added. therefore, the time of customers' demand changing in the time sharing exchange system which has the capability to assign two time slots to each port circuit, and to provide voice-data integration service -- a time slot -- effective -- using -- a problem -- I have left -- things are understood. If the present invention is followed, a circuit contains a Noodle holder by receiving a circuit board, and the port board and circuit board for performing circuit operation, and providing N pairs of time slots of each board of the 1st and 2nd groups so that the communications service of the 1st type may be given, The intermediary cage [ as ] in which each port circuit on a board receives the most important pair of a time slot, A holder, a port board, and a circuit board give the communications service of the 2nd model by giving each of the port circuit in the first half of the 3rd and 4th groups of a port circuit a pair of 1st most important time slot from which a time slot differs, This problem is solved by giving the a pair of most important time slot of the 2nd of each to each to which the port circuit in the second half of the 3rd and 4th groups of a port circuit corresponds. The carrier who will make a pair like 104 and 105 of a time sharing exchange system like PBX if the present invention is followed, The problem mentioned above by enabling it to equip the 1st mode that gives service of the 1st type that needs to use two time slots in each port circuit is solved. It becomes easy to reconstruct a carrier's pair in the case of the 2nd mode that gives service of the 2nd type with which each port circuit needs to use only a single time slot with such equipment. It is easy to change a carrier into the 2nd mode from the 1st mode, and it needs neither change of Wiring, nor change of composition for a carrier and control equipment of a system. PCM and the I/O cable by which plug connection was only made among carriers for performing this conversion are reattached, and the control board of the 1st model currently used for the 1st mode with each carrier is removed, When operating the carrier's pair in the 2nd mode, this may be replaced by the control board of the 2nd model. The carrier who states here can store the port board of the type with which a large number which have 4 per board or eight port circuits differ. The example where each board has four port circuits and which has 64 port circuits per carrier in all with 16 port boards per carrier is shown by the example indicated here. It needs for each of these port circuits to use two PCM time slots, when performing service of the 1st type that is "voice-data service. It is required for a carrier that this service should receive 128 PCM time slots. These are distributed by each carrier's control board and each port circuit receives two PCM time slots in the form of the control signal relevant to a PCM address. Each port circuit needs to use the most important input-and-output signal that has a control signal relevant to an I/O address again. Each carrier like 104 and 105 is connected to the PCM cable which has two halves [ it / it is divided and / for voice-data service ], the 1st and the 2nd, again. Each half of a PCM cable gives the half of the carrier relevant to 64 PCM addresses to the half of the carrier relevant to it. The input-and-output cable of itself is connected to each carrier who operates by a voice-data mode again, and it gives the control signal relevant to 128 different input-and-output signals to 64 port circuits on a carrier. About a voice-data mode, only 64 of the 128 input-and-output signals is used per carrier. The 1st combination of the control board for voice-data service is prepared for the carrier, Intermediary To have [ as ] in which this gives 64 PCM time slot signals received by each half to 32 port circuits of each half of a carrier, and each port circuit receives 2 time slot. These boards are distributed to 64 port circuits of the carrier of 64 address signals in an input-and-output cable again. The carrier may be made in the 2nd mode that instead provides service of the 2nd type that is voice dedicated service, and each port circuit needs only a single time slot and a single I/O address in this case. the PCM cable by which plug connection was made is connected to the carrier with whom two halves of a single PCM cable make two pairs, and the 2nd half of the handling paddle and the cable is constituted for the 1st half of a cable by obtain the 2nd carrier in handling in the 1st carrier. each half of a cable obtains 64 PCM time slots in handling -- . Intermediary To have [ as ] using [ the control board used in the 2nd mode connects the received PCM time slot to 64 port circuits of a carrier, and ] 1 time slot per port circuit. The single input-and-output cable including 128 I/O addresses is connected only to the 1st thing of the carrier with whom handling or Cormorant makes a pair like 104 in both carriers in the 2nd mode. The 1st carrier to whom the input-and-output cable is connected to it receives 128 input-and-output signals, distributes 64 in these input-and-output signals to 64 input-and-output ports of the 1st carrier, and connects with the 2nd carrier via the input-and-output bus jumper of the 64 remaining input-and-output signals. The 2nd carrier receives 64 input-and-output signals from the 1st carrier, and distributes these to 64 port circuits. If constituted in the 1st mode in which a carrier gives voice-data service, Each board on a carrier has the most important ID number (0 thru/or 15), A port circuit is accessed by giving the port address of No. even for the object of the selection signal which specifies a board identification number to a board, and input and output, and giving simultaneously odd number or the port address of No. even for the object of a PCM address. In order to give audio service or service of only data, when it is constituted in the 2nd mode and only the single time slot is used per port circuit, the number of 0 thru/or 7 is attached to the port board of each half of a pair of 1st carrier of a carrier. The number of 8 thru/or 15 is attached to the port board of each half a pair of carrier's 2nd carrier. Port input-and-output addressing is performed by generating simultaneously the input-and-output port address of Even number or Odd given to the control board of the board selection signal and carrier who identify the board on which the circuit by which an address is carried out is placed. This control board gives the port address of No. even to the port board in the left half of a carrier, and after the port address of No. odd changes this into the address of No. even first, it is given to the port board in the right half of a carrier. Therefore, port circuit 0 of the board of No. 0 of a carrier's 1st half (left half) is accessed by generating port selection signal 0 and port address 0 for audio service. Selection signal 0 goes to both right-hand side board 0 and left-hand side board 0. However, the number of port addresses 0 is even, and they are extended by only the board of a carrier's 1st half and choose a port circuit with address 0 on board 0. The corresponding board and port circuit in the right half of a carrier generate board selection signal 0 for the object of input and output, Port address 1 is received from an input-and-output cable, this port address of 1 is translated into 0 on a control board, and it is accessed by giving this after that to port circuit 0 of board 0 on the right-hand side of a carrier. Board identification numbers 8 thru/or 16 have the 2nd carrier in each half of a carrier, and addressing to the port circuit of this carrier's port board is realized by a similar method about audio service. As far as generating of a board selection signal is concerned, PCM addressing of the port circuit about audio service is realized by a method similar to having mentioned above. ing in which each carrier receives the address of the PCM time slot of 64, and it has [ both ] an address of No. even and No. odd. 32 received port addresses of No. even are distributed to 32 port circuits of a carrier's 1st half. the odd-numbered PCM port address obtains the port circuit in the right half of a carrier in handling -- . If the PCM address signal of the odd-numbered port is received, it will be changed into the signal of No. even by the control board, and then will be extended on it in the suitable port circuit in the right half of a carrier. the control board of the present invention -- the 1st or 2nd service mode -- therefore, it operates so that input and output and a PCM signal may be distributed. about the 1st mode, half a minute each of a carrier uses a control board, and each of such a control board obtains the half of a carrier in handling -- . When the carrier is equipped in the 2nd mode, a special control board is inserted in a carrier's 2nd half. A control signal is given to the control board of other halves of a carrier by insertion of this control board. It tells that this signal should distribute functionally the PCM time slot received by it to the control board of a carrier's 1st half to both carriers' half. By using the board of the 2nd type to service of the 2nd type, a board selection signal will be told about the method of occurring to a control board. the above thing shows that it is operating by the way the carrier who makes a pair changing with equipment of the present invention. The carrier port circuit can receive a suitable control signal including whether even per port circuit gives two time slots depending on the mode of the service which should be provided. This can be performed, without changing Wiring into a system or a carrier by the minimum change. An actually required thing only replaces reattaching [ by which a plug termination is carried out ] a circuit, the control board of the 1st type, and the control board of the 2nd type. The present invention is completely understood below by the detailed explanation which referred to the accompanying drawing. Detailed explanation Drawing 1 Drawing 1 is a figure of the PCM type PBX exchange system constituted so that voice-data integration service might be provided. This is prolonged to member terminals 126 and 127 through courses 109 and 120 including carriers 104 and 105 with whom PBX100 has port circuits 108 and 119, respectively. obtaining telephone 113-0 and data terminal 114-0 in handling respectively through course 111-0 and 112-0 including termination device 110-0 for each terminal like 126-0 to carry out the termination of the course 109-0 -- . Terminal 127 is constituted similarly. Port circuits 108 and 119 receive the signal transmitted through courses 109 and 120 from terminals 126 and 127, and transmit the received signal to other terminals relevant to the A call through time slot exchange network (TSI) 106. PBX100 is a stored-program-control type thing, and contains controller 101 containing a processor, a memory, and a control device. Controller 101 drives the input/output system of PBX through course 102, and drives TSI network 106 through course 103. As for the input/output system, this is connected to carriers 104 and 105 via input-and-output buses 117 and 118 including input-and-output interface 107, respectively. Although an input-and-output bus sends information to a port circuit in an I/O command, an address, and other forms, it is henceforth called an input-and-output signal about these. Each input-and-output signal contains the address of a port circuit like 108-0 which should answer the command. Each input-and-output signal includes the control information which gives directions to the port circuit which should perform circuit operation specified at the inside of a port circuit, or a related terminal again, and by which the address was carried out. Both of input-and-output signal ways are tropism, therefore a port circuit returns input-and-output information again to controller 101 via input-and-output bus 117 or 118, input-and-output interface 107, and course 102. Controller 101 transmits the signal which controls time slot exchange network 106 through course 103. This is only henceforth called a network. Network 106 lets PCM buses 115 and 116 pass for the information called a PCM time slot, and the information for controlling port circuits 108 and 119 is sent, therefore PCM information is exchanged between a port circuit and a network. While the system time slot relevant to a port circuit occurs, network 106 transmits the address information and data which specify a related port circuit through PCM buses 115 and 116. A port circuit recognizes arrival of the time slot, and exchanges a PCM signal for network 106 via a PCM bus. About handling or an intermediary To have port circuit, other information which forms then the theme of A call to which these signals have broken A call in handling between the time slot by the present PCM sample or its port circuit of the telephone call is expressed. network 106 -- this PCM information -- I receive, this is memorized temporarily and this is given to other port circuits relevant to the A call same between the system time slots relevant to other port circuits via suitable PCM bus 115 or 116. The information on an opposite direction is transmitted by the same method between port circuits. Intermediary To have [ as ] for which all the terminals 126 and 127 of Drawing 1 provide voice-data integration service. In terminal 126-0, telephone 113-0 provides a telephone service, and data terminal 114-0 provides data service. Termination device 110-0 receives Call information which should be transmitted through course 109-0 to PBX100 from device 113-0 and 114-0. Device 110-0 changes this information into the frame form of the type shown in Drawing 2, and gives this to port circuit 108-0 through course 109-0. Information is sent to the terminal relevant to it from a port circuit in the format same to an opposite direction again. Drawing 2 is illustrating Farmat of the frame to which information is transmitted through courses 109 and 120. Flaming A bit which shows the start of a frame is included F field. The signal and terminal information which are transmitted via a port circuit and an input/output system between terminal 126, or 127 and controller 101 are expressed S field. PCM Call information delivered and received between terminal 126 or PBX100 in 127 and telephone, and a data terminal is included 2 I fields. The field of I1 and I2 essentially expresses the information about two different A call from a terminal like 126-0. The I1 field information from telephone 113-0 is transmitted through course 109-0, and breaks in handling by the 1st thing of the two time slots relevant to port circuit 108-0 by PBX. The information from data terminal 114-0 is transmitted by I2 field through course 109-0, and while the 2nd time slot assigned to it arises, it breaks in handling by port circuit 108-0. if both telephones 113-0 and data terminals 114-0 in terminal 126-0 are Obstructions simultaneously, port circuit 108-0 will obtain both A call in handling simultaneously -- . Call information from telephone 113-0 and data terminal 114-0 is extended by port circuit 108-0 via PCM bus 115 between each time slot in network 106. Telephone call and data terminal A call are turned to an address by control of the dialed number. Handling or breaking terminal 127 is being connected to telephone 124 and data terminal 125 as well as terminal 126 by carrier 105. one pair of telephones which are that this only indicates an example to be and which were connected to each terminal at device TE if required may be installed -- or -- instead, one pair of data terminals by which each of it was connected to device TE may be provided. The information relevant to [ telephone, a data terminal or two telephones, or at least two data terminals of the character of a device are not related, and ] one terminal device in a terminal unit is transmitted by I1 field of Drawing 2, and the information which occurred by the 2nd device is transmitted by I2 field. a receiving port circuit acquires I2 field system information in handling by the time slot by which I1 field was assigned to a handling paddle and its 2nd [ the ] by the time slot to which the 1st was assigned -- . Carriers 104 and 105 are divided into two with the dashed line shown in each carrier's central part as shown in Drawing 1. PCM bus 115 branches carrier 104 into the 1st bus 115a that supplies a handling paddle and 64 PCM time slots of carrier's 104 1st half. Bus 115 branches into bus 115b of the lower part which supplies 64 PCM time slots to carrier's 104 2nd half again. PCM bus 116 transmitting 128 time slots, and obtaining carrier 105 in handling similarly, -- . the branching 116a transmitting 64 time slot, and obtaining carrier's 105 1st half in handling -- . Input-and-output bus 117 gives 128 input-and-output signals to both carriers' 104 half. Similarly, input-and-output bus 118 supplies the input-and-output signal of 128 to carrier 105. Detailed explanation Drawing 3 Drawing 3 is a figure of carriers 104 and 105 who are mounted as shown in Drawing 1, and supply "voice-data service which illustrated details further. Carrier 104 contains port board 0-15. Two most important system time slots are assigned to Am and each port circuit in which each board has four port circuits. Carrier 104 has port data interface (PDI) boards 301 and 302, port control interface (PCI) boat 303, and element 304 further. ing which has element 308 instead of element 304 although carrier 105 is constituted similarly. The function of the board of PCI and PDI is mentioned below. Each of PCM buses 115a and 115b gives 64 PCM time slot signals to carrier's 104 PDI boards 301 and 302. The time slot signal of 64 is given to each of PCM buses 116a and 116b to carrier's 105 PDI boards 305 and 306. PDI board 301 receives 64 PCM time slot signals from bus 115a, A time slot signal is distributed so that eight most important time slots may be given via back wiring of a carrier to each four port circuits of port boards 0 thru/or 7 in carrier's 104 half the left. PDI board 302 receives 64 time slot signals from bus 115b, and distributes eight most important time slots to each of eight port boards 8 thru/or 15 carrier's 104 half the right. carrier's 105 PDI boards 305 and 306 operate similarly, and it obtains them in handling, and they distribute eight PCM time slot signals to each of a port board. Input-and-output bus 117 gives 128 input-and-output signals to carrier's 104 PCI board 303. PCI board 303 gives 64 of the 128 input-and-output signals which it received to 32 port circuits on port board 0 thru/or 7 of carrier's 104 half the left. This gives the remaining input-and-output signals of 64 to 32 port circuits on port board 8 thru/or 15 in the right half of carrier 104 via a carrier's back face cloth line and element 304. Input-and-output bus 118 is given to PCI board 307 of carrier 105 of 128 input-and-output signals. PCI board 307 gives 64 of the 128 input-and-output signals which it received to 32 port circuits of port boards 0 thru/or 7 on carrier's 105 left half, This gives a carrier's back face cloth line to 32 port circuits on port board 8 thru/or 15 in the right half of carrier 105 via through and element 308 for the remaining input-and-output signals of 64. Since each port circuit uses only the even-numbered I/O address, bus 117 of Drawing 3 and the odd-numbered I/O address on 118 are not used by the port circuit so that it may mention below. buses 115,116,117 and 118 are comprised, a port circuit obtains the A call in handling, and a bus system controls a function. A port circuit carries out time sharing use of the bus. The address of a port circuit is given to one segment of a PCM bus or an input-and-output bus, By delivering and receiving information between port circuits through other segments of a bus, when a port circuit follows reception of the address simultaneously, information is exchanged between the PCM section of a port circuit, or an input output section. For example, there are four port circuits in the type of each port board of Drawing 3. These four port circuits are distinguished as port circuits 0, 2, 4, and 6 on each board. However, since two most important system time slots are assigned to each port circuit, it is necessary to give two different PCM bus addresses to each port circuit. Each PCM address is connected with one side of the two time slots assigned to the port circuit. Because there are four port circuits in a board and each port circuit needs two PCM addresses, Port circuit 0 will have addresses 0 and 1, port circuit 2 will have addresses 2 and 3, port circuit 4 will have addresses 4 and 5, and port circuit 6 will have addresses 6 and 7. The address of the port circuit is carried out by giving the board selection signal which identifies the board equipped with the port circuit, and giving the address of the port circuit of the simultaneously selected port board to a suitable bus conductor. Therefore, the address of the port circuit 0 on port board 0 is carried out by giving a board selection signal to board 0 simultaneously on a PDI board, and giving a port circuit address to all the port boards of the half of handling or breaking carrier 104 on the PDI board. Since only board 0 receives a board selection signal, only port circuit 0 of board 0 will answer. Each port circuit has only a single input-and-output port address (address of No. even). The input output section of a port circuit is accessed by giving the assigned I/O address to all the boards of the half of the carrier, and giving the most important board selection signal to the board by which the port circuit is carried simultaneously. PCM buses 115 and 116 are true time sharing buses, and a port address and a board selection signal are given to the specified order in order to specify a system time slot. The port circuit delivers [ as for the port circuit assigned to the time slot between each time slot ] then and receives the remaining portion and information on a system for A call via handling, intermediary If you go, and a PCM bus. The input-and-output bus operates in a similar way except for an address not being carried out in the sequence as which the port circuit was specified about the specified time slot. Instead, the intermediary of the address given to an input-and-output bus is also good in a random order determined by controller 101. Input-and-output bus 117 of Drawing 3 can give the input-and-output signal containing 128 possible port circuit addresses which make carrier 104 an address. Input-and-output bus 118 operates similarly about carrier 105. Since there are only 64 port circuits per carrier, the sound/data mode of Drawing 3 have an input-and-output port address where only 64 per cable differs. A port circuit receives two PCM time slots, and even when connected to the terminal with both telephone and a data terminal, a single input-and-output port address is used per port circuit. A suitable input-and-output message is alternatively transmitted to one of terminal devices by suitable coding of an input-and-output message. In the above composition, only the address of No. even is used in 128 port addresses on cable 117 or 118. The input-and-output port address of No. odd is not used. The system of the present invention is general-purpose, 8 port circuits are carried per board by a easier port circuit with the service of a certain kind which is not peculiar to the present invention, and the port circuit of 128 can be provided in all per carrier. In such a situation, 128 input-and-output port addresses may be given from an input-and-output bus to a carrier. As stated previously, it is about each of 64 port circuits for every carrier, If suitable encoding of an input-and-output message is performed although both telephone and a data terminal are controlled, Since it is enough if a single input-and-output port address is used per port, in the composition shown in Drawings 1 and 3, not all of 128 input-and-output port addresses are used. However, with the composition only for a sound of the present invention, the odd-numbered port circuit is also used so that it may mention below. Detailed explanation Drawing 4 Drawing 4 shows the system constituted like Drawing 1 except having the carrier constituted so that both integrated voice-data service and voice dedicated service may be provided, in order to use the time slot of a system effectively. In carrier 128 of Drawing 4, the port circuit 140 is connected to terminal 135 which has both telephone 132 and data terminal 134 through course 129 like carrier 104 of Drawing 1, or 105. This device operates in a way similar with having already explained in relation to Drawing 1. Carrier 128 receives a 128PCM time slot through PCM bus 116, and this branches to segment 116a which gives 64 time slot to a carrier's 1st half, and the 2nd segment 116b that gives 64 time slot to a carrier's 2nd half. Carrier 128 receives 128 input-and-output signals from input-and-output bus interface 103 via bus 118 again. Only the I/O address of the port circuit which has an even number for some carriers, of course is used. Carriers 104 and 105 of Drawing 4 are constituted for audio service, and are connected to terminal 126,127 which has only telephones 113 and 114, respectively via courses 109 and 120. Carriers 104 and 105 receive not the 128 time slot it received respectively in Drawing 1 in the case of voice-data service but 64 PCM time slots. PCM bus 115 has 128 time slots, and branches to segment 115a which supplies 64 time slots to the whole carrier 104, and segment 115b which supplies 64 time slots to the whole carrier 105. Therefore, carrier 105 shares PCM bus 115 and the time slot of 128 which it transmits. Input-and-output bus 117 gives the input-and-output signal of 128 to carrier 104. By the below-mentioned method, carrier 104 uses 64 of these input-and-output signals, and extends the remaining input-and-output signals of 64 to carrier 105 via input-and-output bus jumper 309. By this method, each of carriers 104 and 105 of Drawing 4 receives not the input-and-output signal of 128 which carrier 128 received but the input-and-output signal of 64. By the cable layout of Drawing 4, carriers 104 and 105 use well the time slot of 64, and the input-and-output signal of 64 given to it. ing which each carrier still contains the board of 16 in which each has four port circuits, and has a port circuit of 64 in all per carrier. However, in the case of the audio mode, each port circuit needs only a single PCM time slot. Therefore, these equipment can be effectively used now by giving the time slot of 64 to each 64 port circuits of carriers 104 and 105. Detailed explanation Drawing 5 As shown in Drawing 4, when it constitutes, Drawings 5 are carriers 104 and 105 who provide service of an audio type, and also show details. Segment 115a of bus 115 gives the PCM time slot of 64 to carrier's 104 PDI board 301. Segment 115b gives the time slot of 64 to PDI board 305 on carrier 105. These 64 time slots per carrier are distributed, and receive a time slot with each single port circuit. Input-and-output bus 117 gives 128 input-and-output signals to PCI board 303 on carrier 104. Board 303 distributes 64 of these input-and-output signals at a time to one circuit, and gives it to 64 port circuits on 16 port board on carrier 104. From PCI board 303, 64 of the remainder of the 128 input-and-output signals passes along element 504, and is given to carrier's 105 PCI board 307 via bus jumper 309. Board 307 distributes every one input-and-output signal [ 64 ] per circuit which it received, and gives it to 64 port circuits of carrier 105. The address of the input output section of one specific port circuit of Drawings 3 or 5 is carried out by giving the I/O address of a port circuit to back wiring of a career, and giving the I/O address of the port circuit in which the port circuit by which the address was carried out simultaneously is carried. 0 thru/or 15, and a number are attached to the port board of Drawing 3 with both carriers. When input-and-output bus 117 gives port selection signal 0 and port address 0 to PCI board 303, the address of the 1st port circuit of board 0 of carrier 104 of Drawing 3 is carried out. The address of the input-and-output port address 0 is carried out on PCI board 303 common to all the port boards. However, since board selection signal 0 is given only to board 0 on a PCI board, only the 1st port circuit on board 0 answers port address 0. Similarly, the address of other port circuits of carriers 104 and 105 of Drawing 3 can be carried out. As stated previously, only the I/O address of the port of No. even is used for voice-data services. Therefore, in Drawings 1 and 3, only the address of No. even in 128 I/O addresses on bus 117 is used by the port circuit. In the mode only for a sound of Drawing 5, each port is mechanically and electrically the same as the port circuit of Drawing 3. However, ing in which both the port boards of both carriers' 104 half have 0 thru/or 7 numbers, and the port board of each half of carrier 105, on the other hand, has a number of 8 thru/or 15 in Drawing 5. Input-and-output bus 117 of Drawing 5 receives the same input-and-output signal as input-and-output bus 117 of Drawing 3. However, also in the input-and-output port address of No. even, in Drawings 4 and 5, both the input-and-output port addresses of No. odd will also be used on bus 117 for audio service. Board selection input-and-output signals 0 thru/or 7 should be used on carrier's 104 board, and should receive PCI board 303 by; bus 117. The board selection signal of given 8 thru/or 15 is extended by PCI board 307 through element 504 and jumper 309, and is used by carrier 105. Carrier's 104 PCI board 303 carries out the address of the port board of both carriers' half with the board selection signal of 0 thru/or 7. The port circuit in the left half of a carrier relates to the port address (0, 2, 4, and 6) of No. even functionally. The port circuit in the right half of carrier 104 is functionally connected with the port address (1, 3, 5, and 7) of No. odd. By this means, the 1st port circuit on boat 0 in the left half of carrier 104 is accessed by board selection signal 0 and port address 0. PCI board 303 contains Intellect brain which is mentioned for giving port address 0 only to the board in the left half of a carrier below. Therefore, only the 1st port circuit on board 0 in the left half of carrier 104 answers board address 0 and port address 0. The address of the 1st port circuit of board 0 in the right half of carrier 104 is carried out by board selection signal 0 and port address 1 which were given to PCI board 303. PCI board 303 contains Intellect brain mentioned below, therefore input-and-output port address 1 is translated into 0, and then is given to the port circuit in the right half of a carrier. Similarly, PCI board 303 gives other input-and-output port addresses of No. even only to the top in the left half of carrier 104. If the odd-numbered port address is received, this will change it into the I/O address of the even-numbered port, and this will be given to the port circuit in the right half of carrier 104. By this method, PCI board 303 uses 64 in the input-and-output signal received through bus 117, in order to access alternatively 64 port circuits on carrier's 104 board. The port address of Even number in the 64 remaining input-and-output signals that PCI board 303 receives from bus 117, and the number of Odd is extended by carrier's 105 PCI board via element 504 and jumper 309. In a way similar with having described carrier 104, the even-numbered port address is turned so that the port circuit of the carrier of a left half may be chosen on board 307, The odd-numbered received port I/O address is translated into the even-numbered I/O address, and it is transmitted so that the port circuit on the right-hand side of carrier 105 may be chosen. it mentioned above -- as -- the port board of carrier 105 of each half -- 8 thru/or 15, and numbering Being done. Therefore, jumper 309 and PCI board 307 give a board selection signal with the number of 8 thru/or 15, in order to choose what it was specified of the port circuits as. A port circuit is chosen for the object of PCM by giving the most important board selection signal to a suitable board, and giving the PCM address of a desired port circuit common to all the boards simultaneously. Only the port circuit on the board directed by the board selection signal by which the address was carried out answers. Since each port circuit of Drawing 3 relates to two system time slots when service of voice-data is provided, each port circuit has two PCM addresses, Odd and Even number. PDI board 301 of Drawing 5 receives 64 time slots from bus segment 115a, and gives 32 in these time slots to port boards 0 thru/or 7 in the left half of carrier 104. Since each port circuit on a board needs only a single PCM port address, each of these port boards receives four time slots about audio service. In Drawing 5, the port circuit on the left-hand side of each carrier is related to the PCM address of No. even, and the port circuit on the right-hand side of each carrier is related to the PCM port address of No. odd. After PDI board 301 first translates into the address of No. even the PCM port address of No. odd which gave the PCM address of No. even which it received from cable 115a to the port board in the left half of carrier 104, and it received, it is given to the port board in the right half of a carrier. A carrier's PCM port address and PCM board selection signal of a right half are extended by BPDI board 502 via a carrier's back face cloth line. This board gives each of 32 port circuits of boards 0 thru/or 7 in the right half of carrier 104 the signal received at a rate of 1PCM address per port circuit. As stated previously, PDI boards 301 and 305 of Drawing 5 translate the port address of No. odd into the port address of No. even, before giving the port address of No. odd to the port circuit in the right half of a carrier via a PDI board. This translation is performed so that only the portion of the port circuit relevant to the PCM address of No. even may be used. Other portions of a circuit are not used. This is wished from the demand on management only the single terminal device of a related terminal enabling it to connect with the termination device by a uniform method. If it does not do in this way but a single terminal device is connected to a terminal by an unsuitable method, connection may be made so that the signal may be transmitted to the portion of the port circuit relevant to the PCM address of No. odd which is not used for voice PCM service. PDI board 305 of carrier 105 of Drawing 5 receives 64 PCM time slots from bus 115b, and gives each of 32 port circuits on port board 8 thru/or 15 in the left half of carrier 105 1 time slot. This gives the remaining 32 time slots to BPDI board 506 via carrier's 105 back face cloth line. BPDI board 506 gives these time slots to 32 port circuits of port boards 8 thru/or 15 in the right half of carrier 105. Detailed explanation Drawings 6 and 7 Drawings 6 and 7 show the details of carriers' 104 and 105 back face cloth line (front view) constituted so that service of a voice-data type might be given. When carriers 104 and 105 are connected by the voice-data mode in Drawings 1 and 3, PDI board 302 is inserted in slot XPDI602 in the right half of carrier 104. PCM cables 115a and 115b (64 time slot is given respectively) are connected to PDI boards 301 and 302, respectively. Input-and-output bus 117 which transmits 128 input-and-output signals is connected to PCI board 303. PDI board 302 supplies the signal (positive) of a high level from that internal circuit to mode signal line 608 at this time. Line 608 is connected to boards 301,303 and 302. Since this signal of a high level of line 608 provides voice-data service to PDI board 301 and PCI board 303, it is shown that the carrier is connected. In this mode, 3 state output driver on PDI board 301 connected to PCM cable extension bus 607 on a carrier's back face cloth line and PDI board 302 is de-energized. When these drivers on PDI board 302 are de-energized, PCM data is not transmitted to PCM cable expansion bus 607 between PDI boards 301 and 302. PCM data required for that which obtains 32 port circuits in the right half of carrier 104 in handling is given to PDI board 302 by PCM cable 115b. Input-and-output bus 117 gives the input-and-output signal of 128 to PCI board 303 for 64 port circuits of carrier 104. A high level signal (positive) is given to PCI board 303 via one conductor of input-and-output bus 117 again, It is shown that this is not what is connected to input-and-output bus 117 immediately after, and is connected to the input-and-output bus cable extension from carrier 105 and other carriers like input-and-output bus jumper 309 of Drawing 5 for the PCI board 307. When PCI board 303 is connected to immediately after input-and-output bus 117, mode signal line 608 is given on a high level from PDI board 302 and a voice-data mode is shown, PCI board 303 gives 64 of the port address which it received, and other input-and-output information to 32 ports on eight port boards in the left half of carrier 104. PCI board 303 lets PCI expansion bus 605 on the back pass, and gives the remaining input-and-output signals of 64 from bus 117 for obtaining 32 port circuits on eight boards in the right half of carrier 104 in handling via element 304. Each port circuit on carrier 104 chooses the voice-data service which received and mentioned above two PCM time slots and two input-and-output signals. However, the address signal of No. odd is not used depending on a port circuit. Carrier 105 of Drawing 7 is constituted like carrier 104 of Drawing 6, and provides voice-data service. Detailed explanation Drawings 9 and 10 Drawings 9 and 10 show carriers 104 and 105 constituted so that audio service might be provided. When being connected so that a carrier may provide audio service, not PDI board 302 but BPDI board 502 is inserted in slot XPDI602 of Drawing 9. PCM cable 115a (64 time slot is given) is connected to carrier's 104 PDI board 301. Input-and-output bus cable 117 (the input-and-output signal of 128 is transmitted) is connected to PCI board 303. BPDI board 502 gives the signal (grounding) of a low level [ line / 608 / mode signal ], and carrier 104 tells being constituted so that audio service may be given to PDI board 301 and PCI board 303. In this state, 3 state output driver on PDI board 301 connected to PCM extension bus 607 on a back face cloth line is energized. Board 301 can supply PCM information now to a carrier's right half by this. The PCM data needed with both PDI board 301 and BPDI board 502 is supplied by PCM cable 115a connected only to PDI board 301. PCM cable 115b is not connected to carrier 104 as shown in Drawing 6. Instead, this is connected to carrier's 105 PDI board 305. PDI board 301 receives 64 time slot from cable 115a, and gives the PCM time slot of 32 to 32 port circuits of eight port boards in the left half of a carrier. This gives 32 PCM time slots to 32 port circuits of BPDI board 502 and eight port boards in the right half of carrier 104 via PCM extension element 607. In this mode, each port circuit receives a single time slot. by the same method as this, PDI board 305 obtains 64 port circuits of carrier 105 in handling, and receives the time slot of 64 from cable 115b to a sake. input-and-output bus 117 obtains both carriers 104 and 128 port circuits on 105 in handling, and gives the input-and-output signal of 128 to a sake to PCI board 303. The high level signal of a stationary state is also given to PCI board 303 via one conductor of input-and-output bus 117, and indicates not input-and-output bus cable extension 301 but directly connected to input-and-output bus 117 like PCI board 307 of carrier 105 of Drawing 10. PCI board 303 is connected to input-and-output bus cable 117, When mode signal line 608 from BPDI board 502 shows service of only a Then sound on the low level, PCI board 303 gives the input-and-output signal of 32 to 32 port circuits on eight port boards on the left-hand side of carrier 104 (0-7), This gives 32 input-and-output signals again to 32 port circuits on port board 0 thru/or 7 in the right half of carrier 104 through back PCI expansion bus 605 to element 504. PCI board 303 supplies 64 input-and-output signals to 64 port circuits on 16 port boards of carrier 105 again. These 64 input-and-output signals are supplied to carrier's 104 element 504 via input-and-output bus extension 606. These are given here to PCI board 307 on carrier 105 via jumper 309 of an input-and-output bus cable. Element 504 gives a low level (grounding) signal to PCI board 307 on carrier 105 again via basketball bull jumper 309. It is shown that this is not directly connected to input-and-output bus 118 to board 307 as shown in Drawing 4, instead this grounding signal receives an input-and-output signal via input-and-output bus jumper 309 at this time. since 64 PCM time slots received from PCM cable 115b are related and audio service is provided using these input-and-output signals, carrier 105 gets the 64 port in handling -- . Detailed explanation Drawing 12 Drawing 12 is illustrating the details of a port control interface (PCI) board like PCI board 303 of Drawing 9. Operation of all the PCI boards is the same. This is only related with the input-and-output bus to which it is connected, and is different intermediary To have. 64 port circuits on all the 16 port boards and carriers are obtained in handling, and one PCI board is used for a sake with each carrier. The input-and-output signal containing a control signal, a port board selection address signal, a port address signal, and data is given to input-and-output bus connector 1201 from input-and-output bus 117, 118, or input-and-output jumper 309. When audio service is equipped with a PCI board like board 303 on carrier 104, these data is given to element 504 and jumper 309 again via input-and-output bus extension lead 606 on the back. This information is given from here to the PCI board on carrier 105 constituted via jumper 309 for audio service. The control information part of an input-and-output signal is given to receiver 1206 from connector 1201 via course 1217. The port address, the port board selection signal, and condition data in the received input-and-output signal are given to transceiver (XCUR) 1202 through course 1211 from connector 1201. XCUR1202 gives a control signal to XCUR1202, annexation XCUR1203, and dried one 1207-1208 via course 1218. These control signals are given to XCUR1202 and annexation XCUR1203, and Set these to either a transmitting data mode or a receiving data mode. Data is given to the port chosen from the input-and-output bus cable via the PCI board in transmitting mode. In receiving mode, data is given to an input-and-output bus cable via a PCI board from the selected port. Driver 1207 gives a signal to the port where it was chosen in the left half of the carrier through course 1225. Driver 1208 gives a control signal to the port board in the right half of a carrier via course 1226 and PCM extension 605. These signals indicate whether the address or the port is then given to the selected port. These signals set XCUR of a port to either transmitting mode or receiving mode again. In the audio mode, a buffer port data interface (BPDI) board like 502 is inserted in the XPDI socket on each carrier as shown in Drawings 9 and 10. Since a carrier is constituted in the service only for a sound when a BPDI board is inserted in XPDI socket 602, the jumper wire of BPDI board 502 connects mode signal line 608 to grounding. In a voice-data mode, port data interface (PDI) board 302 is inserted in XPDI socket 602. Mode signal line 608 is not grounded depending on a PDI board, but a mode signal line is held by pull-up resistance 1228 connected to +V at a high level state. The potential on mode signal line 608 is given to address decoder 1205. It is told whether this signal generates the board selection signal for voice data service as shown in whether the board selection signal for voice-data service as this shows in Drawing 3 to a decoder is generated, and Drawing 5. From input-and-output bus cable connector 1201, the signal called ETM2 signal is given to receiver 1206 through course 1217, and is given to address decoder 1205 via course 1219 from receiver 1206. When ETM2 signal is a high level, this tells that the PCI board is directly connected via an input-and-output bus cable like 117 to address decoder 1205. When ETM2 signal is a low level, this shows that the PCI board is connected to other carriers like 105 via input-and-output bus jumper 309 to address decoder 1205. This information controls how a decoder generates a board selection signal. The audio mode When it is shown that the carrier is operating in the audio mode, the PCI board is carried in carrier 104 on the high level, and ETM2 signal on a PCI board is connected to input-and-output bus 117, Address decoder 1205 supplies only port board selection addresses 0 thru/or 7 to both the outputs 1223 and 1224. Port board selection signals 0 thru/or 7 are given to the port board in the left half of a carrier through course 1223, and are given to the port board in the right half of a carrier via course 1224 and PCI extension element 605. As for this, a PCI board is connected to jumper 309 when ETM2 signal is a low level. It is shown that it is on carrier 105. At this time, address decoder 1205 supplies only port board selection addresses 8 thru/or 15 of both that output. Port board selection signals 8 thru/or 15 are given to the left half of a carrier's port board via course 1223, and are given to the port board in the right half of a carrier via course 1224 and PCI extension element 605. Address decoder 1205 gives a functional energization signal to address Map 1209 and annexation XCUR1203 again through course 1215. This signal controls whether a port address is generated by any in a voice data mode or the audio mode. In the audio mode, only the even-numbered port address (0, 2, 4, and 6) in the received input-and-output signal is given to the half on the left-hand side of a carrier by annexation XCUR1203 through course 1221. Next, data is delivered and received between input-and-output bus cable 117 and the selected port through course 1221, annexation XCUR1203, course 1212, XCUR1202, course 1211, and connector 1201. The port address (1, 3, 5, and 7 which are not used in a voice-data mode) of Odd of a reception input-and-output signal is translated into the port address of Even number by address Map 1209, and is given to a receiver / Driver 1210 via course 1214. These translated port addresses are given to the port in the right half of a carrier via course 1222 and PCI extension element 605. Next, data lets Exclusive wiring pass, It is delivered and received between input-and-output bus cable 117 and the selected port via PCI extension element 605, course 1222, a receiver/Driver 1210, course 1212, XCUR1202, course 1211, and input-and-output bus cable connector 1201. Voice-data mode Mode signal line 608 is maintained at a high level in a voice-data mode by resistance 1228 on a PDI board like 302. By this, address decoder 1205 operates so that the port board selection address which can use [ all the / of 16 ] the received input-and-output information (0 thru/or 15) may be decoded. This de-energizes the annexation function of annexation XCUR1203, and the mapping function of address Map 1209 by sending a de-energizing signal through course 1215 again. Port board selection signals 0 thru/or 7 are given to the port board in the left half of a carrier through course 1223. Port board selection signals 8 thru/or 15 are given to the right half of a carrier's port board through course 1224 and PCI extension element 605. Annexation XCUR1203 gives a port address to the board in the left half of a carrier via course 1221. The port address of the board in the right half of a carrier is given to address Map 1209 through course 1212. Because address Map circuit 1209 is de-energized by course 1215, Without changing, the received port address is given to receiver driver 1210 through course 1214, and is given to the board in the right half of a carrier via course 1222 and PCM extension element 605. next -- obtaining the port where the port address was decoded on the selected port board specified by decoder 1205, and the address of the specified board was carried out in handling -- . Data is delivered and received via course 1221, annexation XCUR1203, course 1212, XCUR1202, course 1211, and input-and-output bus connector 1201 between input-and-output bus cable 117 and the port board in the left half of a carrier. Data is delivered and received via course 1222, receiver driver 1210, course 1212, XCUR1202, course 1211, and input-and-output bus cable connector 1201 between input-and-output bus cable 117 and the port board in the right half of a carrier. Detailed explanation Drawing 13 Drawing 13 is a port Data interface (PDI) board, and also it is illustrating it in detail. In this circuit, the audio mode or the voice-data mode can also operate. When connected in the audio mode, only a single PDI board is used per (lead 608 is grounding) and carrier. This single PDI board is in a carrier's left half. This assigns the half of the PCM time slot which it received to the port board in the left half of a carrier, and is assigning other halves to the port board in the right half of a carrier. The PDI board is connected to a carrier's left half via leads 1313-1310, 1320, 1308, 1323, and 1325. This is connected to a carrier's right half via conductors 1321-1319, 1322, 1324, 1326, and 1327 and extended lead 607. In a voice-data mode, a separate PDI board is used in each half of a carrier, and each board gives all the time slots which it receives to the port board on the half of a carrier. Then, extended lead 607 is not used. The PCM time slot containing a timing signal and PCM data is given to connector 1301 on a PCI board from cable 115a or a PCM cable like 115b. The received PCM data is given to output Latchch 1302 through course 1306 from connector 1301. The PCM data received by the PCI board from the port is given to PCM cable connector 1301 from input Latchch 1303 through course 1307. In the audio mode, as illustrated in not a PDI board but buffer port data interface (BPDI) board 502, or 506 to Drawings 9 and 10, it is inserted in XPDI socket 602. BPDI board 502 or 506 grounds mode signal line 608, when inserted in XPDI socket 602. In a voice-data mode, port data interface (PDI) board 302 or 306 is inserted in XPDI socket 602. Mode signal line 608 is not grounded at this time, but it is set to a high level by pull-up resistance 1328 connected to +V. Mode signal line 608 of Drawing 13 And 1318 is pull-up resistance 1328, port address driver 1314, extended port address driver (EPAD) 1333, timing demultiplexer (T-Dmux) 1330, input multiplexer (I-Mux) 1329, and output driver 1331, It is connected to A hit clock driver 1332. This high level signal de-energizes the output of output driver 1331, A bit clock driver 1332, and EPAD1333. This high level signal controls I-Mux1329 and T-Dmux1330 again, and this transmits the board and data on the carrier of the same side as a PCM cable and a PDI board. At this time, nothing is given to extended lead 607 on a PDI board. A bit clock lead 1308 is given to timing generator 1304, inverter 1305, output Latchch 1302, and a port through course 1308. Frame clock lead 1309 is given to a timing generator through course 1309. A bit and a frame clock specify the present PCM time slot. Two or more eight A bit clock signals exist per time slot. Timing generator 1304 determines a port and a port board selected for the time slot given now. A port address (0-7) is given to port address driver 1314 through course 1315. The high level signal given to course 1318 from mode line 608 for a voice data mode operates port address driver 1314, and operates the port address of both Even number and Odd to a carrier's port by the side of it through course 1313. The arbitrary things of the eight time slots assigned to each port board are chosen by this. Timing generator 1304 gives a board energization signal to T-Dmux1330 through course 1312. Board selection or an energization signal lets T-Dmux1330 pass, and is given to a carrier's port board by the side of it via course 1323. A board energization signal prevents the port board by which an address is not carried out from giving data to a bus by energizing only the output driver of the selected port board. The output driver on other port boards of all the is de-energized. Timing generator 1304 gives a board synchronized signal again to T-Dmux1330 through course 1317. A board synchronized signal lets T-Dmux1330 pass and is given to a port board from course 1325. A board synchronized signal serves as a clock with which a PCM signal goes the port selected between the right time slots in and out. PCM data goes into the port where the A bit clock signal of course 1308 was chosen as the high level at the time of Noodle, and moves from the port where the A bit clock was chosen as the low level at the time of Noodle to a PDI board. As for PCM output data, the 1st A bit clock given through course 1308 is given to output Latchch from PCM cable connector 1301 at a high level synchronizing with a clock at the time of Noodle. As for PCM output data, the following A bit clock given to output Latchch through course 1308 is given to output Latchch 1302 through course 1310 at a high level from output Latchch 1302 at the time of Noodle. The input PCM data to a PDI board is given to I-Mux1329 from the selected port on course 1320. The A bit clock with which the 1st which data was given through I-Mux1329 and given from inverter 1305 was reversed is given to a high level from I-Mux1329 through course 1311 at Latchch 1303 synchronizing with a clock at the time of Noodle. As for PCM input data, the A bit clock with which the next was reversed is given to a high level with a clock into a PCM bus from input Latchch 1303 via PCM cable connector 1301 at the time of Noodle. Each A bit clock with which the output from inverter 1305 was given to the inverter through course 1308 is set to a high level on a low level at the time of Noodle. In the audio mode, mode signal line 608 is grounded on the BPDI board inserted in XPDI socket 602. This low level signal on course 1318 energizes output driver 1331, A bit clock driver 1332, and EPAD1333. this grounding sets I-Mux1329 and T-Dmux1330 as the audio mode, and these obtain the port board of a carrier's both sides in handling in this mode -- . The A bit clock signal on course 1308 is given to the port on timing generator 1304, inverter 1305, output Latchch 1302, and course 1308. The frame clock on course 1309 is given to timing generator 1304. This A bit and a frame clock signal specify the present system time slot. Timing generator 1304 specifies a port and a port board, in order to choose the present system time slot. By a timing generator, the port address of Even number and Odd is both given to port address driver 1214 and EPAD1333 through course 1315. Only the even-numbered port address where it received address driver 1314 with the grounding signal on course 608 in audio service is given to a carrier's left half through course 1313. EPAD1333 changes into the port address of No. even the port address (1, 3, 5, 7) of No. even which it received when course 608 was a low level, and this is given to a carrier's right half via course 1327 and PCM extension lead 607 next. Since the telephone in a related terminal is always connected so that I fields relevant to even port addresses may be used, only even port addresses are used with audio service. Timing generator 1304 gives board selection or an energization signal to T-Dmux1330 through course 1312. T-Dmux1330 gives the board energization signal of the even-numbered port (0, 2, 4, and 6) to the port board in the left half of a carrier through course 1323. T-Dmux1330 gives the board energization signal of the odd-numbered port (1, 3, 5, and 7) to BPDI board 502 through course 1324 and PCM extension lead 607. By energizing only the output driver of the selected port board, a board energization signal prevents the port by which an address is not carried out from giving data to a bus. The output driver of other port boards of all the is de-energized. Timing generator 1304 gives a board synchronized signal again to T-Dmux1330 through course 1317. T-Dmux1330 gives the board synchronized signal of even ports to the port board of the top in the left half of a carrier through course 1325. T-Dmux1330 gives the board synchronized signal of the odd-numbered port to BPDI board 602 through course 1326 and PCM extension lead 607. A board synchronized signal carries out the clock synchronizer of the PCM data which goes the port selected between the right time slots in and out. As for PCM data, the clock synchronizer of the A bit clock is carried out to a high level from a PDI board in a port at the time of Noodle, and the clock synchronizer of the A bit clock is carried out to a low level from a port at PDI at the time of Noodle. The clock synchronizer of the PCM data is carried out for the first A bit clock given through course 1308 to a high level from PCM cable connector 1301 to output Latchch 1302 at the time of Noodle. The following A bit clock given to output Latchch through course 1308 carries out a clock synchronizer to the left-hand side carrier port and output driver with which PCM output data was chosen through output Latchch 1302 to course 1310 at the time of Noodle, and is given at a high level. PCM data is given to a carrier's right half through course 1321 and PCM extension lead 607 from output driver 1331. The PCM data from a carrier's left half is given to I-Mux1329 through course 1320. The input PCM data from a carrier's right half is given to I-Mux1329 from PCM extension lead 607 and course 1319. I-Mux1329 multiplexes the data from both a carrier's halves into the right time slot. At the time of Noodle, through course 1311, the 1st A bit clock given to inverter 1305 carries out the clock synchronizer of the data to input Latchch 1303, and it is put into it by high Level from I-Mux1329. As for PCM input data, the A bit clock with which the next was reversed is given to a high level from input Latchch 1303 to PCM cable connector 1301 at the time of Noodle. Each A bit clock with which the output from inverter 1305 is given to an inverter through course 1308 is set to a high level on a low level at the time of Noodle. Detailed explanation Drawing 14 Drawing 14 is illustrating the details of a buffer port data interface board (BPDI). A BPDI board is inserted in XPDI slot 602 when a carrier is constituted by the audio mode. A BPDI board serves as a timing signal from a PDI board like 301 or 305 inserted in a carrier's left half, and a buffer of PCM data. These signals are given to a BPDI board through PCM extension lead 607, in order to serve the port in the right half of a carrier. A grounding signal is given to mode signal line 608 from BPDI board 502 through course 1413. This grounding shows that it is the audio mode to a PDI Yo PCI board. PCM data is given to buffer 1401 from PCM extension lead 607 through course 1421. Buffer 1401 gives data to a port through course 1414. PCM data is given to buffer 1402 through course 1415 from a port. Buffer 1402 gives data to PCM extension lead 607 through course 1419. From PCM extension lead 607, a A bit clock signal lets course 1422 pass, and is given to buffer 1403. Buffer 1403 lets course 1416 pass and gives a A bit clock signal to a port. A board selection signal is given to buffer 1404 through course 1424 from PCM extension lead 607. Buffer 1404 gives a board selection signal to a port board through course 1417. A board synchronized signal is given to buffer 1405 through course 1426 from PCM extension lead 607. Buffer 1405 gives a board synchronized signal to a port board through course 1418. A port address signal is given to buffer 1406 from PCM extension lead 607 through course 1427. Buffer 1406 gives a port address to a port through course 1411. Detailed explanation Drawing 15 Drawing 15 shows the input-and-output circuit of the port board. This circuit communicates with the PCI board of Drawing 12 through courses 1221-1223 and 1225. Course 1221 gives data and a port address. Course 1223 gives the board selection signal from a PCI circuit to a port board. Intermediary To have with this course most important on the port board in which each of it differs including two or more conductors. Course 1225 transmits Strobe and a control signal like reading / writing signal. Intermediary To have common [ on the board ] to all the port circuits in which this is provided in every one port board including receiver 1501, control logic 1508, and address Latchch 1502 as for each port board. ing which reads each port circuit with write-in register 1503 like write-in register 1503-0 of port circuit 0, and read-out register 1504-0, and has a register. When the board selection signal from course 1223 is suitable, and is given in control logic 1508 and the port address from course 1221 is given to receiver 1501 simultaneously with this, transmission of the information on a port circuit is started. The port address part of information is given to address Latchch 1502 through course 1507. Address information is Latchch(ed) when a strobe signal is given to Latchch 1502 through control logic 1508 and course 1509 from course 1225. Fundamentally, Latchch comprises 8 person Selection 1 decoder, writes in the most important gating signal through course 1506 with the read-out register of the port circuit on a board by which the address was carried out, and gives it to a register. It writes in Drawing 15 with the read-out register of port 0, and only the register is illustrated. The Latchch signal of port circuit 0 is given to register 1503-0 and 1504-0 through course 1506-0. This Latchch signal Guess write-in register 1503-0 is transmitted to a board through course 1221 and receiver 1501, and can receive and register the data given to the register through course 1507-0. With this same Latchch signal, read-out register 1504-0 can give information to course 1221 prolonged on the PCI board through through and transceiver 1501 in course 1505-0 and course 1505 now. As mentioned above, only the register about port circuit 0 is illustrated in Drawing 15. In a similar way, transceiver 1501 and address Latchch 1502 can give a gating signal and information to the register relevant to other circuits on a port board. Detailed explanation Drawing 16 Drawing 16 is illustrating the details of the PCM circuit of each port board. Each port board contains 8 person Selection 1 decoder 1603 common to all the port circuits on a board. Each port board contains two or more transmission buffers 1602 and receive buffers 1601 which corresponded to the port circuit where each of it differs again uniquely. Receive buffer 1601-0 and transmission buffer 1602-0 are the most important in port circuit 0. The perpendicular line is prolonged in the buffer to which other port circuits on the same board correspond. The circuit of Drawing 16 receives the information directed from the PDI board of Drawing 13 through courses 1313-1310, 1320, 1308, 1323, and 1325. The circuit of a specific board and the specific circuit of a board are accessed when decoder 1603 receives a port address from course 1313. Courses 1323 and 1325 contain two or more conductors which were equivalent to the port board in which each of it differs in one discussion. If a port address is received, decoder 1603 will operate and this will produce the output signal prolonged only about one of the port circuits on a board in buffers 1601 and 1602. For example, when a decoder gives the signal on course 1604-0 to both transmission buffer 1602-0 and receive buffer 1601-0, port circuit 0 is chosen. When a A bit clock signal is simultaneously received on course 1608 with the synchronized signal on course 1325 at this time as for buffer 1601-0, buffer 1601-0 can receive PCM data from course 1310. When a board energization signal is simultaneously received at this time, buffer 1602-0 can transmit PCM data to a PDI board through course 1320. Similarly decoder 1603 chooses the arbitrary things of other port circuits on a board, and the coda and decoder enable it to deliver and receive a PDI board and PCM data. Note Account Only the sound is used only for the object of explanation for a term called voice-data to make an understanding of the present invention easy. A term called only a sound may be put in another way only as data, and the term called voice-data may be put in another way as a voice-sound and data again.
[Brief Description of the Drawings]
Drawing 1 is a figure showing the system for voice-data Sibisu, and Drawing 2 is a figure showing the signal format between the terminals of the port circuit of Drawing 1, Drawing 3 is a detail view of the carrier for voice-data service --; -- Drawing 4 is a figure of a Noodle system, as both voice-data service and audio service are provided Drawing 5 is a detail view of the carrier for audio service, Drawings 6 and 7 are figures of the carrier for voice-data service showing details further, and it is Drawing 8, It is a figure showing the arrangement relation of Drawings 6 and 7, and Drawings 9 and 10 are a carrier's detail views constituted for audio service, Drawing 11 is a figure showing the arrangement relation of Drawings 9 and 10, and Drawing 12 is a detail view of the circuit of a PCI board, Drawing 13 is a detail view of the circuit of a PDI board, Drawing 14 is a detail view of the circuit of a BPDI board, Drawing 15 is a detail view of a port input-and-output circuit, and Drawing 16 is a detail view of a port PCM circuit. [The explanations of letters or numerals of a main part], port board ...... PCI, PDI, holder ...... 104,105, circuit board ...... BPDI.
18 members in 9 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 43382182 | United States of America | A | |
| 433821 | – | – | – |
| US19820433821 | – | – | – |
Members18
| Document | Office | Kind | |
|---|---|---|---|
| SE8305237D0 | Sweden | D0 | |
| GB8327049D0 | United Kingdom | D0 | |
| DE3336641A1 | Germany | A1 | |
| FR2534436A1 | France | A1 | |
| SE8305237L | Sweden | L | |
| NL8303490A | Netherlands (Kingdom of the) | A | |
| GB2128850A | United Kingdom | A | |
| JPS5986991A | Japan | A | |
| US4510596A | United States of America | A | |
| GB2128850B | United Kingdom | B | |
| CA1200330A | Canada | A | |
| FR2534436B1 | France | B1 | |
| CH663306A5 | Switzerland | A5 | |
| SE458247B | Sweden | B | |
| JPH0342759B2This record | Japan | B2 | |
| DE3336641C2 | Germany | C2 | |
| NL192173B | Netherlands (Kingdom of the) | B | |
| NL192173C | Netherlands (Kingdom of the) | C |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Cancellation because of no payment of annual feesLAPS | LAPS |
Numbers
- Publication, DOCDB
- H0342759
- Publication, EPODOC
- JPH0342759B
- Application
- 58189418
- Application, DOCDB
- 18941883
- Application, EPODOC
- JP19830189418
Classification
- CPC, 2
- H04Q11/0428
- H04M11/068
- IPC, 2
- H04M11 06
- H04Q11 04