Computer memory management.

[Detailed Description of the Invention]

The present invention relates to the structure of a computing device and a micro computing device, and generally relates to the circuit art of managing especially the memory of a computing device. In any computer systems, especially a micro computer system, since memory elements are the expensive parts in a device, it is a common target to make quantity of random access memory (RAM) needed into the minimum. Simultaneously, it is a target of all computer structures to provide the flexibility in a program, and, thereby, the limit in a storage capacity does not pose a problem added for the programmer. Using technically the individual memory management unit (MMU) arranged between a microprocessor or other central processing units (CPU), and RAM from such a thing has been adopted. Using this MMU permits calling data in a memory in a "logical" address in a program, and the "logical" address is changed into the "physical" memory address to which data actually belongs by MMU. The physical memory actually arranged is less than the logic memory made useful by the program. Therefore, when MMU fully uses a physical memory useful when carrying out software operation in which it was ordered in the system, it is an important element. As for Z8001 microprocessor made from Zilog, as a specific example of such a system, one or the Zilog Z8010MMU memory management unit beyond it is used. This specific microprocessor specifies one of the logic memory segments from which 128 differs on a segment bus, and the specific position in the segment is shown on an address bus. Each [ of the segment of 128 ] has a memory up to 64 K bytes. MMU is used in order to control the capacity of the each of the segment of a memory every 256 bytes. MMU includes a register to each of 64 memory segment, and the register directs the real start address of the each of the physical segment in a physical memory like the capacity of a physical segment. the capability of MMU which controls the capacity of a physical segment -- the data memory of a stack or the amount of good changes -- an intermediary -- it is useful. For example, variable stack memory capacity occupies one of the logic memory segments of 128, and results in removing the useful logic memory in the segment out of the storage capacity of a stack. The 1st Righteousness object of the present invention is to provide the improved memory management system which uses useful logic and a physical memory space effectively. If it summarizes, the improvement by the present invention will use two individual memory management units in which the method of one operates, in order to control the same logic memory segment simultaneously. Each portion of the memory segment controlled by each [ of MMU ] can be extended, and it makes it possible to provide the stack memory and the extended data memory which were extended by it in one logic memory segment. It is prevented by the break register which includes an address in the segment which divides two portions, and duplication of these two memory portions is one of the MMU, From the break address value memorized in the register, depending on whether it is a higher rank or it is a low rank, an address answers the specific address access instructions from CPU, and operation of it is enabled. This break value is updated so that change of the relative capacity of a memory portion may be reflected. By including two variable storage capacity memory portions in one logic memory segment, many limited physical memories are more useful for a programmer because of other use. Drawing 1 shows the block diagram using the improved circuit by the present invention of a computing device. In this example, a micro computer system shows that a central processing unit is microprocessor 11 which may be obtained as Z8001 microprocessor of the single integrated circuit made from Zilog. The microprocessor leads to semiconductor RAM13 of the canonical form. Although computer systems are not shown in Drawing 1, they usually operate in relation to a magnetic media memory like a floppy disk or a tape. Some computer systems shown in Drawing 1 are permitting microprocessor 11 so that the address of the specific portion of memory 13 may be carried out. Three Z8010 memory management units 15, 17, and 19 are adopted from this. Although other portions, for example, data path, and data-processing elements of computer systems are not illustrated, they are known well. There are many useful publications which indicated the microprocessor of Zilog, the structure of a memory management unit, and use which may be obtained in a market, and there are. This example is a manual of Zilog. Two manuals about Z8001 microprocessor and a related circuit are "Z8000CPU technical manual" August, 1980, and with "Z800 PLZ/ASM assembly language program manual" April, 1979. although the memory management unit is indicated somewhat in detail in these publications -- further -- detailed -- "Z8010MMU memory management unit and manufacture specification" October, 1979 and, and with "Z8010MMU memory management unit and technical unit" October, 1980 -- it comes out. These four publications are referred to in the text. Microprocessor 11 of this specific form includes 16 bit-address bus, and it is shown by two individual buses in order that these may explain easily including the top A bit supported by the lowest A bit and bus 23 where the address bus is transmitted by bus 21. The microprocessor 11 has memory segment bus 25. The column on the left-hand side of Drawing 2 expresses two in the useful logic memory segment of 128 which may be separately called by the suitable code on memory segment bus 25. Two logic segments shown by "A" and "B" in Drawing 2 are shown for the object of explanation. Although memory 13 regards microprocessor 11 as including the segment of 128 each capacity of whose is 64 K bytes, it includes a segment with few physical memories 13. Although a physical memory includes fewer segments, the memory which becomes in size is accessed by several different users, and makes a part of segment useful to a predetermined microprocessor in this way. The handling of the memory address on the left-hand side of three MMU of Drawing 1 is shown by the logical address as shown in the column on the left-hand side of Drawing 2, but on the other hand, the address on the right-hand side of three MMU is shown as a real memory physical address, as shown by the column on the right-hand side of Drawing 2. Although the MMU element which may be obtained in the same market is used for each [ of MMU 15, 17, and 19 ], the functions completely differ. It stands to reason that separate code MMU15 which controls a number of logic memory segments which exist for an operating system program, a user program, and similar computer-systems control software is used. On the other hand, a logic segment is used for storage of data, a stack memory, and other similar objects, and they are all controlled by the 2nd MMU. However, according to the present invention, it is for the function of the 2nd MMU used in common being made by individual two MMU17 and 19, and the former of the logic memory in one logic segment controlling a stack, and is for the latter controlling a data part. Both the stack of the logic segment and data can be extended, It is the object of the portion of others of the microprocessor of Drawing 1, and the system between three MMU to control 17 and 19 of MMU in order to prevent duplication of the extended data in one logic segment and the memory portion by which the stack was carried out. Drawing 2 expresses two logic segments "A" and "B", and is provided with the individual data and the stack memory portion which are extended in the direction of Mutually. The control logic of MMU17 and 19 includes system break register 27, user break register 29, the Multiplex circuit 31, and comparison machine 33 as basic essentials. The Multiplex circuit 31 is a switch based on control of the signal level in line 35 only connected to one pin of microprocessor 11. This pin generates the signal to clarify, when "Normal" or a "user" memory portion is used, and user register 29 is connected to one of the two inputs of comparison machine 33 by circuit 31 in that case. A different signal level in line 35 which displays the case where the "system" portion of a memory is accessed produces that system register 27 is connected to the input of comparison machine 33 by the Multiplex circuit 31. The 2nd input of comparison machine 33 is combined with high rank portion 23 of an address bus. A signal is generated by line 37 which uses stack MMU17 when the high-ranking portion of an address bus includes a high-ranking address from the register connected to the input of another side of comparison machine 33. On the other hand, from register 27 or 29 by which the high-ranking portion of an address is connected to the comparison machine input of another side by switch 31, low grade or when equal, a signal is generated by line 39 which uses data MMU19. Therefore, operation of one of MMU17 and the 19 is attained at the time of any 1 way. It is applied in order to use it, when the memory logic segment "A" is called in Drawing 2 as for the address of break register 27. The determination of whether the system stack of a segment "A" or the address in a system-data portion was called is made by comparison machine 33 and its output control signal. User register 29 includes the address for using it within a memory logic segment "B" simultaneously. 64 segment-descriptor-word register by which stack MMU17 was turned to the logic segment "A" as for the method of one, and another side have the register turned to the logic segment "B." usual operation of MMU used in order that MMU may control a stack -- therefore, in order to start with the standard logical address in the peak of a segment and to provide the stack capacity needed, it extends downward. A logic segment "A" and the stack portion of "B" are independently controlled by the reason different segment registers in MMU are used for each reason by MMU17. In a similar way, data MMU19 controls two logic segments "A" of Drawing 2, and the data part of "B" by an individual segment or register. The value in break registers 27 and 29 is set up in order to specify the stack of each logic segment, and the boundary between data parts. Although these registers include a fixed value to the address between these portions, Whatever those relative capacity is even if, even if these registers extend or contract how, since an address is included within each segment which always specifies separation between two, it is preferred to update these registers. Therefore, each [ of break registers 27 and 29 ] is combined with the high rank address portion of an address bus, and, thereby, the high rank address byte can go into any inside of a register at the suitable time. The control for putting in these values to registers 27 and 29 is provided by input-and-output (I/O) address decoder circuit 41. The only I/O Address is assigned to access from a microprocessor, and, in circuit 41, registers 27 and 29 are, When system break register 27 is called, when user break register 29 is called, in circuit 43, an enabling signal is generated in circuit 45. The circuit of Drawing 1 is designed to operate suitably and break register 27 includes the address corresponding to the address shown by 47 of Drawing 2, i.e., the address in Ezi of the data register in a logic segment "A." Similarly, user break register 29 includes suitably the address corresponding to the address shown by 49 of Drawing 2 about a logic segment "B." In this way, since MMU extends and reduces the capacity of the data part of a logic segment, a microprocessor operating system also updates a corresponding break register. Since it extends or reduces at a rate that the data part of the portion applied most is later than a stack portion, Ezi of a data part is used rather than Ezi of the stack portion of a logic segment. In operation, any access enables operation of stack MMU17 by microprocessor 11 of a logic segment "A" which has a larger address than the address shown in 47. A small address carries out whether it is equal to the address shown in 47 in operation [ 19 / data MMU]. A part of program of operation designed in the circuit of Drawing 1 for Z8001 microprocessor and Z8010MMU is shown in a later table. Since the directed data part extends or contracts, the value which should be updated by this table in break registers 27 and 29 is produced. It is an assembly language at the coding partial target by which it is shown in a table, and the C language partially. Standard status line 51 is connected between each [ of microprocessor 11 and MMU 15, 17, and 19 ] by the usual method. It is determined from a microprocessor when decoder circuit 53 should also be connected to this line, and the data part of a memory should be called, In that case, when a suitable enabling signal is generated by line 55 from the decoder or the code portion of a memory is called, a suitable enabling signal is generated by line 57. As mentioned above, code MMU15 does not call any same logic segments called by stack or data MMU17 and 19. One of three MMU is used in the moment there is either. Changing the logical address by the side of the input on the left-hand side of MMU into the physical address in output bus 59 in Drawing 1 is performed by the usual method. What does not usually come out is enabling it to treat independently each of four different logic segment data and a stack memory field to use each stack MMU and data MMU. As shown in Drawing 2, to each [ of system data, a system stack a causer stack and a user data part ], the physical address is independent, therefore permits the flexibility size benefits [ flexibility ] the maximum use of the limited physical memory by the inside of a standard operating system. The segment descriptor word register in data MMU19 which answers the logic segment "A" code of memory segment bus 25 includes start edge physical address 61 of a physical segment "A", as shown in Drawing 2. Similarly, the segment descriptor word register in MMU19 which answers the logic segment "B" includes start edge address 63. In both cases, each register of MMU19 includes information about the capacity of a physical segment. In two of the segment descriptor words which answer independently of a logic segment "A" or "B" in memory segment bus 25 in a similar manner, stack MMU17 includes each for stack start physical addresses 65 and 67. A part of program of operation designed in the circuit of Drawing 1 for Z8001 microprocessor and Z8010MMU is shown in the following table.

[Table]

[Table]

[Brief Description of the Drawings]

The block diagram of the memory management circuit according [ Drawing 1 ] to the present invention and Drawing 2 are figures showing both the logic used by the circuit of Drawing 1, and a physical memory. (Explanations of letters or numerals), 11 ...... A microprocessor, 13 ...... A memory, 15 ...... Code MMU, 17 ...... Stack MMU, 19 ...... Data MMU, 21 ...... A low rank address bus, 23 ...... A higher rank address bus, 25 ...... A segment bus, 27 ...... A system break register, 29 ...... A user break register, 31 ...... Multiplex, 33 ...... A comparison machine, 35, 37, 39, 43, 45, 55, 57 ...... A line, 41 ...... [ ...... A decoder, 59 / ...... A bus, 61 63 / ...... A start edge physical address, 65, 67 / ...... Start physical address. ] An I/O address decoder, 47, 49 ...... A Ezi address, 51 ...... A status bus, 53