Nova Patents
JPH03212901A

Square board type chip resistor

Abstract

PURPOSE:To reduce irregularities of a glass surface and to realize high precision of packaging without increasing dispersion of resistance values and deteriorating oxide resistance of glass by providing a specified three layer glass layer of specified softening point and linear expansion coefficient on a thick film resistance layer. CONSTITUTION:An upper surface electrode 2 is formed on 96 alumina substrate 1 and a thick film resistance layer 4 mainly composed of RuO2 is formed partially overlapping thereon. A first glass layer 5 is formed thereon, whose glass softening point is 550 to 570 deg.C and linear expansion coefficient is 69X10<-7> to 7<5>X10<-7>/ deg.C. An imprinting glass layer 6 having a softening point of 550 to 570 deg.C and linear expansion coefficient of 68X10<-7> to 74X10<-7>/ deg.C and a second glass layer 7 having a softening point of 580 to 630 deg.C and linear expansion coefficient of 62X10<-7> to 68X10<-7>/ deg.C are formed thereon. An edge surface electrode layer 3 is formed, which partially overlaps with the layer 7 and the electrode layer 2. Since a softening point of the first glass layer 5 is lower than that of the second glass layer 7, the imprinting glass layer 6 sinks to the layer 5 and irregularities of a surface reduce, thereby preventing development of cracks on the surface.

JPH03212901A, drawing sheet 1
Sheet 1 of 1

Term

Term ended

Projected expiry passed 18 January 2010, 16.7 years ago.

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1 claim: 1 independent, 0 dependent

  1. 1
    【特許請求の範囲】 絶縁性のセラミック基板と、前記セラミック基板上に形成される銀系厚膜の上面電極層と、前記上面電極層の一部に重なるルテニウム系厚膜の抵抗層と、前記抵抗層を完全に覆う軟化点が550°C~570°Cでかつ線膨張係数が69×10^-^7~75×10^-^7/°Cの第1ガラス層と、前記第1ガラス層上に形成される軟化点が550°C~570°Cでかつ線膨張係数が68×10^-^7~74×10^-^7/°Cの捺印ガラス層と、前記第1ガラス層上で前記捺印ガラス層を完全に覆うように形成される軟化点が580°C~630°Cでかつ線膨張係数が62×10^-^7~68×10^-^7/°Cの第2ガラス層と、前記上面電極層の一部に重なる銀系厚膜の端面電極層とより構成したことを特徴とする角板型チップ抵抗器。