Manufacture of semiconductor device

[Detailed Description of the Invention]

Field of the Invention The present invention is a semiconductor device and a thing especially about the manufacturing method of a memory device. PRIOR ART In recent years, a semiconductor device, especially a memory device have the high request of high integration, and multi-gate structure has come to be well used especially for a read-only memory device (following ROM and an abbreviation). The example of the manufacturing method of ROM of the conventional multi-gate structure is explained according to Drawing 2 below. As shown in Drawing 2 a, mask 8 for impurity diffusion which consists of photoresist corresponding to the ROM code which silicon substrate 1 is made to memorize via the 1st gate dielectric film 2, etc. is formed, and impurity diffused layer 9 for threshold voltage control is formed in a silicon substrate by the ion implantation of impurities, such as arsenic. Next, as shown in Drawing 2 b, multiple 1st gate electrode 3 is formed at equal intervals. Next, as shown in Drawing 2 C, the 2nd gate dielectric film 4 is passed for electrode material 5 of the 2nd Gaea I-electrode, and it is resist pattern 10 of after formation and the 2nd gate electrode Electrode 3l\-/ * It forms on A dog. Next, as shown in Drawing 2 d, etching formation of the 2nd gate electrode 6 is carried out, and interlayer insulation film 7 is formed. Object of the Invention In the above-mentioned conventional manufacturing method, after forming the impurity diffused layer corresponding to the ROM code, the 1st gate electrode and the 2nd gate electrode are formed, After carrying out the user Yo Si order received of the ROM code from the place which forms an interlayer insulation film, the time (following TAT and abbreviation) of 1 shipped as a product had the problem that it was long. the Into which does not form an impurity diffused layer in order to shorten TAT -- interlayer insulation film Freshly -- oh, after rudder forming, the mask for impurity diffusion was formed on the interlayer insulation film, and it had high accelerating voltage -- be [ ion notes ON ] alike -- although Si and the method to write in can be considered It becomes difficult it to control the diffusion region of Si with each different diffusion depth and impurities to it, since Death differs in the shape of the 1st gate electrode and the 2nd gate electrode to the above-mentioned multi-gate method. If constituted only from a 1st gate electrode, although control of the diffusion region of impurities becomes easy, it will drop a degree of location inevitably and cannot expect large scale-ization. The present invention solves such a conventional problem. the object drops a degree of location -- things (shortening of TAT is providing a manufacturing method which can be done easily.). Means for solving problem The means of the present invention is Yo Si about the above-mentioned problem for etching into anisotropic dry etching by Height dimension of Yo 9 and the 1st gate electrode in the case of the 2nd gate electrode formation, the 2nd gate electrode was embedded between the 1st gate electrodes, the 1st gate electrode and the 2nd gate electrode made it flat shape, the interlayer insulation film was formed on it, the mask for impurity diffusion was formed after that, and it had high accelerating voltage -- be [ ion notes ON ] alike -- the process of writing in nine is used. OPERATION Control of the impurity diffusion field of the channel portions of MOS type 1 and run District from Yo 9 interlayer insulation film becomes easy at the above-mentioned technique. EXAMPLE 5 Beno Hereinafter, the example of the manufacturing method of ROM of the multi-gate structure of one example of the present invention is explained according to Drawing 1. As shown in 1st [ The ] figure second, multiple 1st gate electrode 3 is formed in silicon substrate 1 at equal intervals via the 1st gate dielectric film 2. Next, as shown in Drawing 1 b, as shown in Drawing 2 C, it etches into anisotropic dry etching to the height of Yo Si and the 1st gate electrode after forming 2nd gate electrode material 6 via the 2nd gate dielectric film 4, and 2nd gate electrode 6 is formed. Next, as shown in Drawing 1 d, interlayer insulation film 7 is formed on the 1st and 2nd gate electrodes, form mask 8 for impurity diffusion which consists of photoresist corresponding to the ROM code moreover made to memorize, etc., and impurities, such as arsenic, be [ ion notes ON ] alike -- impurity diffused layer 9 for threshold voltage control is formed in Si and a silicon substrate. EFFECT OF THE INVENTION The present invention is the 6. between the 1st gate electrodes by Esoting(ing) by Height casing of the 1st gate electrode of Yo Si to anisotropic dry etching in the case of the 2nd gate electrode formation, >2 gate electrode is embedded and the 1st gate electrode and the 2nd gate electrode make it flat shape, He is Yo Si for writing in by the ion implantation which formed the mask for impurity diffusion after forming an interlayer insulation film on it, and had high accelerating voltage, Since TAT becomes short, without dropping a degree of location because the writing of the ROM code after interlayer insulation film formation becomes easy, it is greatly useful for time-for-delivery shortening of a super-bulk memory.

[Brief Description of the Drawings]

The process sectional view and Drawing 2 in which Drawing 1 shows one example of the present invention are a process sectional view of a conventional example. 1 ...... A silicon substrate, 2 ...... The 1st gate dielectric film, 3 ...... The 1st gate electrode, 4 ..... the 2nd gate dielectric film and 6 ...... the -- The gate electrode material of two, and 6 ...... the -- The gate electrode of two, and 7 ...... an interlayer insulation film and 8 ...... the mask for impurity diffusion, and 9 ...... an impurity diffused layer and 10 ...... the -- the resist pattern of the gate electrode of two.