Ecl circuit

[Detailed Description of the Invention]

Field of the Invention The present invention relates to the ECL circuit of an integrated circuit. PRIOR ART The conventional ECL circuit is shown in Drawing 2, and this is explained. in Drawing 2 -- l -- a NPN transistor and 2 -- NPt1 run District and 3 -- as for a non-inversed input terminal and 7, load resistance and 5 are [ a reversal output terminal and 11 ] reversed output terminals a current generator and 6 load resistance and 4 an inversed input terminal, grounding and the power supply in which 8 is negative as for 9, and 10. When non-inversed input terminal 6 changes from H to L and inversed input terminal 7 changes from L to H, reversed output terminal 11 changes from H to L, and reversal output terminal 10 changes from L to H. The speed to which reversed output terminal 11 changes from H to L is determined by the current capacity of NPN run District 1, and the current value of current generator 5. Changes speed becomes quick, so that the current value of current generator 5 is so large that the current capacity of NPN transistor 1 is large. On the other hand, the speed to which reversal output terminal 10 changes from L to H is proportional to the product of the sum of the parasitic capacitance of wiring, and the collector capacity of NPN transistor 2 which connects the collector and load resistance 4 of NPN transistor 2, and the resistance of load resistance 4. Object of the Invention In such conventional composition, when you were going to make it increase the speed which makes current capacity increase and to which an output terminal changes from H to L by making the area of a transistor increase, collector capacity increased and there was a problem that the speed to which an output terminal changes from L to H decreased. The present invention aims at making the changes speed from L to H of an output terminal increase, without solving such a problem and decreasing the changes speed from H to L of an output terminal. Means for solving problem An ECL circuit which is characterized by that the present invention comprises the following in order to solve this problem. The 1st NPN transistor by which a base was connected to the 1st input terminal, a collector was connected to the 1st source of constant potential via the 1st resistance, and an emitter was connected to the 2nd source of constant potential via the 1st current generator, The 2nd NPN transistor by which a base was connected to the 2nd input terminal, a collector was connected to the 1st above-mentioned source of constant potential via the 2nd resistance, and an emitter was connected to the 2nd above-mentioned source of constant potential via the 1st above-mentioned current generator, The 1st pHMOS transistor by which a gate was connected to a collector of the 1st above-mentioned NPN transistor, sauce was connected to the 1st above-mentioned source of constant potential, and Dorain was connected to a collector of the 1st above-mentioned NPN transistor, 2nd P type MO8 run District by which a gate was connected to a collector of the 2nd above-mentioned NPN transistor, sauce was connected to the 1st above-mentioned source of constant potential, and Dorain was connected to a collector of the 1st above-mentioned NPN transistor. OPERATION According to the present invention, it becomes possible to raise certainly the changes speed from L to H of an output terminal, without decreasing the changes speed from H to L of an output terminal. EXAMPLE One example of the present invention is shown in Drawing 1, and this is explained. In Drawing 1, 1 is a NPN transistor and 2 is NPN run District, 3 -- load resistance 4 -- load resistance and 5 -- as for a reversal output terminal and 11, a non-inversed input terminal and 7 are [ P type MO8 transistor and 13 ] P type MOS transistors a reversed output terminal and 12 a current generator and 6 an inversed input terminal, grounding and the power supply in which 8 is negative as for 9, and 10. In this composition, if non-inversed input terminal 6 changes from L to H and inversed input terminal 7 changes from H to L, reversal output terminal 10 tends to change from H to L, and reversed output terminal 11 tends to change from L to H. If the voltage of reversal output terminal 10 becomes lower than the Threshold voltage of P type MO8 transistor 12, P type MO8 transistor 12 is turned on. On the other hand, since NPN transistor 2 is turned off, reversed output terminal 11 will be charged with the current of the sum of the current which flows in from grounding 8 via load resistance 4, and the current which flows in from grounding 8 via P type MOS transistor 12. By this operation, an output terminal becomes [ changing to H, or ] possible from L quickly. Since P type MO8 run District 12 turns off if the potential of reversed output terminal 11 becomes higher than the Threshold voltage of P type MO3 run District 12, there is no inflow of the current to reversal output terminal 10, and reversal output terminal 10 does not decrease the speed which changes from H to L. EFFECT OF THE INVENTION As mentioned above, according to the present invention, since charging current flows in via P type MOS transistor, an output terminal becomes possible [ changing to H ] from L quickly, and high-speed operation can be realized.

[Brief Description of the Drawings]

Drawings 1 are a circuit diagram of the ECL circuit by one example of the present invention, and a circuit diagram of the ECL circuit of the former [ Drawing / 2 ]. 1 ...... NPN run District, 2 ...... NPN run District, 3 ...... Load resistance, 4 ...... Load resistance, 5 ...... A current generator, 6 ...... [ ...... A negative power supply, 10 / ...... A reversal output terminal, 11 / ...... A reversed output terminal, 12 / ...... P type MOS transistor, 13 / ...... P type MOS transistor. ] A non-inversed input terminal, 7 ...... An inversed input terminal, 8 ...... Grounding, 9