Wafer testing process of ic with non volatile memory

[Detailed Description of the Invention]

[Industrial Application] This invention is A flash(ed) to the test method of the primary test (it calls following WT) in the manufacturing process of IC (referred to as IC below) which has nonvolatile memory. [Description of the Prior Art] W T of IC writes in and comprises a test, stress impression (bake), and a read-out test. They are Drawing 3 + and a test flow chart of tw'r. A write-in test is a test which makes each chip on Wajeha memorize data in the same [ slight ]. Stress impression is written in and imposes load on the wafer after a test from the exteriors, such as heat stress. A read-out test is a test which checks that the data which wrote in and was memorized by the test does not change with stress impression. Next, a write-in test and a read-out test are explained. These tests are testing with the test system constituted by the test device and the automatic line. Flowing of Feno - of the self-!111 inside of a plane [ Drawing / 4 ] -- it is the shown flow chart. A wafer is supplied to a position Agreement part from a feed section. A direction, a chip position, etc. to Waie are detected in a position Agreement part. In a test implementation part, M child for a test is connected to the bonding pad in a chip, and one chip is tested. If one chip serves as the completion of a test, from the size of the chip inputted beforehand, a wafer will be moved so that the terminal for a test may be connected to the next chip, and it will test by Terrible(ing) the terminal for a test to the bonding pad of the next chip. This operation is carried out to the chip of one wafer Inner gold. It is stored by the wafer Hau Eva stowage which the test of the wafer money-paid-on-account chip completed. an untested wafer is supplied to Lack of from a Procurement part, and it is This. A test is completed by this manipulate return. Here, time T which a test takes to one wafer is shown by the following (1) type. T-(t+tn) xn+a -- "-"- (1) -- here, in addition to this, the number of chips in one wafer and alpha of the test time of only 1 A tip, time for a self-rlJJ opportunity to carry out [ t / m ] a chip by one in @ Motion, and a mouth are between required one (processing time in a position Agreement part, etc.). Drawing 2 is a top view of the conventional wafer, and 1 tips in a figure (21 is a bonding pad, 3 is a Square eve line, and it has the composition that the chips of each became independent electrically.), [Problem(s) to be Solved by the Invention] With the conventional wafer, since it was independent electric respectively as mentioned above, there was a problem [ time / T ] of being required, like the above-mentioned (1) formula in the test (write-in test) time per wafer. It was made in order that this invention might carry out the Japanese sake of the above problems, and the chip in a wafer is electrically connected mutually, the whole chip is operated simultaneously, and it aims at carrying out a write-in test by package about all the chips in one wafer, and shortening test time. [A useless means to solve a subject] The wiring from a bonding pad is pulled out on a dicing fin, and it connects with the Ponday pad of other chips, and makes it operation of the wafer test concerning this invention attained in the state where all the chips in a wafer are the same. [Function] The wafer test in this invention can complete a WTI Write test by 1 time per wafer regardless of the number of chips in a wafer. [Example] Hereinafter, 1 operation Column diagram of this invention is explained. The l 1st A is a top view of a wafer which is carrying out WT which is 1 merit 1 Thu i of this invention. in a figure, Dt begins to see wiring for a chip and 2 to connect a bonding pad, for 3 connect Squibf, and for 4 connect chip 1 in a wafer in sleepiness 1, and 5, and they are exclusive terminals. As shown in a figure, chip 1 in connection If you miss and a wafer carries out the same operation for all the chips 1 in a wafer altogether electrically. If it tests by writing in in this state, like [ it is the same with the former and ] the Off theta-chart of Drawing 4, this Waeno - that a wafer flows through the inside of a self-motive, and goes will be supplied to a test implementation part, and it will test by connecting the terminal for a test to bonding pad 2 in chip 1. Since it wires so that all all the chips in a wafer may carry out the same operation here, and it C Is, when testing 1 A tip, one wafer serves as the completion of a test only by Open. When test time of one wafer at this time is set to TA, this time is (2) types of A long time and is Show 0 To. TA=(t)+4 ...... (2) -- 5 t is l-chip test time, and alpha is time (processing time in a position Agreement part, etc.) required for the Ya here. Next, the read-out test after stress impression is explained. even if the all chip in a wafer is connected in 1 mind at the time of a chip design -- read-out operation -- chip each -- it will read, if the mode which operates independently is given, and operation of a test is possible as usual. The read-only terminal that a chip will carry out read-out operation independently if a certain regular signal is inputted is provided in a chip, and if human power of the regular signal which is in a read-only terminal at the time of a read-out test is carried out, it can test by reading it as usual. [Effect of the Invention] According to this invention, it is effective in the ability to perform shortening for 41 hours which write-in test time shows in the following (3) types as mentioned above. deltaT = T -TA ! (t+m) xn-t ...... (3) -- here, in addition to this, the number of chips in one Wajeha and alpha of time for a self-fiJ opportunity to move [ t ] a chip by one 2 m of test time of only 1 Nap and n are required time (processing time in a position Agreement part, etc.).

[Brief Description of the Drawings]

It is the flow chart for which the surface view of the wafer according [ Drawing 1 ] to one example of this invention, the surface view of the wafer of the former [ Drawing / 2 ], and Drawing 3 showed the test flow chart of WT, and the tiA figure showed Flow n of the wafer within the self-motive in WT test system. As for the wiring for which chip 22 connects a bonding pad, 3 connects a Scra eve fin, and 4 connects a chip 1 in a figure, and 5, a read-only terminal is shown. The same numerals show the same or a considerable portion among a figure. Drawing 1 Drawing 2 Substitution people Oiwa increase construction 3 books (spontaneity)