Manufacture of semiconductor integrated circuit

[Detailed Description of the Invention]

(b) Field of the Invention The present invention relates to the manufacturing method of an integrated circuit, and relates to the manufacturing method of MMIC (MonolithicMicrowave Integrated C1rcuits : monolithic microwave integrated circuit) which can be miniaturized especially. (Ro) PRIOR ART Although the hybrid integrated circuit art of attaching an active device and a passive circuit element on an insulating board is conventionally used for a microwave integrated circuit, M&4IC suitable for small mass-production is put in practical use increasingly in recent years. HEMT (High-Electron-MobilityTransistGr : high-electron mobility transistor), GaAs MES FET (GaAs Metal-3 emiconductor FieldEffect Transistor : metal-semiconductor field effect transistor) or HBT (Hetero-BipolarTransistor) : MMIC using a hetero-bipolar transistor is Media Interface Connector (comparing with hybrid ICs, such as Microwave IntegratedCircuitsl). It is advantageous to a miniaturization and a weight saving, and since it moreover excels in mass production nature and reliability, it is expected as a key device of various kinds of microwave apparatus. ! As a circuit element of 1Media Interface Connector, they are active devices, such as HEMT, GaAs, MESFET, and HBT, In order for there to be passive circuit elements, such as transmission tracks (a microstrip line, a Coplanar track, etc.), a capacitor, an inductor, and A coupler, and to make compatibility of the element of both kinds good, microwave design technique is required as a formation method of these elements. It is common to adjust a passive circuit element in the characteristic of an active device by the simulation using the concentration constant or the distributed constant circuit as the method of microwave consistency. And in the former, DC of the active device of shoes to form on a substrate and the average value of RF characteristic are computed, A simulation is performed based on this average value, the circuit pattern of a passive circuit element is determined uniquely, or a simulation is performed based on the desired value of DC and RF characteristic, and a circuit pattern is determined in 1 matter. and -- forming an active device on a substrate first, when producing the photomask etc. beforehand based on this determined circuit pattern and actually manufacturing an integrated circuit -- the next -- this -- a photomask -- it uses and forms the passive circuit element. (C) When an active device is formed on a substrate at general Prefix which an invention tends to solve, even if it sets to the same formation conditions, between each substrate, the characteristic of an active device changes with variations in a formation process, and even if it is in the same substrate, the characteristic of an active device changes with the formation positions. By therefore, a matching method like before using uniform photomask Bakoon, an active device and passive circuit element -- which compatibility may be unable to be taken, when such, when MMIC is actually manufactured, it will begin, and the irregular affinity of both elements will become clear, and there was a problem that the yield of manufacture was low. There was a problem of taking time too much before being able to measure the one circuit characteristic, since manufacture of Photomask takes days. In the present invention, it is made in view of this situation, the characteristic of an active device formed on a substrate is measured, and it draws directly on resist which applied a circuit pattern of a passive circuit element to a substrate based on this measurement result. Therefore, since a passive circuit element can be formed according to the characteristic of an active device for every A tip, compatibility of both elements can be made into a positive thing for every chip, and it aims at providing a manufacturing method of an integrated circuit which can improve a yield of manufacture sharply. (D) Means for solving problem In the way the 1st invention concerning the present invention manufactures the integrated circuit which has an active device and a passive circuit element on a substrate, The circuit pattern which forms an active device on a substrate, measures the characteristic of the formed active device, carries out the simulation of the circuit pattern of a passive circuit element based on this measurement result, and is acquired by carrying out a simulation is drawn. In the way the 2nd invention concerning the present invention manufactures the integrated circuit which has an active device and a passive circuit element on a substrate, An active device is formed on a substrate, the characteristic of the formed active device is measured, the optimal circuit pattern is chosen from a plurality of circuit patterns of the passive circuit element currently designed beforehand based on this measurement result, and this optimal circuit pattern is drawn. In the way the 3rd invention concerning the present invention manufactures the integrated circuit which has an active device and a passive circuit element on a substrate, An active device and a passive circuit element are formed on a substrate, and the characteristic of the formed active device is measured, Based on this measurement result, the simulation of the circuit pattern of passive circuit element - is carried out, The portion which should compare and change the circuit pattern acquired by carrying out a simulation and the circuit pattern of the passive circuit element already formed on the above-mentioned substrate is determined, and the circuit pattern acquired by above-mentioned carrying out a simulation about this portion that should be changed is drawn. In the way the 4th invention concerning the present invention manufactures the integrated circuit which has an active device and a passive circuit element on a substrate, When an active device and a passive circuit element are formed on a substrate, the compatibility of both the formed elements is evaluated and compatibility is poor, The characteristic of the formed active device is measured and the simulation of the circuit pattern of a passive circuit element is carried out based on this measurement and a result, The portion which should compare and change the circuit pattern acquired by carrying out a simulation and the circuit pattern of the passive circuit element already formed on the above-mentioned substrate is determined, and the circuit pattern acquired by above-mentioned carrying out a simulation about this portion that should be changed is drawn. The 5th invention concerning the present invention forms a plurality of active devices on a substrate, All the active devices which measured the static characteristic of each formed active device by the 1st measurement means, and agreed from this measurement result to the static characteristic standard, The characteristics, such as S parameter, are measured in the 2nd measurement means, and it is based on this measurement result, The simulation of the circuit pattern of a passive circuit element is carried out with a simulation system, and it draws on the resist to which the circuit pattern which determined the desired circuit pattern, respectively and determined it as each active device was applied on the substrate, and forms each passive circuit element. The 6th invention concerning the present invention also makes thickness of a substrate the standard at the time of determining the circuit pattern of a passive circuit element in the invention of the 1.2.3.4th or 5. (Ho) OPERATION In the manufacturing method of the 1st invention, the characteristic of the active device formed on the substrate is measured, and the simulation of the circuit pattern of a passive circuit element is carried out based on this measurement result. And this simulation result is directly drawn on resist. If it does so, the compatibility of an active device and a passive circuit element is good. In the manufacturing method of the 2nd invention, the characteristic of the active device formed on the substrate is measured, and the optimal pattern is determined based on this measurement result out of a plurality of circuit patterns of the passive circuit element by which SS Provision is carried out beforehand. Next, this optimal circuit pattern is directly drawn on resist. When it does so, there is no necessity for a simulation. In the manufacturing method of the 3rd invention, the simulation of the circuit pattern of a passive circuit element is carried out based on the measurement result of the characteristic of the active device which formed the active device and the passive circuit element in the 8th order formed on a substrate first. This simulation result is compared with the pattern of the already formed passive circuit element, and the portion which should be changed is determined. Finally a simulation result is directly drawn on resist only about this portion that should be changed. When it does so and there is no portion which should be changed, an active device and a passive circuit element are formed with a series of formation processes. An active device and a passive circuit element are first formed on a substrate, and the manufacturing method of the 4th invention estimates the compatibility of both the formed elements. When compatibility is poor, based on the measurement result of the characteristic of the formed active device, the simulation of the circuit pattern of a passive circuit element is carried out. And this simulation result is compared with the pattern of the already formed passive circuit element, and the portion which should be changed is determined. Finally a simulation result is directly drawn on resist only about this portion that should be changed. It will be estimated that the compatibility of both elements does so and the integrated circuit excellent in compatibility is manufactured certainly. In the manufacturing method of the 5th invention, the static characteristic of each active device which formed a plurality of active devices on the substrate first, and was formed in the next is measured, and the clue characteristic of all the active devices corresponding to a static characteristic standard is measured. And the measurement result responds, a simulation is carried out, and the circuit pattern of the passive circuit element respectively corresponding to each active device is determined. This determined circuit pattern is directly drawn on resist. Thus, the respectively optimal passive circuit element for a plurality of active devices formed on the substrate is formed, and the integrated circuit excellent in compatibility is formed on a substrate. And to what does not agree to a static characteristic standard if, since the circuit pattern of a passive circuit element is not formed, it can provide accurately and quickly only the integrated circuit which uses the active device of a good-quality item. Even if it is in which such manufacturing method, according to the characteristic of an active device, a passive circuit element is formed for every chip. If it does so, the variation in the characteristic of the formed active device will be canceled, and in all the chips, the compatibility of an active device and a passive circuit element becomes good. In the manufacturing method of the 6th invention, the thickness of a substrate is also used as a standard for determining the circuit pattern of a passive circuit element in each manufacturing method of the above-mentioned 1.2nd.3.4 and 5 in addition to the characteristic of an active device. If it does so, the compatibility of an active device and a passive circuit element will become better. It is EXAMPLE to C. The 2 present invention is concretely explained based on the drawing in which the example is shown below. First, the HEMT MMIC amplifier which used HEMT as the active device is explained as an example about the invention of the 1st of the present invention. Drawing 1 is a sectional view showing the structure of HEMT formed on GaAs board l of half-insulation, On GaAs board 1, non-doped GaAs layer 2, non-doped AlGaAs layer 3, n"AlGaAs layer 4, nGaAs layer 5, and n'GaAs layer 6 are laminated at this order, HEMT is making the composition that n'''GaAs layer 6 formed gate electrode 7 on nGaAs layer 5 by which etching removal was carried out partially, and formed sauce electrode 8 and gate electrode 9 on n"GaAs layer 6. Next, the manufacturing process of this HEMT MMIC amplifier is explained. As first shown in Drawing 1, -IJEMT is formed on GaAs board 1 and the static characteristic and high frequency characteristic of HEMT which were formed are measured in Wafer LOVA. Based on the measured characteristic result, the size of the electrode pattern of a passive circuit element is calculated from simulation G This. Subsequently, this calculation result is inputted into the CAD data of electronic beam exposure equipment or a focused ion beam exposure device. Using these devices, this pattern is directly drawn by the exposure to the resist on substrate l by irradiation of an electron beam or a focused ion beam, and a passive circuit element is formed on substrate l. Under the present circumstances, if it is made not to perform pattern drawing of a passive circuit element to a chip whose characteristic of the measured active device does not suit to a standard, improvement in the speed of fabrication operation can be attained. Drawing 2 (a) shows the graph which shows the frequency distribution of the characteristic of the same HE!ilT MMIG amplifier that is a graph which shows the frequency distribution of the characteristic of the HEMTMMIC amplifier which was carried out in this way and manufactured, and was manufactured with the conventional manufacturing method as a comparative example in Drawing 2 (b). The minimum noise figure [ in / to a horizontal axis / in both graphs / 12 GHz ] NF - Frequency (piece) is shown for (dB) on the vertical axis. If it sets to NFA8. and <=1.7dB as a desired value at 12 GHz, the portion which gave hatching in Drawing 2 will serve as inferior goods. As compared with the conventional example whose rate of inferior goods is 40% or more, in the example of the present invention, the rate of inferior goods is reduced to about 20%, and it is understood that the yield of manufacture has been improved. Next, another example of the present invention which manufactures the 12-GHz belt low noise MMIC amplifier which used FET as the active device is described. Let the single end type amplifier which has a circuit as shown in Drawing 3 as circuit composition be an example in this example. FET first shown in Drawing 3 is formed on a substrate, and the static characteristic and high frequency characteristic of FET which were formed are measured in A wafer LOVA. It is based on the measured characteristic result and is a passive circuit element (Drawing 3 a), i.e., an in-series microstrip line. The shape of a C), parallel microstrip line (3rd [ The ] figure To, d), and shunt capacitor (Drawing 3 C6, CD) and DC cut capacitor (3rd [ The ] figure CC) is derived by a simulation. Drawing 4 is a figure which drawing-ized the circuit pattern drawn in the simulation. In inside G, S, and D of a figure, a gate electrode, a sauce electrode, and the Dorain electrode are shown, respectively, Vao and Voo show a gate device and the Dorain bias, respectively, and sauce electrode S of FET is grounded by the Bahia hall. - The data of the optimal circuit pattern as shown in Drawing 4 is inputted into electronic beam exposure equipment or a focused ion beam exposure device as CAD data, This circuit pattern is directly drawn by the exposure to the resist on the substrate by irradiation of an electron beam or a focused ion beam, and a passive circuit element which was mentioned above is formed. Under the present circumstances, let the length and width of a microstrip line be the optimal value according to the high frequency characteristic of measured FET. The depletion layer which arises by an MIM capacitor or pn junction, and Schottky junction can also be used for shunt capacitor C6, Go, and DC cut capacitor Cc. When capacity changes into a substrate side, When forming an active device (FET), shunt capacitor C6, Co, and DC cut capacitor Cc are also formed simultaneously, When measuring the characteristic of an active device (FET), the capacity of these shunt capacitors C6, Co, and DC cut capacitor Cc is also measured simultaneously, It is good also as deriving the shape of in-series microstrip lines a and C and parallel microstrip lines b and d by a simulation so that it may consistent with these. Next, it explains to per simulation and also details of a circuit pattern by the 1 present invention. S parameter of MESFETI and MESFET2 formed on the substrate, respectively is measured by RF Blowoba. As the measurement result, the data shown in Table 1 and 2 was obtained. The circuit pattern simulation-acquired based on this data is shown in Drawing 4 (b) and (C), respectively. This integrated circuit pattern shows a 1 step of MMIC amplifier, and establishes a consistency circuit in input and output of MESFET. As shown in Table 1 and 2, as for S parameter of ME'5FETI and MESFET2, the phase of Sll is changing and other parameters are the same. What made into the characteristic of the same amplifier as the time of Drawing 4 (c) using MESFETI shown in Drawing 4 (b) (the simulation is carried out.) setting in this example, as shown in Drawing 4 (C) -- inputs -- the distance (figure Nakaya seal A) to FET -- about 0.1 mm -- short -- it is that it is Kakunana. And other output consistency is the patterns with completely same both. (Following space) Table I S parameter table 2 of MESFETI Drawing 5 of S parameter of MESFET2, Thus, as 6 which is a graph which shows the frequency distribution of noise figure NF at 12 GHz of a single end type amplifier as shown in Drawing 3 which manufactured, and profit Ga, in addition a comparative example, The graph which shows the frequency distribution of NF and Ga at 12 GHz of the same single end type amplifier manufactured with the conventional manufacturing method which forms a passive component circuit in the fixed uniform circuit pattern is shown in Drawing 6. If Drawing 5.6 is compared, if it is in the amplifier manufactured in the present invention, as compared with what was manufactured by the conventional method, the average value of the characteristic will improve, distribution will also be small, and improvement of manufacture accuracy will be understood. FET which formed this in each Base plate by the present invention (active device) According to the measurement result of the characteristic, it originates in having formed passive component circuits, such as a proper microstrip line. Next, the example which manufactures uni-Brenner type MMI Into is described. Uni-Brenner type MMIC has a Coplanar track as a basic transmission track, and the compatibility of this passive circuit element barrel Coplanar track and active device barrel FET is a problem. A Coplanar track comprises a central conductor and a surrounding grounding conductor, and can change the characteristic of a Coplanar track according to the width of a central conductor and length, and the distance between a central conductor and a grounding conductor. As a microwave transistor, HEMT of the gate length of 0,511 m and gate width 200um is GaAs-machine-treatment-top-machine-Screening(ed). NH [ in / with the HEMT simple substance at this time / 12 GHz ] is [ 1.l]dB and Ga ] l0dB. Next, the characteristics, such as S parameter of HEMT which ranked next one and was formed which forms the grounding conductor of a Coplanar track according to the length or shape of a Coplanar track beforehand searched for by rough calculation, a constant noise figure circle, and a constant profit circle, are measured in microwave Blowoba or a network analyzer. When the grounding conductor is formed also in the circumference of HEMT at this time, that measurement accuracy improves and it is convenient. Subsequently, the impedance of a consistency circuit according to this measured characteristic result is computed by a simulation. According to this computed pattern, in consideration of the distance from that track width, length, and a grounding conductor, the central conductor of a Cobrena track is formed using the direct drawing methods, such as electron beam exposure, and uni-Brenner type MIilIC excellent in compatibility is manufactured. Next, when forming the capacitor of overlay structure (MIM) as a passive circuit element, the example to which the present invention method is applied is described. It is Based (although forming by one drawing directly is possible, since it becomes overlay structure in a capacitor with large capacity, by one drawing, it cannot form directly.) to the characteristic of an active device which was mentioned above if it was in the smallness capacity capacitor which makes ink Digicle structure. Therefore, such a capacitor is formed by carrying out by repeating drawing directly. The formation process of the capacitor which has such an overlay structure is explained with reference to Drawing 7 showing the section (Drawing 7 (a)) and the upper surface (Drawing 7 (b)) of overlay structure. First, active devices, such as HEMT and MESFET, are formed and the characteristic (a static characteristic, a high frequency characteristic) of each active device is measured. According to this measurement result, the drawing pattern of a series of direct drawing described below is controlled. Lower layer metal 11 is formed on GaAs board 10 of half-insulation using the direct drawing method to resist simultaneously with other tracks or resistance, Next, resist is put and the pattern of a dielectric is directly drawn on this resist, It is made to be or more [ it forms the upper metal 13 on dielectric thin film 12 using the same direct drawing method as the time of forming dielectric thin film 12 which consists of 5i02, SiN, etc. using this pattern, and finally forming lower layer metal 11 ] zero. The capacitor which makes an overlay structure excellent in compatibility with an active device can be formed. By the way, as for a capacitor, there is also a capacitor which used the diode in addition to what makes overlay structure which was mentioned above. Drawing 8 is a sectional view showing the capacitor which used the Schottky barrier diode, and, in inside lO of a figure, as for metal and 22, the GaAs board of half-insulation and 21 are [ an ohmic electrode and 23 ] n layers. When forming an active device, 23 [ zero-layer ] is formed in the ion implantation of one GaAs set treatment Kotono, and the capacitor which has the capacity which is adjusted to this active device is formed after forming an active device. Capacitor capacity C is Like (since it is determined, capacity C of the capacitor to form can be adjusted in an active device by controlling zero layer of bonded surface products (diode area) S of 23 with golden * Genus 21.) of following the (1) type here. C=e and Es -no 2 V+Va+ -S =- (1) e: Electronic charge F, 3: Dielectric Constant N0 of Semiconductor : Impurity Density Vat: Built-in Voltage ■ The example of the capacitor using shot Kibaria reverse bias voltage and p-n junction Guiode is shown in Drawing 9, if shown in Drawing 9 showing the example of the capacitor using a Varactor diode in Drawing 10, 10 is a GaAs board of half-insulation, and 31.32.33 shows metal, p layer, and n layer, respectively -- the -- if shown inO [ 1 ] figure -- ]

0 is a GaAs board of half-insulation -- 41.42.43.44.45 -- respectively -- metal, a p layer layer, n layer, and n -- if it is in such an example that shows 09 layers further It is realization To color about good compatibility [ as opposed to / since the capacity of a capacitor is determined by the bonded surface product of a diode, form two or more capacitors beforehand, control the connection methods (the number, parallel, series, etc.) to a circuit, and / an active device ]. In a manufacturing method which was explained in full detail above, the characteristic is measured about each of each formed active device, Based on this measurement result, the circuit pattern of a passive circuit element is computed in a simulation, and it is supposed that a passive circuit element is formed for every active device based on that calculation result so that the compatibility of both elements may become the optimal. Therefore, the compatibility of an active device and a passive circuit element is always good in each chip, and its yield of manufacture improves. Such a method is very useful when it is going to manufacture especially a trial product (i.e., when producing the module of many quality a small number of [ every ] on the same board). However, since the pattern of a passive circuit element will be directly drawn according to each at resist after computing a circuit pattern with optimal passive circuit element by performing a simulation for every active device in this manufacturing method, there is a difficulty that manufacture of a circuit takes a long time. The method which has canceled such a difficulty is a manufacturing method in the invention of the 2.3.4th of the present invention. In the manufacturing method of the 2nd invention, a plurality of circuit patterns of the passive circuit element computed in the simulation are prepared beforehand, The pattern made the optimal is chosen from the circuit pattern which formed the active device and prepared it based on the measurement result of the characteristic of the formed active device on the substrate, It is the same as that of the 1st invention that is 6 which draws the selected circuit pattern directly to the resist on a substrate, and forms a passive circuit element and that mentioned above the method of drawing in this case directly. And this 2nd invention is applicable to all the examples described as an example of the 1st invention. Although it is inferior for a while by the method of the 2nd invention in respect of such compatibility [ in / as compared with the 1st invention / each active device ], since it is not necessary to perform a simulation after forming an active device, there is an advantage that the circuit which was excellent in compatibility for a short time can be manufactured. Like the method of the 1st invention, if the measurement result of the characteristic is kept from forming a passive circuit element about a poor active device, it is possible to shorten production time. remarkable about degradation of compatibility, if many circuit patterns are prepared according to the class division with the fine characteristic -- grade relief can be carried out. In the manufacturing method of the 3rd invention, after forming an active device and a passive circuit element on a substrate first, the characteristic of the formed active device is measured. And based on this measurement result, a circuit pattern with optimal passive circuit element is computed by a simulation, and the pattern and this simulation result of the passive circuit element already formed are compared, Change draws a change circuit pattern directly to the resist on a substrate only about a required portion. Next, it etches, when reduction in a pattern is required, and when a pattern needs to be added, vapor deposition and liftoff following this are performed. Next, the example of the 3rd invention is explained. First, the example which enlarges the size of the inductor which is a passive circuit element of MMIC is explained based on Drawing 11 showing the process. In Drawing 11, the figure of a left column is an upper surface figure of the process, and the figure of a right column is a sectional view of the process.

After forming the active device and passive circuit element of [C on GaAs board 50, the characteristic of an active device is measured and a circuit pattern with optimal passive circuit element is computed based on this measurement result. This optimal circuit pattern is compared with the circuit pattern of the passive circuit element currently formed, in order to make compatibility of both elements good, it became clear that it was necessary to enlarge the size of inductor 51 (11th [ The ] figure fa) -- the rotation application of the resist 52, such as PMMA and polymethyl methacrylate, is carried out on GaAs board 50 (Drawing 11 (b)). Resist 52a of the field corresponding to the portion which extends the size of an inductor, development is performed after making it expose using electron beam drawing art (11th [ The ] figure fcl) -- metal layer 53 which consists of Ti/Pd/ Au next is vapor-deposited (an organic solvent is used for Drawing 11 (d+) and the last, and it removes with resist 52, and completes expansion of the size of inductor 51.) (Drawing 11 (e)). Next, the example which makes the size of an inductor small is explained based on Drawing 12 showing the process. In Drawing 12, the figure of a left column is a principal surface figure of the process, and the figure of a right column is a sectional view of the process. After forming the active device and passive circuit element of MMIC on G-aAs board 50, That it is necessary to make the size of inductor 51 small in order to make compatibility good it became clear in the simulation based on the measurement result of the characteristic of an active device (Drawing 12 (al) -- the rotation application of the resist 52, such as PMMA and polymethyl methacrylate, is first carried out on GaAs board 50 (Drawing 12 (b)).) Development is performed after exposing resist 52b of the field corresponding to the portion which makes the size of an inductor small using electron beam drawing art (Drawing 12 (C)). Next, it is inductor 51a which consists of Ti/Pd/ Au of the field which needs to be made small CF4 RIE using +0z (Ox : 4%) gas (reactive ion etching) Etching removal is carried out in law (Drawing 12 (d)). Finally an organic solvent is used, resist 52 which remains is removed, and reduction of the size of inductor 51 is completed (Drawing 12 (el).). Although this example explained the example of size change of an inductor, it can completely carry out similarly about size change of other passive circuit elements, such as a transmission track, a capacitor, and A coupler, and can apply this 3rd invention to each example of the 1st invention mentioned above. In the method of the 3rd invention, since a circuit pattern is only changed only about a required portion such after forming an active device and a passive circuit element simultaneously first, when change is not required, there is an advantage that formation of an active device and a passive circuit element can be performed by a series of work. When change is unnecessary, if it sees from the overall standpoint of manufacturing many circuits since compatibility is good, as compared with the 1st invention, the time for manufacture will be shortened in the state of this as. Manufacturing method * of an invention of the 4th of the present invention is explained. In this 4th invention, an active device and a passive circuit element are first formed on a substrate. Then, the compatibility of both elements is evaluated. When consistency is unsuitable, the characteristic of the formed active device is measured like the 3rd above-mentioned invention, Based on this measurement result, a circuit pattern with optimal passive circuit element is computed by a simulation, About a portion to be changed out of the passive circuit element already formed, When expose alternatively and it continues on resist using the direct drawing method, it etches when reduction in a pattern is required, and a pattern needs to be added, it is [ vapor deposition and ] Continuing (liftoff is performed.) to this. This 4th invention is applicable to each example of the 1st invention mentioned above. Since the actual compatibility of such an active device formed in the method of the 4th invention and a passive circuit element is evaluated, good certainty has the compatibility of both the elements in the manufactured integrated circuit higher than the method of the 1.2.3rd invention of the above-mentioned. Since change is not needed when the evaluated compatibility is good, like the 3rd above-mentioned manufacturing method, in such a case, formation of an active device and a passive circuit element can be performed at a series of processes, and the working hours of manufacture can be shortened as a whole as compared with the method of the 1st invention. Next, with reference to Drawing 15, it explains about the method of the 5th invention. GaAs wafer 100 in which HEMT as a plurality of active devices was formed is laid in a Blowoba stand, and pro Ping is performed for the chip in the wafer of ten lots by DC Blowoba lOI. And with DC characteristic measurement system 102, the static characteristics (Idss, gm, Vp, Vr, Vf, n, etc.) of each chip are measured, and the measurement data is inputted into DC measurement data part 103. the control circuit which becomes DC characteristic system 102 from 21 pairs about the data from these apparatus here including a semiconductor parameter analyzer, a capacity meter, etc. -- a system -- and data collection control is carried out and measurement data is outputted. And DC measurement data part 103 memorizes the inputted static characteristic data of each chip. All the chips of DC standard success thing are notified to RF instrumentation system 105 among each of this chip. RF instrumentation system 105 makes Brombing all the chips of DC standard success by RF Blowoba 104, and measures the characteristics, such as S power meter NF and Ga, -- measurement data division 106 -- a time check -- a sex is inputted. Network A realizer to which RF instrumentation system 106 performs S parameter measurement of l boat and 2 port network, NF meter which measures NF and Ga, the synthesized sweeper who waves and outputs power, the tuner which takes consistency of input and output, a power meter, etc. are included -- and The control circuit which consists the data from these apparatus of computers performs a system and data collection control, and it outputs measurement data. It is based on the measurement result of the characteristics of each chip which was inputted into measurement data division 106 and memorized, Microwave simulation part 107 which performs the simulation of a passive circuit element by microwave circuit simulation part 107, As the shape of in-series microstrip line, parallel microstrip line, and shunt gear Bashik and DC cut capacitor is shown in Drawing 4, it derives by a simulation. changing into CAD data the circuit pattern of each chip obtained by this simulation in CAD data creation part 108 -- exposure device control system 109 -- a person -- power is carried out. Exposure device control system 109 draws the circuit pattern directly adjusted to each chip, respectively by the exposure (iio) to the resist on wafer 100 by irradiation of an electron beam or a focused ion beam. Next, the manufacturing method of the present invention mentioned above is explained according to Drawing 16. Drawing 16 is a sectional view in each process of 44Media Interface Connectors. First, as shown in The 16th figure (A), a HEMT operation layer (n"GaAs/ nGaAs/n"AIGnAs) is grown up by the MBE method on GaAs board 611 of half-insulation. n"GaAs is 200 2 X 101a101a thickness, and nGaAs is 5xlQI7cm-" thickness 500 here. People and n"AlGaAs carry out growth formation by the MBE method at 500 2 X 10110l.8" thickness, respectively. Subsequently, as shown in The 16th figure (Ro), in the etching solution which uses photoresist (for example, OMR-83 by TOKYO OHKA KOGYO CO., LTD.) for insulating isolation, and performs Depth 0.5gm Mesa etching and which is used here, they are sodium hydroxide solution and a mixed-solution of hydrogen peroxide solution. Then, as shown in The 16th figure (C), Omic electrode 62 is shaved using the LMR resist by Fuji Chemicals Industrial Co., Ltd., for example to the HEMT section and a resistance part, and it forms by the Footoff method. Vapor deposition metal is Au-germanium(800A)/N1 (100-person 1/2000 Auf(s)), and gives 420degreeC and the ohmic alloy for 90 seconds after liftoff. At this time, manufacture can be completed mostly and the resistance part can search for the ohmic characteristic at this time. As shown in further The 16th figure (D), a shot key electrode is formed in the HEMT section, and it is considered as gate electrode 63. First, TOKYO OHKA KOGYO CO., LTD. make is carried out, Sis l-DEBR-1000M is applied to an Imum layer, and Robertern between 0.4LLII+ is obtained using deepUV light. And recess etching is carried out so that ID5S value for which it asks may be acquired. An etching solution is a mixed-solution of phosphoric acid, hydrogen peroxide solution, and water. Here, it etched so that about 350 residual film thickness might become in Ar. Ti500 person / A16000 person is formed by electron beam vapor deposition as an electrode material after that, and liftoff is performed. S parameter and the noise parameter of the HE M T section are measured in the state of an on-wafer here using RF Blowoba. Based on this measurement result, a simulation is carried out and the numerical value and its pattern shape of a microstrip line required to acquire the MMIC characteristic for which it asks from Cimignile- John, and MIM capacity are decided. If pattern shape is determined as shown in The 16th figure (Ho), lower layer metal 64 pattern of microstrip line 65 and MIM capacity will be formed. Here, as this pattern formation, in order to make an electron beam into the resist applied on the substrate, the liftoff method which used electron beam resist is used. Metal layers 64.65 are 3000 2000 1000 Ti / Pd(s)/Au(s). SiN B Vast 66 of 2000 film thickness performs Passivation after that. Like and the upper metal 67 of Ml and M capacity which are finally shown in The 16th figure (What) are formed like the above-mentioned technique, In order to carry out loss reduction of the microstrip line part, gold plate mouth 8 is given, and MMIC which consists of HEMT section 0. MIM resistance 71. resistance 72 and microstrip line 73 is formed. If it is in the manufacturing method described above, although the circuit pattern of a passive circuit element is computed in the simulation based on the measurement result of the characteristic of each formed active device, compatibility with both good elements may not be acquired only now. It is because the influence of the thickness of substrates, such as GaAs, poses a problem. That is, when the thickness of the substrate differs, even if a circuit pattern is the same, characteristic impedance differs. When the Bahia hall is used, with the thickness of a substrate, grounding conditions differ and it affects the characteristics, such as a short stub. The influence of the substrate thickness in the circuit characteristic is explained. A microstrip line is formed on a GaAs board (dielectric constant epsilonr = 12.5), Although characteristic impedance is about 50ohms when the thickness of 1, for example, a GaAs board, which shows the relation between thick fence mum of a GaAs board and characteristic impedance (omega) in Drawing 13 is 1100u the time of fixing the width (72 or 3 micrometers) of this track, If substrate thickness is changed about ±50%, characteristic impedance will carry out lOomega grade change. (a) shows the case where the thickness of a GaAs board is 120 micrometers, among 1 figure showing the characteristic of a bandpass filter at the time of designing a bandpass filter on a GaAs board in Drawing 14, and (b) shows among the figure the case where the thickness of a GaAs board is 80 micrometers. From the result shown in Drawing 14, change of the thickness of a substrate will understand changing sharply the characteristics, such as Q value of a bandpass filter, or path loss. Generally the thickness of a substrate is maintaining the thick state in consideration of the workability at the time of element formation. However, in MMIC, in order to enable operation in a microwave range by the problem on a miniaturization or the characteristic, it is necessary to make a substrate thin. Then, it is common among the manufacturing process of MMIC to etch the back of a substrate after formation of an active device. Therefore, even if it is in the same wafer, the thickness of a substrate may show variation, or the whole wafer may carry out thinning to it, and in an actual manufacturing process, the error of the thickness of a substrate is about ±20 micrometers. Thus, since this variation has big influence on the circuit characteristic as the variation in the thickness of a substrate occurs in a manufacturing process and moreover being mentioned above, it is required to compute the circuit pattern of a passive circuit element by performing the simulation not only based on the characteristic of an active device but the thickness of the substrate. The method devised by such a situation is a manufacturing method of an invention of the 6th of the present invention, and it is this method, The characteristic of the formed active device is measured and the thickness of a substrate is also the method of computing the circuit pattern of a passive circuit element by measuring and performing the simulation based on the data of both which were obtained, and drawing directly on resist according to this pattern. Of course, it is applicable to the invention of 1.2nd.3 and 4.5 which mentioned this 6th invention above. It is possible to raise the yield more about each from each 1.2.3.4th invention in such each manufacturing method that applied this 5th invention to each 1.2.3.4th above-mentioned invention since the simulation was performed in consideration of thickness in the manufacturing method of the 6th invention. (A) EFFECT OF THE INVENTION As explained in full detail above, the characteristic of each formed active device is measured in the manufacturing method of the present invention, and since the circuit pattern of a passive circuit element is drawn based on the measurement result, a passive circuit element can be formed according to the characteristic of the active device for every ■ chip. As a result, the variation in the characteristic of an active device can be canceled, semiconductor circuit +MMIC which was excellent in the compatibility of both elements can be manufactured, and the yield of manufacture improves sharply. Since the optimal thing is chosen from a plurality of circuit patterns of the passive circuit element formed beforehand by the manufacturing method of the 2nd invention again based on the measurement result of the characteristic of the formed active device, It is possible to manufacture the semiconductor circuit which did not need to perform a simulation and was excellent in the compatibility of both elements for a short time. moreover -- since an active device and a passive circuit element are formed first and a circuit pattern is only changed only about an unsuitable portion in the manufacturing method of the 3rd and an invention of four -- many (about a circuit, an active device and a passive circuit element can be formed at a series of processes.) In the manufacturing method of the 5th invention, the respectively optimal passive circuit element for a plurality of active devices formed on the substrate is formed, and the integrated circuit which was excellent in compatibility is formed on a substrate. and it is what does not agree to a static characteristic standard -- since it is, and the circuit pattern of a passive circuit element is not formed if it carries out, only the integrated circuit which uses the active device of a good-quality item can be provided accurately and quickly. In the manufacturing method of the 6th invention, as data at the time of determining the circuit pattern of a passive circuit element since not only the characteristic of an active device but the thickness of a substrate is applied, much more improvement in the yield of manufacture can be aimed at.

[Brief Description of the Drawings]

Drawing 1 is a section construction drawing of the active device (MMIC) of a HEMT MMIC amplifier which manufactured in the present invention, The histogram which shows the characteristic of each HEMT MMIC amplifier which Drawing 2 manufactured by the present invention and the conventional method, In Drawings 4, Drawing 3 is a representative circuit schematic of FET MMIC manufactured in the present invention, and a Bakoon figure of the transmission track designed based on the characteristic of FET in Drawing 3, The histogram which shows the characteristic of FET MMIC which Drawing 5 manufactured in the present invention, The histogram which shows the characteristic of FET MMIC which Drawing 6 manufactured by the conventional method, Drawing 7 is the upper surface figure and sectional view showing the overlay structure of the capacitor manufactured in the present invention, Drawing 8 is a section construction drawing of the capacitor which used the Schottky barrier diode, the [ the section construction drawing of the capacitor with which Drawing 9 used the p-n junction diode, and ] -- the section construction drawing of the capacitor with whichO [ 1 ] figure used the Balakku diode, The graph which shows the relation of substrate thickness and characteristic impedance, and Drawing 14 are graphs which show the relation between substrate thickness and the characteristic of a bandpass filter. [ in / in the mimetic diagram and Drawing 13 in which Drawing 11 and Drawing 12 show the process of the manufacturing method of the present invention / a microstrip line ] A block diagram for Drawing 15 to illustrate the manufacturing method of the present invention and Drawing 16 are sectional views of each process in the manufacturing method of the present invention. A 1.10.5 O-GaAs board, 51 ... An inductor, 52 ... Resist. Drawing 1 1.2 1.4 L, S 1.8 2.ONFmin (dB) (a) Mourning NFcnFn(dB) (b) 2 Figure CG-VGG Go, Vo. 0 50 Micrometers Toe--> 4 Figure (A) Drawing 4 (B) (Input consistency circuit) (output consistency circuit) Drawing 4 (C) SatoshiJ alpha One Extinction The crawl 1 <= area A gay i twins alpha Off a core -- Si 9 Page 7 figure Drawing 8 Drawing 9 Chopsticks 10 figure E 11 figure ■ 12 Figure Present 13 figure Drawing 14 Drawing 16 Drawing 16