Prioritized information packet switching system

[Detailed Description of the Invention]

Information packet with the semantic priority semi- grade to which the present invention comes out with ON time Multiplex, and plurality is different among time Multiplex, and a time priority unit Switching It is related with a system. Asynchronous time switching The information which is sound, data, a number picture, a report message, etc. in a system is a bit. It is transmitted as a packet and each packet has one bit which sets up the source (source) of a packet, and the direction which should be given to a packet in a circuit. Switching currently indicated by document EP-△-Q 113639 A system is each switching of an asynchronous time switching circuit. It is the best for using as a node (SWltching node). The switching A system has the fixed length of 128 A bit. - Switch a packet with a label of eight bits currently supported as an example by ON Multiplex of 1G linked to appearance Malbup REXX of 16. It is divided into document EP-A-0108028 isochronous [ a plurality of ]. each packet occupies one time, and comes out and is, and it does not convey the information packet supplied from a source -- each time -- an "empty" packet, Namely, Multiplex containing a packet which a fixed label is limited to this type of packet, and cannot be used for information packets. Straffer is indicated. The pattern (motif) of the bit which continues after the label of an empty packet is also a specific pattern. Multiplex is synchronized by an empty packet. Switching currently indicated by document E P-A-0113639 In a system, Engaging of clutch of the new identification specified by attribute (attribut) of the two types, the ON Multiplex number in plurality and the number of appearance Multiplex in the plurality which supplies a new label and a packet to the everybody packet checked with a label, is carried out. If an exception In a manner, it comes out of a packet (e, 1) (e is a number of ON Multiplex, and a Is label), and switches to a packet (s, j) (it comes out s and the number of Maldives REXX and j are new labels). This packet Switching In a system, It is Packett before the 1st action "label conversion" which the control memory programmed at the time of a setup of transmission (it is also called a virtual circuit) performs stores in a buffer memory. - (e) i) it being carried out by receiving, and label (i) being replaced by the label (j), and continuing -- a packet (eSj) -- buffer It is stored in Me and seven persons' known address (decided by write-in time set up by (e)). It is stored in the standby file which this address comes out and is engaging with Multiplex (S). A system is driven by an output, the standby file which comes out at the time of each scanning cycle of appearance Malbub REXX, and is engaging with Multiplex (S) is read, and the address of the new packet which ~ appearance Multiplex (S) should support is generated. Buffer They are [ as opposed to / in Me going up / one ON Maldives REXX (e) ] N memories. Packet which there is a zone and is sent from ON Multiplex (e), Whenever it is crowded 11 in one zone in N zones currently assigned to this person Multipurpose * A cup (e) and a new fortune-telling lump is performed, the inner lump address of a packet is modFormer leaseN. [Increment is carried out. Each memory The writing in a zone is periodic, namely (i+N) if the packet of eye watch is written in, the i-th packet will be destroyed. That is, a packet is a buffer if the time of N packets is exceeded. It cannot continue remaining into a memory. So, buffer at the time of writing Although management of a memory is easy, If appearance Multiplex (S) becomes peak traffic (paintc dCtraffic) (i.e., if the number of packets increases more than average value), It is taken away and the newcomer packet for which it waited time longer than N packet time will break, and an ON packet will disappear. This incident (i nC1dont) is different depending on whether what is transmitted is sound, it is a picture, or it is a message. For example, even if sound is good, its error rate will be larger than a message. On the other hand, when transmitting a certain kind of message, if one packet is lost, an understanding of a message will become impossible. If N is enlarged, this difficulty is cancelable to some extent. however, the thing which production costs will become high if the number of seven Me is increased -- in addition, there is a danger that transmission of others, such as transmission of sound, will be affected. In order to reproduce high wages, packet transmission time in a system must not be made lower than the full limits set up beforehand, and holding time of the packet in each switching system must not be made longer than the time set up beforehand, therefore N must not be enlarged too much. J, P, Quinquis (applicant of this application), H, 5I3rVel, In the system currently indicated by the France patent application [data packet switching system with a priority unit] for which J and rrancOi3 applied to the same day as this application, One in two priority semi- grades is assigned to each package, and a priority semi- grade address is connected to the packet reading address to the Ooguchi file which is engaging with appearance Multiplex, According to restoration; Stand of the standby file, it shifts with reading of the standby file, allowing a disappearance rate higher than an upper-layers Optical level package to a low priority semi- grade package (d (although 3calaO (3) is processed)). Buffer Fortune-telling lump control of a memory is not made an issue of, therefore the holding time in a buffer memory is limited to the scanning time (namely, N "packet time") of this memory. Buffer It is a buffer if write-in control of a memory is complicated. The efficiency of a memory becomes low. namely, the ON packet of a sky -- buffer b buffer which occupies one zone of a memory In seven Me, a zone cannot be re-used, if after [ the last use of a zone ] N "packet time" does not pass after the packet included in a zone is emitted not but. C) They are N memories to everybody Maldives REXX. When the zone is being engaged, if loading of appearance Multiplex is not the same, it will not be said that it becomes ideal distribution, When temporary/local overload which has on appearance Multiplex occurs, big disappearance of a packet is produced. the simple write-in control with which a fortune-telling lump address and old lump time agrees -- buffer the capacity of a memory -- only a part is re-used very much. The basic object of the present invention is A buff by improving write-in control? It is Toward about the efficiency of a memory. - It is providing the system which carries out ♪. Like the after-mentioned, reading processing of the same package with semantic priority semi- grade as what is indicated by the above-mentioned France patent application in write-in control of the buffer memory is combined in the present invention. A packet with time priority semi- grade can also be processed by this control. The maximum buffer set up beforehand When the holding time in a memory is guaranteed to a package, it says that the packet had a high time priority unit, and discharge of a low time priority semi- grade packet is delayable until the overload of appearance Multiplex which should send the packet is canceled. The packet in which the present invention has both highly semantic priority semi- grade and high time priority semi- grade again, Or switching which can process ideally the package which has highly semantic priority semi- grade or high time priority semi- grade again, or the package which has both low semantic priority semi- grade and low time priority semi- grade again It aims at providing a system. As one feature of the present invention, there are two semantic priority units between ON time Multiplex and high time Multiplex, and it is A buff? Information packet stored in the standby file which is engaging with each high time Multiplex where the storing address of the packet of a memory transmits a packet Switching It is at a system and is as one component. Each word of the The state field memory comprises a bit of high time Multiplex and the same number, The address of this point field memory is the buffer. It has agreed with the address of a memory, Each bit of a word is stored in the same address as a word, and the packet which should be sent to appearance time Maldives REXX corresponding to a bit has one highly semantic priority semi- grade, When not sent by attention appearance Maldives REXX yet, it is set to 1, and each packet storing address provides the system chosen from the addresses of the point field memory in which all the bits carry out addressing to the word which is 0. As another feature of the present invention, the packet which has highly semantic priority semi- grade is a buffer. When written in in the address with same memory, Or the packet which has highly semantic priority semi- grade again is a buffer. It is read in the address with same memory, When addressing is written in and carried out between adjacent fortune-telling lump addressing, old lump addressing of the point field memory is carried out, and contents of a word are changed, Each word read by the point field memory when all the bits were set to 0 is freedom f of a buffer memory about the address! It chooses as a lump address. as another feature of the present invention -- each one means address of a point field memory -- free address being stored in a file -- free address the output of a file -- the packet \ i-th place rate -- buffer A seven Me storing address is supplied. As another feature of the present invention, when an ON packet is empty, it is a free address. A memory is not read. It is stored in each standby file which 1st another A bit of the present invention to which the storing address sets the semantic priority unit of a packet if it Features is accompanying, Each Samuraiso file has a low semantic priority semi- grade packet reading address which each file adjoins between the entrance of two zones, and the exit and which is contained in series between two reading, When a fortune-telling lump of the 1st zone is full of the 2nd zone, it can access only a highly semantic priority semi- grade packet, Only the number of times with a low semantic priority semi- grade packet reading address equal to the number of the reading addresses stored in the 1st zone to the utmost stored earlier than the oldest highly semantic priority semi- grade packet reading addresses that still exist in the file is destroyed. The 1st A bit to which the storing address sets the semantic priority unit of a packet as another feature of the present invention, It is stored in each standby file which the 2nd A bit that sets up the time priority unit of a packet is accompanying, or [ each standby file comprising two 7? Il, and storing in the 1st file by the 2nd A bit ] -- the -- it is determined whether to store in 27? Il, all high time priority semi- grade packets are stored in the 1st file, and the 2nd file is not read if the 1st file does not become empty. As another feature of the present invention, each word of a point field memory is equivalent to one bit of an examination memory, The bit is set to 1 when a correspondence word has at least one bit 1, It is read at a rate later than the average stay frequency of bucket 1~ in the Buffeam hips, and bit 1 is a buffer. If written in Me [Ri, the address of the correspondence word of a point field memory will be written in an address file. The data input of a point field memory as another feature of the present invention, It is connected to the selection line which makes a storing address crowded [ among them ] in a Wait Mr. file, this line -- the -- functioning during half a 2 byte time -- a bit write-in enabling input, Similarly in one side, it is connected to the selection line, and is connected to the output of the scanning machine of high time Multiplex in the method of Use, The scanning machine functions during the 1st byte time via the 1st individual AND gate electrical-connection-ized by the semantic priority unit bit sent from the output of the standby file which is sent from a label conversion memory or is scanned again, the address input is connected to the output of the 1st multiplexer -- the 1st [ the ] -- multi--- break -- the 1st human power of an item -- a cycle -- binary Are connected to the output of a counter. The 2nd human power is an address. It is connected to the output of a file and the 1st Marububureli drives by the semantic priority unit bit, the 2nd multiplexer -- the -- drive with half a 2 byte signal, and data output is connected to the partner input of a NAND gate -- the output of the NAND gate -- address Are connected to the fortune-telling lump enabling input of memory *. Address The data input of a memory is a periodic binary. It is connected to the output of a counter and is an address. The data output of a memory supplies a storing address. The above and the above-mentioned unexpected feature of the present invention are further clarified through the detailed explanation of one example of the present invention introduced to below, referring to an appending figure. Switching of Drawing 1 Switching of the type with which the system is indicated by document EP-A-0113639 Although it is a system, The structure of switching circuit (circuit d'aigillage) (A CE), and buffer of a packet The memory (MP) write-in addressing mode is different. Switching of Drawing 1 There are a 160 input joined part (E0~E15) and an output joined part (SO~515) of 16 in a system, and it is a fixed-length packet to each joined part. There is Multiplex (this is as being indicated by document EP-A-0108028). Each in-series byte is changed into a parallel byte, and the input circuit (CE) which delays a start by 1 byte between the human power joined part of one flaming (cadrage) Si The and the next input To the junction for the start of a packet is established in each input joined part (E0~E15). The outputs of an input circuit (GE) are parallel / Diagonal conversion (conversion parallele-diagonale). (Paragonal (paragona+) conversion) It is connected to the partner input of an input rotation matrix (MRE) to perform. By Paragonal conversion, the 1st output of an input matrix (MRE) generates the label of all the packets one by one, and the 2nd output generates the 2nd byte of a packet, and 3rd byte 10. Sequence of an input boat which conveyed the label (1) (rang) Each label (+) which (e) is accompanying is stored in a label conversion memory (MC). A label conversion memory (MC) is a new label (j> is generated and the selection information on one or more standby files which can be set to a switching circuit in another side (S) is generated.) in one side. Although it is that there is nothing to the switching system of Documentary I-E P-delta-0113639, a memory (MC) is a switching circuit (AGE> is supplied.) about two bits (pl) and (p2). If the packet has semantic priority semi- grade if pl is O, and it is 1, it is a packet (it does not have Yo semantic priority semi- grade.). If p2 is 0, the packet has time priority semi- grade, and if it is 1, the packet does not have time priority semi- grade. Therefore, there are the following four kinds of packets. packet A : it also has a semantic priority semi- grade and time priority unit by pl =p2=1 -- Sports -- there is nothing. Although it has semantic priority semi- grade by packet B:pi=o and p2-1, it does not have a time priority unit. Although it has a time priority unit by packet C:p 1= 1 and o2=o, it has both semantic priority semi- grade and a time priority unit by 6 packet o:p1=p2=o without a semantic priority unit. It is A beat, when the label which the conversion memory (M P) changed is a label of a non-empty packet and bit 1 is not so! -0 is impressed to the output line (PNV) of a conversion memory (MP). It is connected to the 1st human power of A buff 1 memory (MP), and the outputs of the memory (MC) which supplies a new label<j> by the line of eight trees are 33 To and a buffer. Other human power of the memory (MP) is connected to the partner output of a matrix (MRE). Buffer connection * The output of the memory (MP) is carried out to the partner input of the output rotation matrix (MP8), The output of the output rotation matrix (MP8) is respectively connected to parallel / serial (P/S) byte converter, and the output of parallel / in-series converter is respectively connected to the appearance terminal area (So~515). Switching of Drawing 1 Central control 2Il machine (UCC) which supplies label conversion information to a memory (MC) according to the virtual circuit further set to a system, Local Bit From Croutta (horloge bitIocae) to a byte There is a hourly base (BT) which supplies a clock and a word (e). - Switching which has an ON terminal area of 16 as an example In the system, a word (e) comprises four bytes. A word (-e) is binary. In a hourly base (BT), it generates with a counter. Binary The first four outputs of a counter generate a word (e), and a counter is a byte. An increment is carried out at the rate (rytme) of a clock. Connection system (aison) (e) (Drawing 1) A word (e) drives an input rotation matrix (MRE), and scans the standby file in IOL and a switching circuit (ACE) for the Human-affiliation part of Me [To (MC). Reverse word obtained by the inverter (I NV) (inverse) (e/) It is sent by the connection system (e/) and an output rotation matrix (MP8) is driven. switching currently indicated by document EP-A-0113639 in which the reading address of the packet is stored considering the Possession Mr. file of 16 of a system -- A buff 1 -- the total number of addresses of a memory (MP) -- 2 -- then The storing capacity of this file of -emaxr is in 2; It will be a buffer if time to be equivalent to 2 at -e-T (T is the scanning cycle time of an appearance boat (S0~S15)) passes. All the packets stored in the memory (MP) are destroyed. Since a king is equal to 2 e-tQ (circumference Ill of a byte clock), he is equal to packet time. according to the present invention -- this difficulty -- it should cancel -- the time of writing -- buffer Memory which the packet which does not carry out addressing of the memory (MP) periodically, but has semantic priority semi- grade already occupies It has a means which comes out of and carries out addressing according to a zone. In Drawing 1, (GM) shows this addressing means as a memory control means. With reference to Drawing 1, multiple connection of Flux S (the line (MSO~MS15) and the line (pl) are comprised) which is by appearance from a memory (MC) is carried out to the partner input of a switching circuit (AGE) and a memory control circuit (GM), and the line (p2) is connected only to the switching circuit (ACE). A switching circuit is a reading address in one side. Word AD (07) is supplied and the bit (pr) which directs whether to be the packet in which the object of a write-in address has semantic priority semi- grade in another side, or there is nothing is supplied. East AD (0-7) and a line (pr) are connected to the partner input of a circuit (GM). The bunch (e) is connected to both circuits (ACE) and (GM). A memory control circuit (MP) supplies a memory (MP) W lump address through a bunch (K) (a word (K) is sent to a switching circuit (80E)). A memory control circuit (GM) is shown in Drawing 2, and a switching circuit (80E) is shown in Drawing 6. The connection system of a memory (MP) and a circuit (AGE) also has two memories (MAR), (A.I. Artificial Intelligence) L, and its drive logic as a basic building block of a control circuit (GM) with reference to Not shown 2 figure. The package with a semantic priority unit to which the memory (MAR) has not been emitted yet is a buffer. It is a memory which directs the state of occupying the memory (MP). Buffer In address (i), in a memory (MP), the 16 same bit words (Zi) correspond to each zone (i) which is a 128-bit arrangement zone of one packet. In a word (Zi), each A beat l- is one appearance joined part (s.). It corresponds to ~515, if the attention packet has a semantic priority unit, a bit is 1, an appearance joined part emits an attention packet, and it is t. [It will not be set to 0 if it kicks. Therefore, when an ON packet writes in, the contents of a memory (MAR) are changed again at the time of reading of an appearance packet. A memory (MAR) is scanned periodically and writing is not only performed, but it supplies a word (Zi) one by one. Address (i) is certainly written in a file (ADL) with all the pits O a word (71). Or -- making it like -- an ON packet -- buffer The address (+) written in a memory (MP) is written in a memory (ADL). So, a memory (ADL) is a buffer in a specific time. Address of a memory (MP) It is a file containing a list. When the output of a file (ADL) is specific, an address (K) is supplied, and the present people packet is stored in the address (K). Like the previously-mentioned, it is a word (K> is sent also to the standby file of the switching circuit (ACE) specified again by the signal supplied to a bunch (S), a line (pl), and (p2) from a conversion memory (MC).). Write-in Atto, Les 7% of Capacity of a file (ADL) can be made comparatively small. The scan of write-in Address Files (while ADL> fills, the output points to a full state, and it is a memory (MAt)) is closed. There are one data input (80E), a plurality of write-in enabling inputs (WO~W15), one addressing input (EAD), and one data output (Zl) in a memory (MAR). There is a line of 16 trees corresponding to 16 A bit of one word (71) in an input (ADE), The line of the 16 trees is a gate (R1) of 16. (it is connected to 0-15>, the 1st human power of the gate (R1) (0-15) is respectively connected to the line (M2O-MS15), and the 2nd human power receives a signal (LJ).) It is O between the halves of the beginning of 1-byte time, and a signal (U) is 1 between next halves. A callback item (U/) is also used for below. The input (wo-w16) is connected to the output of the AND gate (R2) (0-15) of 1G, the 1st human power of the AND gate (R2) (0-15) is connected to the output of an OR gate (R3) (0-15), and multiple connection of the 2nd human power is carried out to the output of the OR gate (R4). the 1st human power of the OR gate (R3) is connected to the output of an ANl gate (R1) (0~15) -- the 2nd human power -- Demarche -- it is connected to the output of 16 of break '+ (Nl), and the data input of a demultiplexer (N1) receives a signal (U/) -- a control input -- a signal (l is received.) The input of the OR gate (R4) is connected to the line (pl) which has come out of the conversion memory (MC), and the line (pr) which has come out from the switching circuit (ACE). buffer the capacity of a memory (MP) is alike two -- it is -- the addressing input (EAD) whose number of a line is k at the time is connected to the output of a multiplexer (N2) The data input (SCPTl) of the multiplexer (N2) is connected to the output of a counter (CPTl), The 1st data input (SCPTl) of the counter (CPTl) is connected to the output of a counter (CPTl), the 2nd data input is connected to the output of another multiplexer (N3), and the flkl control input is connected to the output of an OR gate (R4). The 1st data input of a multiplexer (N3) is filed (it is connected to the output (K) of 80L>, the 2nd data input is connected to the output (△D) (0-7) of a circuit (ACE), and a control input receives a signal (LJ).). A state will be O, if the data output (Zi) of the memory (MAR) with 16 lines is connected to the input of 16 of a NOR gate (R5) and the output of a NOR gate (R5) has bit 1 in the read word (Zi). a file (ADL) -- Multi -- break -- one data input connected to the output of IJ- (N4), One data output (K), one write-in clock input which functions on frequency (frequencc octct) twice the frequency of 2H of a byte, and one write-in enabling ON AJ (there are AE>, a One of a 1-degree file full directions output (EP), and one reading clock input (HL).) The 1st human power of the multiplexer (N4) is connected to the output of a counter (CPTI). A counter (CPTl) is a counter modulo 2. come three-person Khai 4, it is connected to the output of an AND gate (R6), and the input of a counter (CPTl) comes out -- J3 To, The 1st order input of an AND gate (R6) will receive a clock on the 2nd, the 2nd human power (reverse input) is connected to the output (FP) of a file (ADL), and the 3rd human power (reverse input) is connected to the output of OR Gaea 1- (R4). An output (FP) is connected to the 1st human power (reverse input) of an AND gate (R7), and an output of an AND gate (R7) is connected to a control input of a multiplexer (N4) in one side. It is connected to the 1st human power of an OR gate (R8) in another side. The 2nd human power of an OR gate (R8) is N. It is connected to the output of R gate (R5), and the output is connected to the inner lump enabling input (AE) to file (8[). The reading clock input (+-I L) of a file (ADL) is connected to the output of an AND gate (R9), a state is 1 when the label from which two lines (PNV) by which the 1st human power of an AND gate (R5) receives one A 0 Poke, and the 2nd human power is connected to the partner output of a conversion memory (MC) by the line (PNV) were changed by the memory (MC) is not a label of an empty packet. Data output of a file (ADL) is a partner input and a buffer of a switching circuit (ACE) and a multiplexer (N3). It is connected to an input of a register (G). Buffer. An output is [ in / a clock input of a register (G) receives H clock, and / a method of - ] A buff 1. It is connected to an addressing input of a memory (MP), and is connected to the 1st human power of a multiplexer (N5) in another side. The 2nd human power of the multiplexer (N5) is connected to the output of a counter (CPT2), and the output of the counter (CRT2) is connected to the 2nd human power of a multiplexer (N4). The overflow output of the counter (CPT2) is connected to the input (RAZ) of flip 70 grain (BBl), and 1 Set input of flip 70 grain (BBI) is connected to the contact (OLE) periodically energized by a timer (un-illustrating). The output (Q) of flip 70 grain (BBl) is connected to the data input of a flip-flop (BB2), a flip 70 grain (BB2) paste O Poke input receives a signal (H/), and the output (Q) is connected to the control input of a multiplexer (N5). Three outputs (Q) of a flip-flop (BB2) invigorate with the data input of a memory (MEM), and are connected to the 1st human power of an AND gate (RIG) again. 2k to which the memory (MEM) corresponds to the zone of a buffer memory (MP), or the word (Zi) of a memory (MAR) respectively (the 1 A bit word (Y) of Ill is stored.) It is 1 when a bit of a word (Y) does not have a free correspondence zone. It is O when a correspondence zone is free. The damage lump enabling output of a memory (M[EM) receives a signal (A 1), the addressing input is connected to the output of a multiplexer (N5), and data output is connected to the 2nd human power of an AND gate (R10). The 3rd human power of AND Gaea 1- (RIO) receives a signal (1-1/), and the output is connected to the 2nd human power of an AND gate (R7). it can set to the scan of :memory (MAR) which relates the operation principle of the control circuit (GM) of Drawing 2 with the next basic motion, and explains it, an old lump of the packet which has highly semantic priority semi- grade, and the appearance joined part of the packet which has highly semantic priority semi- grade -- reading -- the surveillance of an occupancy state. A counter (CPTI) performs the scan of a memory (MAP). a gate (R6) flows -- Listen (an OR gate (R4) and a signal (FP) are O) -- it shifts, The and a 211-clock signal increment a counter (CPTl), and an output signal (SCPTI) is impressed to the input (0) of a multiplexer (N2). Since the output signal of an OR gate (R4) is 0, a multiplexer (N2) impresses a signal (SCPTl) to the address input of a memory (MAP). Gate (since the 2nd human power is O, R2> (015) flows through neither, but the word (Z i) stored in this address by work of an address (SCPTl) is read.) If one or more bits 1 are contained in a word (Zl), a NOR gate (R5) will not generate a signal, but no writing in a file (ADL) is performed. It is a buffer when only bit O is contained in the read word (Zi). Whether the package stored in the address (SCPTI) of a memory (MP) has semantic priority semi- grade, or]

I hear that appearance joined part Sustained release of the Why was carried out, it is, and a NOR gate (R5) impresses a signal to a file (ADL) 1 lump enabling input (AE) via an OR gate (R8), A file (ADing) receives the same address (SCPTl) sent through a multiplexer (N4) from a counter (CPTI). When the gate (R7) is intercepted, the output signal of the counter (CPTl) impressed to the input (0) of a multiplexer (N4) is transmitted by the multiplexer (N4). Or -- the bucket write-in address which is made like and used later is written in a file (ADL). If a file (ADL) fills, a signal (FP) and (=1) will intercept good The leaves (R6), a gate (R6) stops 211-clock transmission, and a counter (CPT'1) is turned off. Therefore, if a file (80L) fills, a memory (MAP) will go out. A counter (CPTl) is turned off when writing is performed in the memory (MAR) (i.e., also when the output of an OR gate (R4) is 0). If the state of a line (PNV) is 1, it writes in for every H byte time, and an address (K) is read by memory (A.I. Artificial Intelligence) L, It is sent to the write-in addressing input of a memory (MP), and is a buffer. It is sent to a switching circuit (N3) through a register (G), and is sent to input 1 of a multiplexer (N2) through the multiplexer (N3) by which Kaisei is carried out with a control signal (U). Buffer When the packet which should be written in the address (K) of a memory (MP) has highly semantic priority semi- grade, a line (pl) is set to 1, and an OR gate (R4) carries out Kaisei in connection with it, and it sends an address (K) to the address input of a memory (MAP). An AND gate (R1) (0-15) sends the word (ACE) which directs the hint appearance joined part (jonction 5ortantc impliquee) sent from a memory (MC) during the same time (IJ) to the data input of Me [To (MAP). To the last, the word (ADE) is O gate (R3) (it is sent to 0-15>, and Kaisei of the OR gate (R3) (0-15) is carried out by the gate (R4), it passes, and sends a word (ADE) to the partner input of NO gate (R2) (0-15).). Therefore, marking of the write-in enabling input (wQ-w15) corresponding to the appearance joined part (S0~S15) which sends an attention packet is carried out. Therefore, a word (ADE) is written in a memory (MAR) and turns into a word (Z i). If the packet which should be written in does not have highly semantic priority semi- grade, neither of the inputs (wl~W15) is energized, but all the bits are 0 and a word (Zi) continues remaining in the address (K) of a memory (MAR). When the appearance joined part specified by the signal (e/) sends a packet with highly semantic priority semi- grade, The output line (pr) of a switching circuit (ACE) carries out Kaisei of the OR gate (R4), A multiplexer (N3) is an output (AD) (connecting 0-7> to the input (1') of a multiplexer (N2)) of the open circuit (ACE) of a signal (Ll). Therefore, multi-pre Xusano * (N2) sends the reading rear dress (AD) of a packet, and (0-7) to the address input of a memory (MAP), Gate where the demultiplexer (N1) which drives with a signal (e/) corresponds to the hint appearance joined part (R3) (0-15) A signal (U/) is sent. All the gates (R1) (0-15) close between signals (U/), therefore the data input of a memory (MAR) sends the word in which all the bits are O. However, only 0 corresponding to the fortune-telling lump enabling input (wo" - w15) specified by the Kaisei gate (R3) is written in. Therefore, in a word (Zl), the pit corresponding to a discharge Let's go out joined part in a packet with attention semantic priority semi- grade is set to O from 1. If the package which should be sent does not have highly semantic priority semi- grade, a gate (R4) closes, and Kaisei of each gate (R2) (0-15) is not carried out, but a word (Zi) is eternal. This has an important meaning especially, when changing the semantic priority unit of a diffusion packet (paqucts diffuses). In that case, same number as a line (S) of lines (pl) and gates (R4) are required. That is, the composition of the circuit of Drawing 2 is changeable to some extent. The signal (e), signal (K), signal (AD) (0-7) (these three signals are synchronized signals) which direct byte time, The signal (U) which it is O during the first half a byte time, and is 1 during next half a byte time, A signal (pl), a signal (pr), the output signal (SEL) of an OR gate (R4), The output signal (SAD) of a multiplexer (N3), and the output signal (MS) (0-15) of a memory (MC), Gate (R1) (the output signal (ADE) (0-15) and gate (R2> (output signal of 0-15> (the chronogram of W> (0-15) is shown in Drawing 3.))) of 0-15>) It is A buff about the packet with highly semantic priority semi- grade which should be diffused as an example towards an appearance joined part (So), (S5), and (S9)? Loading is carried out to the write-in address (24) of a memory, and it is A buff 1 during the same byte time. The case where come out of the packet with highly semantic priority semi- grade currently written in the address (4) of the memory, and it emits to a joined part (S7) is considered. Therefore, the value of the byte time specified by a signal (e) is 7, and the values of a signal (An) and (0-7) are those with 4 Tooth, and value foil 24 of a signal (K). It is 1 during the 7th byte time, and the signal (pr) of a signal (pl) is the same. Therefore, a gate (R4) generates the opening signal (SEL) (=1) of this byte time. The multiplexer (N3) which drives with a signal (U) generates value 4 of the first foil AD (0-7) in half a byte time, and it generates value 24 of (K) during next half a byte time (signal (SAD)). It lets all the byte time pass, and a signal (MSO), (MS5), and (MS9) are 1 in a bunch (S). All the signals (ADE) (0-15) are 0 during the first half a byte time (U= 0), and a line (ADEO), (ADE5), and (ADE9) are 1 during next half a byte time (U= 1). During the first half a byte time, f multiplexer (N1) supplies gate (R3) (7) 1, and it supplies O to other gates. Therefore, a gate (R2) (7) supplies one during the first half a byte time. This state is (W7), a line (ADE4) is set to O at this time, and the 7th word [ 4th ] A bit is set to 0. In next half a byte time, Gaea 1-(R2) (0), ((R2) 5), and ((8, 2) 9) supply 1, a line (ADEO), (ADE5), and (AD[9) are set to 1, and 11 whites of the address supplied by a signal (SAD) are set to 24. Therefore, address Bit 0.5.9 of a word (71) is set to 1, and other bits of the word continue being O.

it comes out in relation to the scan of [To (MAP), and as mentioned previously, the zone of A buff 7 memory (MP) which semantic priority semi- grade occupies cannot be re-used if A beat 1~ of a word (71) which corresponds to the packet in a memory (MAR) is at O, and there is nothing. ?- '+ if 1ffi file becomes A-puff low or a component (for example, one in gate (R2) (0-15)) causes malfunction, one or more A beat 1~ of a word (-Z) will be reset by Why -- ti -- a person -- there is fear. Although that probability is very small, this type of trouble has an accumulation effect. In the present invention, an attention zone is artificially blocked with a memory (MEM) and a counter (CPT2). except for check time -- the output (Q) of flip 70 grain (BB2), and L -- it is different and the data output of Me [To (MEM) is set to 0. In this state, it is a write-in address (whenever K> is read by the file (ADL), the address is sent to the addressing input of a memory (MEM) by the multiplexer (N5), the correspondence bit of a memory (MEM) is set to 0, and a gate (R10) is set to 0.). If an input (OL E) is energized, the output signal (Q) of 7 A lip 70 grain (BBl) is in time (H/) J3, and a flip-flop (BB2) is To generate about Recopy (recopier) L/and a signal (-1). A state changes and a multiplexer (N5) sends the output signal of a counter (CRT2) to the addressing input of Me F To (M E M). a gate (△7) Recovery the bit scanned in seven Me (MEM) to each time (H/) of every. Whenever the bit is 1, a correspondence zone does not become free but is blocked. A gate (RIO) will change the state of a multiplexer (N4) via a gate (R7), if an output is set to 1 (a file (ADL) assumes that it has not filled). A multiplexer (N4) is a counter (count of CRT2> (namely, a file (address of the zone blocked which ADL> should supply) is sent to the data input of a file (ADL) at the time of the writing of a new packet.)). Or -- it is made like and seven Me (MEM) and a counter (CPT2) block one address with the circuit. The correspondence bit of a memory (MEM) is immediately reset by the output of a flip-flop (BB2) 1. A counter (CPT2) will reset a grain ([3B1) to 0 on overflow One ° Leave flip the 7th, and the check cycle of a system will finish it. buffer the output of a register (G) -- or -- the output of a counter (CPT2) occurs again The signal, the byte who takes the values from zero to 255 Clock signal (1-1), The switching circuit (ACE) which shows the chronogram of the signal which the output (Q) of a 21-1 frequency signal and a flip-flop (BB2) generates in Drawing 4 in Show 1 * figure 5, It comprises the - Honoring circuit (C dish O~CT 15) of 16, one scanning circuit (SCA), and one multiplexer (MX). In; circuit (CT O) where two fixed files and a plurality of logic circuits are in a circuit (CTO~CT15) respectively, they are two files (FSPTO), There is (FPTO), there are circuit (CT1) 1 Il (FSPTI) and (FPTl), and there are a file (FS P T 15) and (FPTl5) in 1.90 circuits (CT15). The Show 1 * circuit (C dish A) is common in Drawing 6 in the circuit (CTO) and the circuit (CTdelta) at Honoring circuit J Why of 16. Data input which receives a signal (rho) in a standby file (FPTO) from a file (ADL) to a word (K), and a label conversion memory (MC), A reading address<s r'o> and the data output which generates a signal (SP), A write-in clock input (HEE), a reading clock input (HL) and an old lump enabling input (deltaF), and CIF 1 - There are enabling human power (AL) and an output (FNVO) which directs that a file is not empty. The signal (SP) is equivalent to the signal (pl) which is engaging with the address (SFO) which appears in the data output of a file (FPTO). Faul (FPTO) is divided into two zones (Z T) arranged in series between data input and data output, and (7 delta). There are an output which directs that the zone (ZA) filled, and an output (PP) which directs that at least one word is contained in a zone (seven dishes) in a file (FPTO). Data input which receives a signal (p l) in a Ooguchi file (FSPTO) from a file (ADL) to a word (K), and label conversion Me t To (MC), It is generating To shake data output about a reading rear dress (SFO') and No. 13 (SP'), It writes in and shifts with a Ri 0 Poke input (A 1F), reading clock human power (H carrying out), and fortune-telling lump enabling human power (AE'). There are an enabling input (deltaL') and an output (FNVO') which directs that a file is not empty. The signal (SP') is equivalent to the signal (pl) which is engaging with the address (SFO') which appears in the data output of a file (FSPTO). The file ("SF'TO) is divided into two zones (21') and (ZA') which are arranged in series between data input and data output. There is directions J Output (FPN') in a file (FSPTO) about being [ which directs that the zone (ZA') filled ] the output, and at least one word being contained in a zone (ZT'). Bunch (S) (116 lines (MSO~M S 15) are comprised and the circuit (CTO~C 1-15) is engaging with each line respectively.) The line which transmits a signal (pl) is common to the partner input of a circuit (CTO-0 dish 15). the data output (SCO-8C15) of a circuit (CTO~C15) -- each Multi -- break (it is connected to the input of 16 of J (MX), and the output of a multiplexer (MX) generates No. 131 (pr) with the reading address to a buffer memory (MP).) An output (FNVO) and (FNV'O) are respectively connected to the partner input of a scanning circuit (SCA). In the circuit (SCA), the input (FNVO~FNV15) is respectively connected to the input of 16 of a multiplexer (MNV), The output of the multiplexer (MNV) is connected to the data input of a flip-flop (VP), and the Tulloch input of a flip-flop (VP) receives a signal (HD). Flip-flop (VP) and (7) output (Q) generates Trust s (SVP), and is connected to the input of a demultiplexer (DMF), and the output of 16 of a demultiplexer (DMF) supplies a signal (VSO~VS15) to a circuit (CTO-CT15) respectively. The control input of a demultiplexer (DMF) and a multiplexer (MNV) receives a signal (e) and (BTl) respectively. In the circuit (to SC), input (FNV'O~FNV'15) 1. is respectively connected to the input of 16 of Ma jLrf-7 recreation"f (MNV'), The output of multi-Brek (MNV') is connected to the data input of flip 70 grain (VP'), and the clock input of flip 70 grain (VP'') receives TrustM (HD). The output (Q) of a flip-flop (VP') generates a signal (SVP'), and is connected to the input of a demultiplexer (DMF'), and the output of 16 of a demultiplexer (DMF') supplies a signal (VS'0" - VS'15) to nu way (CTO~CT15) respectively. The control input of demulti Prek tJ- (DMF'') and multi-Brek (MNV') receives a signal (e) and (BTl) respectively. Three inputs (AE) of a file (FPTO) invigorate, and are connected to the output of an AND gate (Pl), the 1st human power of the AND gate (Pl) is connected to the line (B-2), the 2nd human power is connected to the line (MSO), and the 3rd human power is connected to the output of a NANr gate (B-2). The 1st contrary input of a gate (B-2) is a line (it is connected to pH and the 2nd contrary input is connected to the output (FPN) of a file.). The output (PP) of a file is connected to the signal input of flip 70 grain (B1) in one side, It is connected to the input of inverter (I) in another side, and three outputs of inverter (I) invigorate, and are connected to the 1st human power of AND Gaea 1- (B3), the 2nd human power of the AND gate (B3) is connected to the output (SP) of a file, and the 3rd human power receives a signal (HL). The output of gate - (B3) is connected to the input (RAZ) of a flip-flop (B1), and the clock input of flip 70 grain (B1) is connected to the output (VSO) of a demultiplexer (DMF). The output (Q) of the flip-flop (B1) which sends a signal (881) is connected to 1 Set input of flip 70 grain (B-2), the signal input of flip 70 grain (B-2) is O, and the clock input of flip 70 grain (B-2) receives a signal (Hl). The output (Q) of Fritzbuch 1 Kozub (B-2) who sends a signal (ppl) is connected to the signal input of a flip-flop (B3), and the clock input of flip 70 grain (B3) receives TrustM (HD). In the output (Q) of flip 70 grain (B3) which sends a signal (pp2), it is connected to the 1st human power of an AND gate (B4), and the 2nd human power of an AND gate (B4) is a signal (it is To receive about SP>.). The output of the gate (B4) is connected to the 1st human power of an OR gate (B5), the 2nd human power of the OR gate (B5) is connected to the output (VSO) of a demultiplexer (DMF), and the output of a demultiplexer (SMF) is shifted. It is connected to the enabling input (AL). The input (AE') of a file (FSPTO) is connected to the output of an AND gate with 3 human power (as for one, two are an order input by an inversion input) (P'1), The reverse input of the AND gate (P'1) is connected to the line (B-2), the 1st order input is connected to the line (MSO), and the 2nd order input is connected to the output of a NAND gate (P'2). Gate (the 1st contrary input of P'2> is connected to the line (pl), and the 2nd contrary input is connected to the output (FPN') of a file.) The output (PP') of a file is connected to the signal input of flip 70 grain (81') in one side, It is connected to the input of inverter <■° in another side, and three outputs of an inverter (■°) invigorate and are connected to the 1st human power of an AND gate (P'3), The 2nd human power of the ANI gate (P'3) is connected to appearance h of a file (SPo), and the 3rd human power receives a signal (HL). The output of the gate (P'3) is connected to the input (RAZ) of a flip-flop (R'l), and the clock input of flip 70 grain (B'1) is connected to the output of an AND gate (P6). The 1st order input of good 1- (P6) is connected to the output (VS'0) of a demultiplexer (DMF'), and the 1st inversion input is connected to the output (VSO) of a demultiplexer (DMI"). The output (Q) of flip 70 grain ([3'l) is connected to 1 Set input of a flip-flop (B'2), the signal human power of flip 70 grain (8 degrees2) is 0, and a flip-flop ([3'2) paste 0 Poke input receives No. 18 (HD). The output (Q) of the flip-flop (B'2) is connected to the signal input of a flip-flop (B'3), and the clock input of Noritsu 70 grain (B'3) receives a signal (HD). The output (Q) of the flip-flop (B'3) is connected to the 1st human power of an AND gate (P'4), and the 2nd human power of an AND gate (P'4) receives a signal (SP'). The output of the gate (P'4) is connected to the 1st human power of an OR gate (P'5), the 2nd human power of the OR gate (P'5) is connected to the output of a gate (P6), and the output of an OR gate (P'5) is shifted. It is connected to the enabling input (delta1- *). It is connected to the 1st human power of an AND gate (P7) (0-9), and eight data output lines and output lines (SP) of the Phung Il (F P T O) are AND good - (P7) (the 2nd human power of 0-9> is connected to the output (VSO) of a demultiplexer (DMF).). The data output line and output line (SP") of file (FSPTO) 8 tree are To connect h T a3 To and an AND gate (P'7) (the 2nd human power G, the tAND gate (P6) of 0-9> (connected to D output (VSO).)) to the 1st human power of an AND gate (P'7) (0-9) (7). Multiple connection of the output of a gate (P7) (0-9) is respectively carried out to the input of the multiplexer (MX), eight outputs of multi-Brek (MX) read, an address (AD) and (0-8) are transmitted, and the 9th output transmits a signal (or) (0(P'7)-9). the time diagram of a signal (HE), (1-IL), (IID), (K), (BTl), and (e) -- the -- the [a / 7 / figure and ] -- it is shown in an 8a~12a figure. The cycle of a signal (hO) is switched. Bit of a system It is twice the cycle of a clock. It is sent by four lines and the increment of the signal (e) is carried out every four cycles of every byte time, i.e., (hO). It is supplied by a file (△DL), and is read at the rate of a byte clock (I"), therefore Truste (K) is a signal (Bribery of K> changes synchronizing with the increment of a signal (e).). a word (K) -- an isolation rate ---like (quasi-aleatoire) -- the write-in address which changes from O to 255 is set up. A signal (1-I D) is high-level between the first two bit time of byte time, and it is Loule Bell between six more bit time. The signal (HL) is following only 2-bit time from the signal (HD), and, as for a signal (+-I E), only 2-bit time is from a signal (HL). - It is progressing. Although the increment of the signal (8T1) sent by four lines is carried out for every byte time, he has followed only half a byte time from the signal (e). The temporal duration of the signal (MS) sent from a memory (MC) and (015) is 1-byte time respectively. As an example, when a signal (MSO) is 1, a circuit (CTO) advances the write-in request to one file, and when a signal (MSO) is 0, a circuit (DTO) is written in and does not advance a request. If are suited more concretely and a write-in request will be advanced, writing will be performed in the standup edge (front montant) of a signal (1"E). As shown in Drawing 6, only in a file (FPTO) or a file (F S P T O), the writing of a packet reading address is performed according to the value of the bit (p2) which sets up a time priority unit. when (p2) is 1, it is an AND gate (Pl) -- 1 A -- an input (AE) -- high Since it can be made a level, an address (K) is written only in a file (-FPTO). When (rho 2) is O, an address (K) goes old lump enabling only into the file (FSTPO) into which an AND gate (P1') puts Acceptance. therefore -- only the address of a packet with high time priority semi- grade goes into a file (FTPO) -- a certain thing t Up quantity semantic priority semi- grade in this packet -- Simultaneously U To have -- things are made. Although only the address of a packet without time priority semi- grade goes into a file (FSPTO), a certain thing in this package can have highly semantic priority semi- grade. Regardless of whether the attention packet has a high window '' Taste theory priority unit regardless of the state of a signal (pl), since the output of a NAND gate (P2) is 1, only when a signal (FPN) is 0, the writing of a file (FPTO) is enabled (p2=1 >.). Writing is performed by signal <1-IE in which a gate (Pl) will carry out Kaisei if a line (MSO) is set to 1, and the writing of the word (K) to a file is enabled, it rises in the center of byte time with a signal (8E), and an edge appears. If it is directed that the signal ('FPN) was set to 1 and the zone (ZA) of a file (FPTO) filled, and a line (pl) is not set to 1, the output of a gate (P2) will not be set to 1. therefore -- if the attention packet does not have highly semantic priority semi- grade (p=1> write-in enabling <AE=1) and it is -- To -- [ -- it is -- . Although the word (K) which corresponds to the packet with highly semantic priority semi- grade, and is sent to an output (SO) is written in a file (FPTO) and shifted, it exists in a zone (seven dishes). In this case, even if the word (K) corresponding to a packet with low semantic priority semi- grade has high time priority semi- grade, it is not written in a file (FPTO), but the contents of this bucket 1~ stored in the memory (MP) disappear. The same may be said of the file (FSPTO), and if a zone (ZA') fills, a signal (FPN') will enable the writing of only a packet with highly semantic priority semi- grade by an AND gate (P2'). A signal<'e> is 4 A bit. It is a word and the value is a byte. It changes to 0 (0000) to 15 (1111) at a rate, a line (FC15~FCO) is scanned, and it lets a multiplexer (MX) pass, and is a buffer. It reads to a memory (MP) and sends an address. A signal (BTI) is also 4 A bit. Although it is a word and the same value as a signal (e) is taken, only half a byte time is 31! It is by lupsilon. A treat of a signal (BTl) -- next, it explains. Some loading of a file (FPTO) and (FSPTO) Before examining a case, the Work 1jl principle of a scanning circuit (SCA) (Drawing 6) is explained. All of a file (F, PTO) and (FSPTO) shall not be empty probably. In this case, 2 Horn output (FNVO), (FNV'O);t; it is 1 both. When a signal (BTl) is set to 0000, a signal (FNVO) and (FNV'O) are each /z Ma Itf. - It is sent to flip 70 grain (VP) and (VP') by Brez+j (MNV) and (MNV'). Flip 70 grain (VP) and (VP') Rikobi- this signal (=1) by the standup marginal smell of signal ()-I D. a signal (SVP) and the figure of (SVP') with the passage of time -- the --a [ 7 ] figure -- Not shown. (e) When set to =OO00, a signal (SVP) and (SVP'') are Sending rail to an output (VSO) and (VSO') by a demultiplexer (DMF) and (DMF') respectively. A signal (VSO) (=1) intercepts a gate (P6), and is sent to an OR gate (P5) and an AND gate (P7). Shift The signal impressed to the enabling input (carrying out) is set to 1, and an AND gate (P7) impresses an address word (deltaD) (0-7) and a bit (SP) to a multiplexer (MX), Since the signal (e) impressed to the control input of a multiplexer (MX) is 0000, a multiplexer (MX) is an address word (deltaD> (0-7) and a pit (SP) are passed.). As being shown in the rVso/All chronogram of the 7th the a figure (a item (AL) being 1 between byte time (e) =OOOO(s)), * by which the word to which the shift in a file appears in a line crack and the output of a file (F P T O) on the standup edge in within a time [ this ] (+10) is replaced by a following word. On the other hand, the gate (P6) is intercepted and does not set the input (AL') of a file (FSPTO) to 1. Therefore, the word which appears in the output of a file (FSPTO) is not emitted by the multiplexer, and a shift is not performed in a file (FSPTO). The file (FPTO) is empty this time and it considers the case where a file (FSPTO) is not empty. A signal (FNVO) is 0 and a signal (FNVO') is 1. As operation of a multiplexer (MNV), (MNV'), Fritz Frob (VP), (VP'), a demultiplexer (DMF), and (SMF'), in time (e) =0000, a signal (VSO) is 0 and a signal (VS'O) is 1. Therefore, an input (AL) is still O, a gate (P7) (0-8) is intercepted, Kaisei is carried out, an input (AL') is set to 1 in connection with it, and a gate (P'7) (0-8) carries out Kaisei of the gate (P6). A multiplexer (MX) shifts on the (HD) standup edge, and lets an appearance J To word pass to the output of a file (FSPTO). After all, the address in a file (FPTO) has time priority semi- grade higher than the address in a file (FSPTO), and the address in a file (FSPTO) is not read through a multiplexer (MX), if a file (FPTO) does not become empty. A signal (SP) and (SP') are processed by a multiplexer (MX), and become a signal (pr), and a signal (pr) is used for the write-in operation to a state memory device (MAP) as it mentioned previously, while referring to Drawing 2. next, six [of a file (FPTO) -- a kudzu -- a - Ding case is introduced and the disposal method of high / packet with low semantic priority semi- grade in the packet is clarified. - As an example, it is Active. The storing capacity of a zone (7A) shall be 16 words (not restricted to this). The storing capacity of a middle zone (ZT) shall be 8 words as an example. Six [1-Ding cases of a file (FSTPO) are similarly processed in the present invention, and the detailed explanation is doubled with it of a file (FPTO). the -- 10-Ding the [ about a case ] -- as shown inb [ 7 ] figure, in a file (FPTO), three words (A), (B*), and (C) shall be written in in order (a rate -- highly semantic priority semi- Position word Somewhat -- things are shown) Therefore, in this case, a signal (FPN) is 0 and a signal (FNVO) is 1. In all the 7? Il, a word (A) and a bit (SP) are in the output of a file so that that may be right, and this is a word (A> means existing in the correspondence input of a gate (P7) (0-8) which carries out Kaisei at the time of time (e) =1111.). In this byte time, contents of a word (A) are the outputs (AD) (sent to the reading address input of a memory (MP) from 0-7>.) of a multiplexer (MX). An input (AL) is set to 1 by a signal (FNVO) how, It is as having mentioned previously that a shift occurs in a file, a word (△) is replaced by work of (HL) standup edge by a word (B-) during byte time e= 1111, and a word (C) occupies the 2nd position. the [ therefore, / this ] -- in 10-Ding case, a word (A) is read through a multiplexer (MX) and emitted by shift from a file (FPTO). In byte time e= oooo, a multiplexer (MX) sends the word read by one in the file of a circuit (C-r15) as a figure shows at the time of (AD) (0-7) A of the 7th the a figure. the --a [ 8 ] figure -- the -- 20-Ding the [ which shows a case ] --b [ 8 ] figure -- three of files (FPTO) -- one by one -- the time of Hyde -- 1ito (e= 1110) and to+ 1 (E= 1111) and t O+ the state in 2 (e=oooo) -- Showing. In time 10, the standby zone (ZA) is full, a word (delta), (B), (C*), and (X*) are contained, and a word with highly semantic priority semi- Crying (P*) is contained in the middle zone (7T). the -- three serial time toSto+1 and to+2 are shown also ina [ 8 ] figure. Like the 78th and the case shown inb [ 7 ] figure, if time is set to to+1 from to, a word (A) will be read through a multiplexer (MX), will be emitted from a file in the termination of time t O+-1, and will be replaced by a word (B). This is state 10 A 1 of the 8th the b figure. In time 10, a signal (PP) and a signal (FNVO) are 1. If (e) 11111.: Becomes, a flip-flop (B1) will receive a signal (VSO) from a multiplexer (DMF), will Recovery a signal (PP) and (=1), and will be set to 7 A lip 70 grain (B-2) Chi 1 by (SBI). In time to+1, on the <1-1l.->standup edge, when a sand straw word (A) is emitted from a file, a 7 Lipship O grain (B3) Recovery the state (ppl) of a flip-flop (B-2), and sets a state (pD2) to 1. In time to+2, the gate (B4) whose signal (SP) is 1 since the word (8) taken and replaced does not have priority semi- grade in a word (A) therefore whose two inputs are 1 maintains a signal (AL) to 1 through an OR gate (B5). Therefore, a word (B) is emitted by the shift of a file (FPTO) in the next standup edge of a signal (HL), and the termination of Sort of time to+2. the [ therefore, ] -- the contents of a watch To inform file are (0), (X-), and (2) inb [ 8 ] figure at n end of Do not show profit time 10 A 2. In time to+1, a signal (e) is 1111, Since the file (FPT15) (or FSPT15) is connected to an output (AD) and (0-7) by the multiplexer (MX) through the gate (B7) (0-7) (or P'7 (0-7)), a word (B) has not passed the multiplexer (MX). Therefore, buffer The packet stored in the address (f3) of a memory (Mr') is not sent to an appearance joined part (SO). When this packet is to be sent only to this appearance junction a;, it is destroyed completely, but when making it be to be spread to a plurality of joined parts other than (So), it continues remaining in the fFtIll file which is engaging with these joined parts of a plurality of. Word (if A> is emitted from a file (FPTO), a word (P*) will move to a standby zone (ZA) from a relay zone (ZT) at the time of a circumference, and a signal (PP) will be set to O.) And since a word (8) does not have highly semantic priority semi- grade, the output and signal (SP) of inverter (I) are set to 1, and it the (HL) [ next ] Rises, it sets green, and the output (RAZ) of a gate (B-2) sets a 7 A lip 7O grain (B1) to O. In a following ()-I D standup edge, the flip-flop (B-2) whose data input is O Recovery this state, and 7 A lip 70 grain (B3) Recovery this state in the next (A ID) standup edge, i.e., the termination of time tQ+1. Or -- it will be made like, a zone (ZT) will become empty in the start edge of time t O--2, and flip-flop (B1) (B3) ~ will be in hibernation altogether -- the -- a circuit (CTO) continues functioning like the 1st case shown in 7a andb [ 7 ] figure. In tQ+17 between rIS(s) (un-illustrating), a word (C-) is read through a multiplexer (MX), and it is emitted from a file (FPTO). the --a [ 9 ] figure -- the -- 30-Ding the [ which shows a case ] --b [ 9 ] figure -- three serial byte time tO (e= 1110) of a file (Fr'TO), tO+1 (E==1111) and t O+2 (in rt and 10 between s which show the state in e =0000>, the standby zone (ZA) is full, and it is a word (A-) and (8) (C 9.)) (X-) is contained and a word (P*) is contained in the relay zone (ZT). the -- three serial time to, to+1, and to+2 are shown also ina [ 10 ] figure. If time is set to to+1 from 10, a word (8*) will be read through a multiplexer (MX), will be emitted from a file in the termination of time ↑0+1, and will be replaced by a word (B). This is in state 10+1 of the 9th the b figure. In time 10, a signal (P P') and a signal (FNVO) are 1. a flip-flop (81) receiving a signal (VSO) from a demultiplexer (DMF), if ei> is set to 1111, and Recovery(ing) Trust'j (-pP) (=1) -- (S[31) -- 7 A lip 70 grain (B-2) -- 1 -- Serra]- it is carried out. In time tQ+1, on the (+-I L) standup edge, when In other words word <delta One is emitted from a file, a flip-flop (B3) Recopy the state (ppl) of a flip-flop (B-2), and sets a state (p p, 2) to 1. In time tQ+2, since the word (B) taken and replaced does not have a priority unit in a word (A*), a signal (SP) is set to 1, therefore the gate (B4) whose two inputs are 1 maintains a signal (△L) to 1 through an OR gate (B5). Therefore, a word ([3) is emitted by the shift of a file (FPTO) in the next standup edge of a signal (A IL), i.e., 49 Q of time to+2. However, a word (B) does not pass a multiplexer (MX). Therefore, the contents of the file kicked J3 to the termination of time tO+-2 are (0), (X-), and (P*). In time to+17. (un-illustrating), a word (0) is read through a multiplexer (MX), and it is emitted from 7? Il. Initialization of flip-flop (B1) (B3) ~ is performed like the case of the 2nd above-mentioned case. the [ therefore, ] -- 30-Ding a case -- the -- 20-Ding Although it is almost the same as a case a file (FPTl) when If+ of a signal (e) is set to i -- < -- or the state of FSPT i -- not related the word which appears in the output of a file is read through a multiplexer (MX) regardless of whether it has semantic priority semi- grade -- a package -- buffer I thought it useful to explain the motion which comes out of seven Me (MP) and it sends to a joined part (S i), when you understand J To. the --a [ 10 ] figure -- the -- a 40-Ding case -- the [ Show 1 ] --b [ 10 ] figure -- four serial byte time to (e = 1110>) of a file (FPTO) to+1 ()E-1111 to-+-17 (GJ State is shown in e=1111> and tO+18 (e=oooo).) In time 10, the Special machine zone (Zdelta) is full, and they are a word (A), (8), and (C) (D> and (X) are contained and a word (P) with a priority unit is contained in the relay zone (ZT).), the -- four serial time to, to+1, tO+17, and to+18 are shown also ina [ 10 ] figure. If time is set to to+1 from to, a word (A) will be read through multi-Blechner (MX), and in nfA of time to+1, it is emitted from a file, and is a word with a priority unit (replaced by eight.). In time 10, a signal (PP) and a signal (FNVO) are 1. (e) receives 1111 D htH, f flip-flop (B1) receives a signal (VSO) from a demultiplexer (DMF), a signal (PP) and (=1) are Recovery(ed), and 7 A lip 70 grain (B-2) is Serra 1 to 1 by (SB1). - It is carried out. In time t O+1, it is (HL) standup edge, namely, when a word (A) is emitted from a file, 7 A lip 70 grain (B3) Recopy the state (ppl) of a 7 Lipship [I grain (B-2), and A state ta (p p 2) is set to one. Word (since the word (B*) taken and replaced with A> has a priority unit, Trustg (SP) is set to O, therefore the output of a gate (B4) is maintained by 0 and reset by signal (deltaL) O through an OR gate (B5).) Therefore, in the next standup edge of signal ()-I L, it is a word (B are not emitted.) to tQ+17. Although a signal (PP) is reset by 0 during this time and the 1st human power of a gate (B3) is set to 1, Since a word (B-) is a word with priority semi- grade, a signal (SP) is set to O, a flip-flop (B1) is not reset by the input (RAZ) at O, but the state of flip 70 grain (B-2) and (B3) is eternal. In time [ when (e) is set to 0000 ] to+17, a word (8) is read through a demultiplexer (MX), No. 18 (VSO) is set to 1, word < 13 One is emitted by work of (MNV), (VP), and (DMF), and a word (C) appears in the output of a file in time tQ+17 by it. rubbing as that by which no word was written in the file between time 10 and time to+17 -- the [ t and / [] -- the [ which is shown in 8a andb / 8 / figure ] -- it returns to 10-Ding case. a word (C) -- time t Q+33. -- it is set [ it is alike and ] and read. Especially, in time to+17, since (PP) is O, a signal (VSO) changes the state of 7 Lip flow (B1). Therefore, in time to+18, a flip-flop (B-2) and (B3) are reset by O. the --a [ 11 ] figure -- the -- the [ which shows a 50-Ding case ] --b [ 11 ] figure -- four serial byte time tO (e= 1110) of a file (FPTO), and to+1 (E = the state in 1111>, to+2 (e=oooo), and to+3 (c= 0001) is shown.) Between [ to ] 111, the standby zone (7A) is full, a word (A), (B), (C), (D), and (X) are contained, and two words with a priority unit (P*) and (Q*) are contained in the relay zone (seven dishes). the --a [ 11 ] figure -- four serial time tQ, tQ+-i, to+2, and t Q+3 -- Not shown. If time is set to t Q11 from 10, a word (delta*) will be read through a multiplexer (MX), will be emitted from a signal (VSO) (=1) file in the termination of time to+1, and will be replaced by priority-semi- grade-less To B. Therefore, although a word (P*) goes into a zone (ZA) in time t O+1, a word (Q*) remains in a zone (7T). In time 10, it is TrustQ. (PP) and a signal (FNVO) are 1. (e) -- 1111 -- Ds -- if -- a flip-flop (B1) Recovery a signal (PP) and (=1), flip 70 grain (B-2) is set to 1, and a flip 7O grain (B3) is also continuously set to 1 (the previously-mentioned passage). Word taken and replaced with a word (△*) (since [3> does not have a priority unit, a signal (SP) is set to 1 and a gate (B4) maintains a signal (delta carrying out) to 1.) Therefore, in time tQ+-1, a word (B) is emitted by the shift of a file on the (HL) standup edge. during this time -- a word (Q continue remaining in a relay zone (ZT), and a signal (PP) is maintained by 1 -- therefore, 7 A lip 70 grain (Bl) and L -- it is different and the state of a flip-flop (B-2) and (B3) is maintained.) In time tQ+3, since a word (C) does not have priority semi- grade, a signal (SP) is maintained by 1, and gate <B4 maintains a signal (AL) to 1 too. Therefore, it is emitted, without word CC also passing a multiplexer (MX) in (HL) standup edge. In the termination of time to+3, in order that a word (Q-) may go into a zone (ZA), a signal (r'P) is reset by 0. and -- flip 70 grain (B1) ~ (83) is initialized as previously-mentioned -- the -- 10-Ding Operation is performed as a case. the --a [ 12 ] figure -- six loading a case -- the [ Showing 1 ] --b [ 12 ] figure -- five serial byte time to (e= 1110), to+1 (e= 1111) and to+2 (e = the state of the file (FPTO) in 0000> and to-1-17 (e= 1111) and to+18 (e=oooo) is shown.) In time 10, the standby zone (ZA) is full, and they are a word (delta*), (B), and (C*) (D). (X) is contained and they are two words (P-L (Q-) is contained.) in a relay zone (ZT). They are five serial byte time t O (e = 1110>, to+1 (e= 1111), to+-2 (e= 0000), t O A 17 (e= 1111), and tO+18 (e= 0000) is shown.) toa [ 13 ] figure. If time is set to to+1 from 10, a word (△*) will be read through a multiplexer (MX), will be emitted from a file by a signal (VSO) (=1) in the termination of time to+1, and will be replaced by a word (B) and (an II-point-semi- grade-less word). Therefore, although a word (P*) goes into a zone (ZA) in time [0+1, a word (0) continues remaining in a zone (Z T). In time to, a signal (PP) and a signal (FNVO) are 1. If (e) is set to 1111 in time to+i, in Ri] B, flip 70 grain (81) will carry out a signal (PP) and (=1), flip 70 grain (B-2) is set to 1, and flip 70 grain (B3) is also continuously set to 1 (the previously-mentioned passage). H Since the word (B) taken and replaced with a word (8*) does not have priority semi- grade, a signal (SP) is set to 1 and a gate (B4) holds to a signal (AL) to 1. Therefore, time t O+ In 2, a word (B) is emitted by the shift of a file on the (HL) standup edge. the word in this time (8*) continues remaining in a relay zone (ZT), and a signal (PP) is maintained by 1 -- flip 70 grain (Bl) and L -- it is different and the state of a flip-flop (B-2) and (B3) is maintained. In time to+3< un-illustrating, since a word (C*) is a word with a priority unit, a signal (PP) is set to O, and a gate (B4) is intercepted. Therefore, word (without being emitted in (HL) standup edge in time tQ+3, in time tQ+17, C will be read through a multiplexer (MX), if a demultiplexer (DMF) carries out bullfighting of the signal (VSO) to A 1 again 1111 in (e).) Time is carried out, a word (Q-) goes into a zone (ZA) in O-2, a zone (ZT) becomes empty, and a signal (PP) is set to 0. therefore -- being related with reading of a word -- the -- 10-Ding It returns to a case. However, the signal which a signal (VSO) does not appear only in time tQ+17, but directs that a word (C-) is a word with a priority unit (since it is continued by intercepting SP> (=1) a gate (B3), the flip-flop (B1) continues operating.) Therefore, it is signal (SB1) and (ppl)(+) B-2 G Yo sure 1 under time tQ+17. the -- 8a. while referring tob [ 9 ] figure -- the -- 20-Ding Shin f3 (VSO) resets a flip-flop (B1) to hibernation, and the state of flip 70 grain (B-2) and (B3) applies correspondingly as the case was explained -- To a close. -Loading introduced to F A word new during processing was premised on not going into Off ? Il at all in the case. Since one word 2: Is crowded for every by]-time when sending a penetration packet to an attention appearance joined part, it is clear that there is no unreasonableness in this premise. Six upper loading By reading explanation of a case, circuits (CTO~CT15) are these six loading. Completely processing a case in a similar manner will be understood. In the example of the switching circuit shown in Drawing 6, it is Trust@. The line which transmits (pl) is common to the partner input of a circuit (Di0~CT15). Switching When sending the packet which goes into a system only to only one appearance joined part, it is a part for"- by the line of one tree. When diffusing namely, sending a penetration packet to a plurality of appearance joined parts by each line of a bunch (S), it means that the line (pl) packet has or has high priority semi- grade to no appearance joined parts. a semantic priority unit is given to a diffusion packet to a specific appearance joined part, and it is made not to give t Yo semantic priority unit to it to other appearance joined parts -- being alike -- 16 trees are individual -- 1 (pI) must be connected to an each circuit (CT O~CT 15). Package of others [ Easy / to which the zone (ZA) of a file (FPTi) (FSf/ or /] Ti) has filled with the packet address with a semantic priority unit ] It is this PacketI- when an address arrives. An address is not emitted. However, by devising A set of traffic conditions, if the case of an accident is removed, probability that such a trouble will occur can be made very small. It switches about this. 2i11all machine NCC of a system is used whenever a virtual circuit is set up, therefore it is necessary to care about recognizing the average load of each appearance joined part. When there are too many communications with highly semantic priority semi- grade requested to one appearance joined part, System till (UCC) sorts out a specific setup in it, and prevents a blockade (engorgement).

[Brief Description of the Drawings]

Drawing 1 is a packet of the present invention. It is a block diagram of a switching system. Drawing 2 is a buffer of the present invention. It is a lineblock diagram of a memory control circuit. Drawing 3 is a chronogram which shows the operation principle of the state memory device of the control circuit of Drawing 2. Drawing 4 is a chronogram which shows the operation principle of the safety circuit (circlit de 5ecurisa mouth on) of the control circuit of Drawing 2. Drawing 1 switches Drawing 5. Switching of a system It is block diagram Durham of a system circuit. Drawing 6 is a processing circuit lineblock diagram of the system circuit shown in Drawing 5. the -- a 7a~12a figure is Indication 11.1 figure about various loading cases of two control files of the processing circuit of Drawing 6. the -- a 7b~12b figure -- the [ each ] -- it is a figure corresponding to a 7a~12a figure -- loading the contents of an attention standby file change according to a case -- Indication size. Member name Switching circuit: 8C "bucket buffer Me [To (MP) input joined part: EO~[15 Output joined part: SO~315 input circuit 2 -- CE Input rotation matrix: MR[E Label: i - sequence: e Label conversion memory: New label: j Selection information: S A beat l-: pl, 12 Bad thing i-: △, [3, C, D output Fll:PNV Output rotation matrix: Parallel / in-series byte converter: P/S medium-fire controller: UCC-word: e reverse sorting:e/ Inverter: INV - Flux: S line: MSO~MS15 FIl:pl, p2 seven Me system illegal circuit 2GM Write-in address Word: AD Flux (0-7): AD (0-7) -FA:pr Flux: K - word : Memory: MAPlADL Zone: i - word: Z; Address: i - A file: ADL appearance crab FP - data ON crab ADE addressing people crab [EAD Data output = Zi Gate: R1 (0-15) a connoisseur -- ON crab U/ AND gate: R2 (0-15>) OR good 1~:R3 (0-15>) OR gate: R4 AND gate: R1 (0-15) False-rumor Luxe Package 2N10R gate: R4 Marubou -- break To meet: -- N2 data ON crab S CP T 1 Counter: CPTl Multiplexer 2N3 Data output =71 TrustR and LJ ORA niece-1~ Appearance crab K NOR Gaea h:R5 Multi-Prek IJ:N/I Fortune-telling lump enabling: 8E the amount crab [of file full directions -- 1 old lump clock ON crab HL AND gate: -- R6 8Nl gate =1<7 OR gate: R8 It is Not and is gate:R5. AND good 1- : R9 Buffer Register: G Multiplexer 2N5 Power-Ninta:, CRT2 Person crab RA Z - contact: CLE appearance crab O Noritsu Bufu rope BBI, 2.3 signal: -- H/ Seven - Me: MEM△ND gate: -- R10 Word: Y F P Output signal Si Cormorant: S - Trust';5 (PTI) : Address: 5CPT1 Control A ts 5''5: LJ It writes in - address 2 and is enabling people crab WO-w15. Signal: SdeltaD AD[ - Trust Si i:Ms (0-15) (0-15>) No. 111 : Signal: W (0-15>) Line AtE: (0-15>) Processing circuit: CTO~CT15 File: FSPT-FPT Appearance crab FNVO-7 dress: SFO zone: ZTSZ△ -appearance crab PP t; lump address: SFO' Signal: sp' Old lump enabling people crab AE' shift enabling ON crab deltaL. Appearance crab FNVO' Zone: deltaT', Z△. Appearance crab FPN' Flip-flop: VP Trust J?J : 11 D - A ij Yo s:svp Demarububureli: DMI-multiplexer: MNv signal: e -t3 T 1 - circuit: -- eight SC(s) crab FNV'O~FNV'15 Multi plexor: -- MNV' -- Noritsu 70 grain: -- vp' Signal: svp' False-rumor Lubblek 1 To: DMF' Trust F3: VS'o-vs'1s NAND gate :P 2 Gate :P 3 AND gate :P 4 OR gate :P 5 AND gate :P '1 NdeltaND gate :P '2 Appearance crab r'p' Noritsu 70 grain: B' 1.2.3 AND gate = P'3 AND gate :P 6 AND gate: l'4 0R Gaea 1-:r'5 Gate :P 6 It passes and is NO gate :P 7 (0-9) AND gate :P A '7 write-in (0-9) address: AD (0-8) signal: -- hO - signal: 'SVP and SVP -- word:A (Ne) and B(*) C(-) X (Ne) ON crab AE'