Bypassing system in matrix switch

[Detailed Description of the Invention]

[Summary of the Invention] It aims at bypassing at high speed and transmitting the high-speed detour method packet data of the matrix switch in the case of transmitting packet data to a receive buffer from a transmission buffer at high speed using a matrix switch, The packet transfer controlling part which inputs packet data and adds a buffer address and a detour place buffer address at the time of normal, The packet transmission way to which the output data of the packet transmission upsilon1wJ section is transmitted, Two or more receive buffers which receive the packet data transmitted from the packet transmission way, It is constituted by the signal wire which transmits the packet abandonment signal from a receive buffer, and is the above-mentioned packet transfer controlling part, The buffer address at the time of normal and the time of a detour is added to a packet, and it is the above-mentioned receive buffer, Packet data will be taken into an internal memory, if the packet data sent from a packet transmission way is supervised and it checks that self is a buffer at the time of normal, Only when a memory overflowed, a packet abandonment signal is sent out and it checked that self was a detour place buffer, and a packet is taken into an internal memory and the above-mentioned packet abandonment signal is received, processing which does not discard this packet is realized by hardware.

[Industrial Application] The present invention relates to the high-speed detour method of the matrix switch in the case of transmitting packet data (only henceforth a packet) to a receive buffer from a transmission buffer at high speed using a matrix switch. Since the packet exchange network which transmits data to the unit called a packet collectively has good compatibility with bursty data, it has spread as a computer network widely. However, in order to transmit these data certainly without an error, they are an obstacle and the detour to wipe and which is depended for meeting, Since it was controlling by software in order to process complicated procedures, such as resending etc. of error detection, abandonment, routing, and the packet that was discarded or disappeared, high-speed data transfer was impossible. The research and development which are going to realize high-speed data transfer prosper in recent years by on the other hand realizing processing conventionally realized by software among exchange processings of a packet by hardware.

[Description of the Prior Art] Drawing 7 is a figure showing the system configuration example using the matrix switch by the conventional hardware. Transmission buffer 4 by which receive buffer 2 which receives the packet from a terminal/circuit transmits a packet to output-packets transmission way (N pieces) 3 in a terminal/circuit is connected to input packet transmission way (N pieces) 1, respectively. Transmission buffer 5 is connected to the intersection of input packet transmission way 1 and output-packets transmission way 2. And in input packet transmission way 1, it is input packet transmission! Output-packets transfer controlling part 7 is connected to output-packets transmission way 3 for 6 111 copies of II(s), respectively. Drawing 8 is a figure showing the example of a format of a packet, and is constituted by an addressee address and data. The system constituted in this way exchanges data as follows. ■ Input packet transfer controlling part 6 polls receive buffer 2, and performs transmission instruction of a packet to receive buffer 2 in which a packet exists. ■ Input packet transfer controlling part 6 analyzes the address information which the packet outputted from receive buffer 2 has, and performs reception directions to applicable transmission buffer 5. ■ Output-packets transfer controlling part 7 performs data transfer to output A buff 74 by the same method as ■ and ■. Here, analysis of the address information on ■ and ■ is conducted by referring to the look-up table to which the address of a buffer applicable using the address information which a packet has is outputted, and is physically constituted by the memory.

[Problem(s) to be Solved by the Invention] Although exchange operation of a packet is [ a matrix switch which was mentioned above ] realizable at high speed, in order to transmit without checking the state of the buffer (transmission buffer 4) of a transmission place, Transmission buffer 4 overflowed, and when it was not able to receive, there was a problem of transmitting a packet to the buffer by generating of an obstacle in spite of being when packet reception of the buffer of a transmission place is impossible. The present invention is a method aiming at offer of the matrix switch which can But as if data transfer is performed correctly, without being made in order to solve the above-mentioned subject, and losing data in such a case.

[Means for solving problem] Drawing 1 is a principle block diagram of the present invention. The packet transfer controlling part which 11 inputs a packet and adds a buffer address and a detour place buffer address in a figure at the time of normal, and the packet transmission way to which 12 transmits the output data of the packet transfer controlling part 11, Two or more receive buffers which receive the packet to which 13 is transmitted from the packet transmission way 12, and 14 are signal wires which transmit the packet abandonment signal from a receive buffer.

[Function] packet transfer controlling part 11 -- an input packet -- each at the time of normal, and the time of a detour -- a buffer address is added and outputted. Each receive buffer 13 supervises the packet of packet transmission way 12, compares with the buffer address of self the buffer address added to the packet, and recognizes whether self is a buffer at the time of normal, or it is a buffer at the time of a detour. At the time of normal, at the time of a buffer and a detour, although a buffer takes in packet data and performs data transfer processing to a terminal / circuit, or an output-packets transmission way, when an internal memory overflows during this processing, it outputs a packet abandonment signal and discards this packet. For example, at the time of normal, by a buffer, when #j is a buffer at the time of a detour, the receive buffer of #i will perform data transfer processing instead of #i, if #j receive buffer receives the packet abandonment signal from #i via signal wire 14. When an abandonment signal is not received at this time, it considers that the buffer at the time of normal received, and the buffer for a detour discards this packet. Thus, exact data transfer can be performed at high speed, without losing a packet.

[Example] Hereinafter, with reference to drawings, the example of the present invention is described in detail. Drawing 2 is a figure showing the example of composition of packet transfer controlling part 11. As shown in a figure, it comprises shift register 11a, look-up table 11b, and header adjunct 11c. It goes into shift register 11a, the analysis of an address is completed, and a packet generates delay until a buffer address is outputted. At this time, an address is latched and goes into look-up table 11b. As shown in Drawing 3, when [ normal ] an address is received, a buffer address is memorized by look-up table 11b at the time of a buffer address and a detour. When [ normal ] an input address is received, a buffer address is outputted at the time of a buffer address and a detour. Header adjunct 11C is a switch concretely, generates delay until the output of a Baza address is completed from a look-up table by shift register 11a, and outputs data, A buffer address is added by change at the time of a buffer address and a detour at the time of normal from look-up table 11b, and it sends out to packet transmission way 12. Drawing 4 is a figure showing the example of a format of the packet which did in this way and was created. It turns out that the buffer address is added to the head section at the time of a buffer address and a detour at the time of normal. Drawing 5 is a figure showing the example of composition of receive buffer 13. The same thing as Drawing 1 attaches and shows the same numerals. As shown in a figure, it comprises receiver 13a, shift register 13b, counter 13C, memory 13d, driver receiver 13e, self-address comparison machine 13f, pointer control part 130, and fault detection part 13h. 15 is a signal wire which transmits the signal which shows the boundary of a packet. The packet received with receiver 13a goes into shift register 13b. On the other hand, counter 13c counts the packet boundary signal from signal wire 15, recognizes the head of a packet, generates the timing signal which shows the head of a packet, and gives it to self-address comparison machine 13f. Self-address comparison machine 13f compares the self-address built in with the address data from shift register 13b to the output timing of counter 13C, and recognizes whether self is a receive buffer at the time of normal, or a receive buffer at the time of a detour. First, the case where self is a receive buffer at the time of normal is explained. In this case, self-address comparison machine 13f participates reception directions in a pointer system and 1111 copy 13g. The pointer control part 13g has three pointers, and two of them express the head address of the packet read in response to the packet boundary signal now, and the write-in address which is ends. It is an address specifically given to memory 13d, and gives the address of the memory which writes in the packet sent by receiver 13a. The one remaining pointers are addresses read from a memory, and detect overflow from the difference of a read-out address and a write-in address. Abandonment of a packet is performed by replacing the present write-in address with the head address of a packet. If overflow occurs during bucket writing or an obstacle occurs, an abandonment generating signal will be sent to driver receiver 13e. At this time, driver receiver 13e is set to normal by normal / detour select signal of self-address comparison machine 13f, and a packet abandonment signal will ride on signal a14 by considering it as a receiver at the time a driver and for a detour at the time for normal. Also when fault detection part 13h detects a certain obstacle, the signal which shows the same abnormalities as signal wire 14 rides, and it is shown that it cannot receive. Next, the case where self is a receive buffer at the time of a detour is explained. In this case, a receive buffer recognizes that self is a buffer for a detour by the same operation as the above-mentioned. And it is supervised whether a packet abandonment signal is sent, setting driver receiver 13e to a receiver, and receiving this packet. When the packet abandonment signal has been sent via signal wire 14 * driver receiver 13e at this time, Pointer control part 139 discards this packet by same pointer operation, when it has been recognized by the counter which is supervising the packet boundary signal that received the packet as it was, and an abandonment signal was not received, and transmission of the packet was completed. Drawing 6 is a key map of the present invention of operation. (A) (0) shows the time of a detour for the time of normal, respectively. First, the time of normal is explained. Buffer address m is added by packet transfer controlling part 11 at the time of buffer address j and a detour at the time of normal, and the packet which entered in the forms of address Ai and data is sent out to packet transmission way 12. Although data is inputted into both receive buffers j and m, since buffer j ends reception at the time of normal, buffer m discards the received packet at the time of the detour which a packet abandonment signal issues. On the other hand, since a packet abandonment signal comes out from buffer j at the time of normal at the time of a detour, in response, buffer m performs the usual processing at the time of a detour. Therefore, also when a detour is needed, high-speed transmission is possible.

[Effect of the Invention] Since the present invention is constituted as mentioned above, even when the obstacle which will be obeyed occurs, the matrix switch which can transmit a packet at high speed can be provided.

[Brief Description of the Drawings]

The figure in which Drawing 1 shows the principle block diagram of the present invention, and Drawing 2 shows the example of composition of a packet transfer controlling part, the figure in which Drawing 3 shows the example of composition of a look-up table, the figure in which Drawing 4 shows the example of a format of a packet, the figure in which Drawing 5 shows the example of composition of receiving A buff ?, and Drawing 6 are key maps of the present invention of operation, The figure showing the system configuration example using the matrix switch of the former [ Drawing / 7 ] and Drawing 8 are figures showing the example of a format of a packet. As for a packet transfer controlling part and 12, in Drawing 1, receiving A buff? and 14 are signal wires a packet transmission way and 13 11.