Semiconductor device and manufacturing method thereof

The present invention relates to a display device using an oxide semiconductor and a manufacturing method thereof.

Thin film transistors formed on flat plates such as glass substrates, as typified by liquid crystal display devices, are made of amorphous silicon or polycrystalline silicon. Thin film transistors using amorphous silicon have low field-effect mobility but can be adapted to large-area glass substrates, while thin film transistors using crystalline silicon have high field-effect mobility but require a crystallization process such as laser annealing, and are therefore not necessarily suited to large-area glass substrates.

In response to this, attention has been drawn to techniques for fabricating thin-film transistors using oxide semiconductors and applying them to electronic devices and optical devices. For example, Patent Documents 1 and 2 disclose techniques for fabricating thin-film transistors using zinc oxide or In-Ga-Zn-O-based oxide semiconductors as oxide semiconductor films and using them as switching elements in image display devices.

<p><patcit num="1"><text>Japanese Patent Application Laid-Open No. 2007-123861</text></patcit><patcit num="2"><text>Japanese Patent Application Laid-Open No. 2007-096055</text></patcit></p>

<p>An object of the present invention is to provide a structure and a manufacturing method thereof in which electric field concentration that may occur between a source electrode and a drain electrode is alleviated and degradation of switching characteristics is suppressed in a bottom-gate thin film transistor.</p><p>Another object is to provide a structure that improves coverage of an oxide semiconductor layer and a manufacturing method thereof.</p>

<p>A bottom-gate thin film transistor has an oxide semiconductor layer on a source electrode and a drain electrode, and the angle θ1 of the side surface of the source electrode in contact with the oxide semiconductor layer and the angle θ2 of the side surface of the drain electrode are set to 20° or more and less than 90°, thereby increasing the distance from the upper end to the lower end of the electrode on the side surface of the source electrode and the drain electrode.</p><p>One configuration of the invention disclosed in this specification is a semiconductor device including: a gate electrode over a substrate having an insulating surface; an insulating layer over the gate electrode; a source electrode and a drain electrode over the insulating layer; and an oxide semiconductor layer overlapping the gate electrode and the insulating layer between a side surface of the source electrode and a side surface of the drain electrode facing the side surface of the source electrode, with the insulating layer interposed therebetween; and an angle formed between a surface of the substrate and the side surface of the source electrode and an angle formed between the surface of the substrate and the side surface of the drain electrode are greater than or equal to 20° and less than 90°.</p><p>The above configuration solves at least one of the above problems.</p><p>Although it depends on the metal material used for the source and drain electrodes, a natural oxide film is formed on at least the side surfaces of the source and drain electrodes. This natural oxide film is formed when the electrodes are exposed to an atmosphere containing oxygen, such as the air, after etching. Furthermore, a natural oxide film is also formed on the side surfaces of the electrodes when the film formation atmosphere contains oxygen when an oxide semiconductor layer is formed after etching.</p><p>In addition, in order to prevent the formation of a natural oxide film on the electrode surface, a buffer layer (n⁺It is preferable to successively deposit the buffer layer (also referred to as a buffer layer) without exposing it to the air. The buffer layer is an oxide semiconductor layer having lower resistance than the oxide semiconductor layer, and functions as a source region or a drain region.</p><p>In the above structure, a buffer layer is provided on the top surfaces of the source electrode and the drain electrode, and an oxide semiconductor layer is provided on the buffer layer.⁺By successively depositing the oxide film (also called the oxide layer) without exposing it to the air, the formation of a natural oxide film on the top surfaces of the source and drain electrodes is prevented.</p><p>In a bottom-gate thin-film transistor, when a voltage sufficiently higher than the threshold voltage is applied to the gate electrode to turn it on, the path of the drain current (the current path in the channel length direction) first runs from the drain electrode through the oxide semiconductor layer near the interface with the gate insulating film and reaches the source electrode.</p><p>Note that the channel length of a bottom-gate thin film transistor having an oxide semiconductor layer over a source electrode and a drain electrode corresponds to the shortest distance between the source electrode and the drain electrode, and is the distance of the oxide semiconductor layer sandwiched between the source electrode and the drain electrode and near the interface with the gate insulating film.</p><p>n⁺When a layer is formed on the top surface of the drain electrode and the source electrode, if the conductivity of the native oxide film formed on the side of the electrodes is low, the main path of the drain current is from the drain electrode to the n⁺through the oxide semiconductor layer near the interface of the drain electrode side, through the oxide semiconductor layer near the interface of the gate insulating film, through the oxide semiconductor layer near the interface of the source electrode side, and⁺The oxide semiconductor layer obtained by sputtering tends to have a film quality near the interface with the surface on which it is deposited that is affected by the material of the surface on which it is deposited.⁺The oxide semiconductor layer has at least three interfaces with different materials: an interface with the native oxide film on the side surface of the drain electrode, an interface with the side surface of the source electrode (and the side surface of the drain electrode), and an interface with the gate insulating film. Therefore, in the oxide semiconductor layer, the interface state with the native oxide film on the side surface of the drain electrode is different from the interface state with the gate insulating film, so the oxide semiconductor layer near the interface with the side surface of the drain electrode functions as a first electric field concentration relaxation region. Also, the interface state with the native oxide film on the side surface of the source electrode is different from the interface state with the gate insulating film, so the oxide semiconductor layer near the interface with the side surface of the source electrode functions as a second electric field concentration relaxation region.</p><p>In this manner, the regions of the oxide semiconductor layer that overlap with the side surfaces of the source electrode and the drain electrode function as electric field concentration relaxation regions.</p><p>The oxide semiconductor used in this specification is InMO₃(ZnO)_mA thin film represented by (m&gt;0) is formed, and a thin film transistor is fabricated using the thin film as a semiconductor layer. Note that M represents one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M may be Ga, or may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. Furthermore, some of the oxide semiconductors contain Fe, Ni, or other transition metal elements, or oxides of these transition metals, as impurity elements in addition to the metal element contained as M. In this specification, this thin film is also referred to as an In-Ga-Zn-O-based non-single-crystal film.</p><p>The crystalline structure of the In-Ga-Zn-O based non-single crystal film is observed to be amorphous in XRD analysis. The In-Ga-Zn-O based non-single crystal film analyzed was formed by sputtering and then heat-treated at 200°C to 500°C, typically 300 to 400°C, for 10 to 100 minutes.</p><p>The angle θ1 of the side surface of the source electrode and the angle θ2 of the side surface of the drain electrode that are in contact with the oxide semiconductor layer are set to 20° or more and less than 90°, and the distance from the upper end to the lower end of the electrode on the side surface of the source electrode and the drain electrode is increased, thereby increasing the length of the first electric field concentration alleviation region and the length of the second electric field concentration alleviation region, thereby alleviating electric field concentration. Furthermore, the distance from the upper end to the lower end of the electrode on the side surface of the electrode can also be increased by increasing the film thickness of the source electrode and the drain electrode.</p><p>Furthermore, when the oxide semiconductor layer is formed by sputtering, the thickness of the film formed on the side surface of the electrode perpendicular to the substrate surface may be thinner than the thickness of the film formed on the top surface of the electrode. By setting the angle θ1 of the side surface of the source electrode and the angle θ2 of the side surface of the drain electrode in contact with the oxide semiconductor layer to be 20° or more and less than 90°, the uniformity of the film thickness can be improved even on the side surface, and electric field concentration can also be alleviated.</p><p>1, if a line extending from the lower end of the side surface of the source electrode to the upper end of the side surface of the source electrode approximately matches the slope of the side surface of the source electrode, the source electrode can be said to have a tapered shape, and the angle θ1 formed between the substrate surface and the side surface of the source electrode can be called the first taper angle.If a line extending from the lower end of the side surface of the drain electrode to the upper end of the side surface of the drain electrode approximately matches the slope of the side surface of the drain electrode, the drain electrode can be said to have a tapered shape, and the angle θ2 formed between the substrate surface and the side surface of the drain electrode can be called the second taper angle.</p><p>Furthermore, the electrode side surface is not limited to a shape having one angle, and the electrode side surface may have a step as long as at least the angle θ1 of the side surface of the lower end of the source electrode and the angle θ2 of the side surface of the lower end of the drain electrode are 20° or more and less than 90°.</p><p>Another aspect of the present invention is a semiconductor device comprising: a gate electrode on a substrate having an insulating surface; an insulating layer on the gate electrode; a source electrode and a drain electrode on the insulating layer; and an oxide semiconductor layer overlapping the gate electrode and the insulating layer between a side surface of the source electrode and a side surface of the drain electrode facing the side surface of the source electrode, the side surface of the source electrode being opposite to the side surface of the drain electrode; wherein an angle formed between a surface of the substrate and a side surface of a lower end of the source electrode and an angle formed between the surface of the substrate and a side surface of the lower end of the drain electrode are 20° or more and less than 90°.</p><p>In the above configuration, the angle formed between the substrate surface and the side surface of the lower end of the source electrode is made different from the angle formed between the substrate surface and the side surface of the upper end of the source electrode. Also, in the above configuration, the angle formed between the substrate surface and the side surface of the lower end of the drain electrode is made different from the angle formed between the substrate surface and the side surface of the upper end of the drain electrode. Note that the cross-sectional shapes of the side surfaces of the source electrode and the drain electrode facing each other across the oxide semiconductor layer are substantially identical because they undergo the same etching process.</p><p>For example, the angle of the side surface of the lower end of the source electrode (and drain electrode) may be made different from the angle of the side surface of the upper end of the source electrode (and drain electrode), and the angle of the side surface of the upper end of the source electrode (and drain electrode) may be set to 90°. By making the angle of the side surface of the upper end of the source electrode (and drain electrode) larger than the angle of the side surface of the lower end of the source electrode (and drain electrode), the spacing between the masks for forming the source electrode and drain electrode can be designed to be narrow, and as a result, the channel length can be designed to be short, for example, the channel length can be designed to be 1 μm to 10 μm.</p><p>Furthermore, the side shapes of the source electrode and the drain electrode may have at least a partial curved surface. For example, in the cross-sectional shape of the source electrode and the drain electrode, the lower end of the electrode may also have a curved surface determined by the center of the radius of curvature located outside the electrode.</p><p>The side surface of the source electrode and the drain electrode may have a cross-sectional shape that widens from the upper surface of the electrode toward the substrate.</p><p>The electrodes having the various cross-sectional shapes described above can be formed by dry etching or wet etching. Etching equipment used for dry etching includes etching equipment using reactive ion etching (RIE) and dry etching equipment using high-density plasma sources such as ECR (Electron Cyclotron Resonance) and ICP (Inductively Coupled Plasma). Furthermore, compared to ICP etching equipment, dry etching equipment that can more easily achieve uniform discharge over a large area includes an ECCP (Enhanced Capacitively Coupled Plasma) etching equipment, in which the upper electrode is grounded, the lower electrode is connected to a 13.56 MHz high-frequency power supply, and the lower electrode is connected to a 3.2 MHz low-frequency power supply. This ECCP-mode etching equipment can also handle substrates, such as 10th-generation substrates with a size exceeding 3 m.</p><p>The source electrode and the drain electrode may be a single layer, or may be a multi-layer structure of two or more layers made of at least two different materials.</p><p>Another aspect of the invention relating to a manufacturing method for achieving the above structure is a method for manufacturing a semiconductor device, which includes forming a gate electrode over a substrate having an insulating surface, forming a gate insulating layer that covers the gate electrode, stacking a conductive layer and a buffer layer over the gate insulating layer without exposure to air, selectively etching the buffer layer and the conductive layer to form source and drain electrodes having side surfaces that form an angle of 20° to 90° with a substrate surface of the substrate, and forming oxide semiconductor layers over the gate insulating layer, the source electrode, and the drain electrode.</p><p>In the structure according to the above manufacturing method, the buffer layer contains indium, gallium, and zinc, and the same target as that for the oxide semiconductor layer formed over the buffer layer can be used.</p><p>The buffer layer and the oxide semiconductor layer can be formed separately by changing the deposition atmosphere, and the manufacturing cost can be reduced by using a common target.</p><p>In the structure according to the above manufacturing method, one of the features is that the conductive layer and the buffer layer are stacked on the gate insulating layer without being exposed to the air, and are successively formed.</p><p>In the structure according to the above manufacturing method, the conductive layer forming the source electrode and the drain electrode is formed using a metal material such as aluminum, tungsten, chromium, tantalum, titanium, molybdenum, or an alloy material thereof. The conductive layer may be a stack of two or more layers, such as a stack of an aluminum film as a lower layer and a titanium film as an upper layer, a stack of a tungsten film as a lower layer and a molybdenum film as an upper layer, or a stack of an aluminum film as a lower layer and a molybdenum film as an upper layer.</p><p>In this specification, continuous film formation means that the atmosphere in which the substrate to be processed is placed is always controlled to be a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere) without coming into contact with a contaminated atmosphere such as air during a series of processes from the first film formation step performed by sputtering to the second film formation step performed by sputtering. By performing continuous film formation, film formation can be performed while avoiding re-adhesion of moisture and the like to the cleaned substrate to be processed.</p><p>In this specification, the continuous film formation includes a series of processes from the first film formation step to the second film formation step performed in the same chamber.</p><p>In addition, when a series of processes from the first film formation process to the second film formation process are performed in different chambers, the scope of continuous film formation in this specification also includes transporting the substrate between chambers without exposing it to the atmosphere after the first film formation process is completed and performing the second film formation.</p><p>In addition, even if there is a substrate transport process, an alignment process, a slow cooling process, or a process of heating or cooling the substrate to the temperature required for the second process between the first film formation process and the second film formation process, it is considered to be within the scope of continuous film formation in this specification.</p><p>However, if a process using a liquid, such as a cleaning process, wet etching, or resist formation, is performed between the first and second film formation processes, it is not considered to fall within the scope of continuous film formation as defined in this specification.</p><p>In this specification, terms indicating directions such as top, bottom, side, horizontal, and vertical refer to directions based on the surface of a substrate when a device is placed on the surface of the substrate.</p><p>Note that the ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking layers, nor do they indicate specific names as matters for identifying the invention in this specification.</p>

<p>By adjusting the angle between the substrate surface of the substrate and the side surface of the source electrode and the angle between the substrate surface of the substrate and the side surface of the drain electrode, the coverage of the oxide semiconductor layer provided on the source electrode and the drain electrode is improved.</p><p>By providing the electric field concentration relaxation region, electric field concentration that may occur between the source electrode and the drain electrode is relaxed, and degradation of the switching characteristics of the thin film transistor is suppressed.</p>

<figref num="1">1 is a cross-sectional view illustrating an example of a semiconductor device.</figref><figref num="2">1 is a cross-sectional view illustrating an example of a semiconductor device.</figref><figref num="3">1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.</figref><figref num="4">1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.</figref><figref num="5">1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device.</figref><figref num="6">1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device.</figref><figref num="7">1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device.</figref><figref num="8">1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device.</figref><figref num="9">1A and 1B are diagrams showing an example of a cross-sectional view and an example of a top view of a terminal portion;</figref><figref num="10">1A to 1C are top views illustrating an example of a method for manufacturing a semiconductor device.</figref><figref num="11">1 is a cross-sectional view illustrating an example of a semiconductor device.</figref><figref num="12">FIG. 1 illustrates an example of a block diagram of a semiconductor device.</figref><figref num="13">FIG. 2 is a diagram illustrating an example of the configuration of a signal line driver circuit. </figref><figref num="14">10 is a timing chart illustrating an example of the operation of the signal line driver circuit.</figref><figref num="15">10 is a timing chart illustrating an example of the operation of the signal line driver circuit.</figref><figref num="16">FIG. 2 is a diagram illustrating an example of the configuration of a shift register.</figref><figref num="17">17 is a diagram illustrating a connection configuration of the flip-flop shown in FIG. 16. FIG.</figref><figref num="18">FIG. 2 is a diagram illustrating an example of a pixel equivalent circuit of a semiconductor device.</figref><figref num="19">1 is a cross-sectional view illustrating an example of a semiconductor device.</figref><figref num="20">1A and 1B are a cross-sectional view and a top view illustrating an example of a semiconductor device.</figref><figref num="21">1 is a cross-sectional view illustrating an example of a semiconductor device.</figref><figref num="22">1A and 1B are a cross-sectional view and a top view illustrating an example of a semiconductor device.</figref><figref num="23">1A and 1B are diagrams illustrating examples of usage of electronic paper.</figref><figref num="24">FIG. 1 is an external view showing an example of an electronic book.</figref><figref num="25">FIG. 1 is an external view showing an example of a television device and a digital photo frame.</figref><figref num="26">1 is an external view showing an example of a gaming machine.</figref><figref num="27">FIG. 1 is an external view showing an example of a mobile phone.</figref><figref num="28">FIG. 10 is a diagram illustrating an example of electrical characteristics of a thin film transistor.</figref><figref num="29">FIG. 1 is a top view of a thin film transistor fabricated for measuring electrical characteristics.</figref><figref num="30">1A to 1C are cross-sectional views showing steps for producing a sample.</figref><figref num="31">1A and 1B are a photograph and a cross-sectional view showing a part of a cross section of a sample.</figref><figref num="32">1A is a diagram showing an example of a cross-sectional structure of a semiconductor device, FIG. 1B is an equivalent circuit diagram, and FIG. 1C is a top view.</figref><figref num="33">FIG. 2 is a cross-sectional view showing the structure of a calculation model.</figref><figref num="34">10 is a graph showing calculation results.</figref><figref num="35">10 is a graph showing calculation results.</figref><figref num="36">10 is a graph showing calculation results.</figref><figref num="37">10 is a graph showing the calculation results (Comparative Example).</figref>

This embodiment will be described below.

1 shows an example in which a thin film transistor 170 is provided over a substrate. Note that FIG. 1 is an example of a cross-sectional view of a thin film transistor.

A gate electrode 101 provided over a substrate 100 having an insulating surface is covered with a gate insulating layer 102, and a first wiring or a second wiring is provided over the gate insulating layer 102 overlapping with the gate electrode 101. A buffer layer is provided over the first wiring or the second wiring functioning as a source electrode layer 105a or a drain electrode layer 105b, respectively. A first buffer layer 104a is provided over the source electrode layer 105a, and a second buffer layer 104b is provided over the drain electrode layer 105b. An oxide semiconductor layer 103 is provided over the first buffer layer 104a and the second buffer layer 104b.

In FIG. 1, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, typified by Corning 7059 glass or 1737 glass, can be used as a light-transmitting substrate 100 .

The gate electrode 101 is a single layer or a laminate of different metal materials. The gate electrode 101 is made of a metal material (an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), or an alloy containing the above elements), and the angle of the side surface of the gate electrode 101 is set to 20° or more and less than 90°. The gate electrode 101 is formed by etching so that at least the end portion is tapered.

The gate insulating layer 102 may be formed as a single layer or a stacked layer using an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, or a tantalum oxide film obtained by a sputtering method or a plasma CVD method. Note that it is preferable to select a material that has a sufficient selectivity when etching the source electrode layer 105a and the drain electrode layer 105b formed on the gate insulating layer 102. When etching the source electrode layer 105a and the drain electrode layer 105b, the surface of the gate insulating layer 102 may be etched to a thickness of about 20 nm, and it is preferable to remove a small amount of the surface layer to remove etching residues of metal materials.

The source electrode layer 105a and the drain electrode layer 105b are formed as a single layer or a stack of different metal materials, and are made of a metal material (an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), or an alloy containing any of the above elements).

1, the cross-sectional shape of the source electrode layer 105a is such that the angle θ1 formed between the substrate surface of the substrate and the side surface of the source electrode layer 105a is 20° or more and less than 90°. The cross-sectional shape of the drain electrode layer 105b is such that the angle θ2 formed between the substrate surface of the substrate and the side surface of the drain electrode layer 105b is 20° or more and less than 90°. Since the drain electrode layer 105b are formed by the same etching process (dry etching or wet etching), the angle θ1 and the angle θ2 are almost the same. By setting the angle θ1 of the side surface of the source electrode layer 105a in contact with the oxide semiconductor layer and the angle θ2 of the side surface of the drain electrode layer 105b to 20° or more and less than 90°, the distances from the upper ends to the lower ends of the electrodes at the side surfaces of the source electrode layer 105a and the drain electrode layer 105b are increased.

In FIG. 1, angles θ1 and θ2 are expressed with the back surface plane of the substrate as the substrate surface, but this is not particularly limited, and it goes without saying that the angles will be the same even if the front surface plane of the substrate is used as the substrate surface because the back surface plane and the front surface plane of the substrate are parallel.

The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is formed by depositing an oxide semiconductor target containing In, Ga, and Zn (In₂O₃:Ga₂O₃The oxide semiconductor film is formed using a ZnO (ZnO=1:1:1) target at a substrate-to-target distance of 170 mm, under a pressure of 0.4 Pa, with a direct current (DC) power supply of 0.5 kW, in an oxygen-containing argon atmosphere. A resist mask is then formed, and the film is selectively etched to remove unnecessary portions. Note that using a pulsed direct current (DC) power supply is preferable because it can reduce dust and ensure a uniform film thickness distribution. The oxide semiconductor film has a thickness of 5 nm to 200 nm. In this embodiment, the oxide semiconductor film has a thickness of 100 nm.

Note that a first buffer layer 104a is preferably provided between the source electrode layer 105a and the oxide semiconductor layer 103. In addition, a second buffer layer 104b is preferably provided between the drain electrode layer 105b and the oxide semiconductor layer 103.

The first buffer layer 104a and the second buffer layer 104b are made of an oxide semiconductor layer (n⁺layer) that functions as the source or drain region.

n⁺The layer is In₂O₃:Ga₂O₃A target containing In:ZnO=1:1:1 was used, and the film formation was performed by sputtering under the conditions of a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm.₂O₃:Ga₂O₃Even though a target with a composition ratio of InGaZnO=1:1:1 is intentionally used, an InGaZnO-based non-single-crystal film containing crystal grains of 1 nm to 10 nm in size immediately after film formation may be formed. It should be noted that the presence or absence of crystal grains, as well as the density and diameter of the crystal grains, can be adjusted within the range of 1 nm to 10 nm by appropriately adjusting the target component ratio, film formation pressure (0.1 Pa to 2.0 Pa), power (250 W to 3000 W: 8 inches φ), temperature (room temperature to 100°C), and film formation conditions of reactive sputtering. The film thickness of the second InGaZnO-based non-single-crystal film is 5 nm to 20 nm. Of course, if crystal grains are contained in the film, the size of the included crystal grains does not exceed the film thickness. In this embodiment, the film thickness of the second InGaZnO-based non-single-crystal film is 5 nm.

In addition, a conductive film to be the source electrode layer 105a or the drain electrode layer 105b and an n⁺By depositing the oxide semiconductor film to be the layer by a sputtering method without exposing it to the air, it is possible to prevent the source electrode layer or the drain electrode layer from being exposed during the manufacturing process and from being contaminated with dust.

The oxide semiconductor layer 103 obtained by a sputtering method tends to have a film quality in the vicinity of the interface with the surface on which the film is formed that is affected by the material of the surface on which the film is formed.⁺The oxide semiconductor layer 103 has at least three interfaces with different materials: an interface with the native oxide film on the side surface of the drain electrode, an interface with the side surface of the source electrode layer (and the side surface of the drain electrode layer), and an interface with the gate insulating film. Therefore, in the oxide semiconductor layer 103, the interface state with the native oxide film on the side surface of the drain electrode is different from the interface state with the gate insulating film, so the oxide semiconductor layer near the interface with the side surface of the drain electrode layer functions as a first electric field concentration relaxation region 106a. Furthermore, the interface state with the native oxide film on the side surface of the source electrode is different from the interface state with the gate insulating film, so the oxide semiconductor layer near the interface with the side surface of the source electrode functions as a second electric field concentration relaxation region 106b.

The angle θ1 of the side surface of the source electrode and the angle θ2 of the side surface of the drain electrode that are in contact with the oxide semiconductor layer are set to 20° or more and less than 90°, and the distance from the upper end to the lower end of the electrode on the side surface of the source electrode and the drain electrode is increased, thereby increasing the length L1 of the first electric field concentration alleviation region 106a and the length L2 of the second electric field concentration alleviation region 106b, thereby alleviating electric field concentration. Furthermore, the distance from the upper end to the lower end of the electrode on the side surface of the electrode can also be increased by increasing the film thickness of the source electrode and the drain electrode.

Furthermore, when the oxide semiconductor layer 103 is formed by sputtering, the thickness of the film formed on the side surface of the electrode perpendicular to the substrate surface may be thinner than the thickness of the film formed on the top surface of the electrode. By setting the angle θ1 of the side surface of the source electrode and the angle θ2 of the side surface of the drain electrode in contact with the oxide semiconductor layer to be 20° or more and less than 90°, the uniformity of the film thickness can be improved even on the side surface, the region where the oxide semiconductor layer 103 is locally thin can be reduced, and electric field concentration can also be alleviated.

1 shows an example in which a line connecting the lower end of the side surface of the source electrode layer (drain electrode layer) and the upper end of the side surface of the source electrode layer (drain electrode layer) substantially coincides with the inclination of the side surface of the source electrode layer (drain electrode layer). In this embodiment, however, an example in which a step is formed on the side surface of the source electrode layer (drain electrode layer) will be described with reference to FIG. 2. As long as at least the angle θ1 of the side surface of the lower end of the source electrode layer and the angle θ2 of the side surface of the lower end of the drain electrode layer are 20° or more and less than 90°, the side surface of the electrode may have a step. Note that the same reference numerals are used in FIG. 2 to designate parts common to those in FIG. 1.

A gate electrode 101 provided over a substrate 100 having an insulating surface is covered with a gate insulating layer 102, and a first wiring or a second wiring is provided over the gate insulating layer 102 overlapping with the gate electrode 101. A buffer layer is provided over the first wiring or the second wiring functioning as a source electrode layer 405a or a drain electrode layer 405b. A first buffer layer 404a is provided over the source electrode layer 405a, and a second buffer layer 404b is provided over the drain electrode layer 405b. An oxide semiconductor layer 403 is provided over the first buffer layer 404a and the second buffer layer 404b.

The substrate 100 having an insulating surface, the gate electrode 101, and the gate insulating layer 102 are the same as those in the first embodiment, and therefore detailed description thereof will be omitted here.

The source electrode layer 405a and the drain electrode layer 405b are formed as a single layer or a stack of different metal materials. The source electrode layer 405a and the drain electrode layer 405b are formed using a metal material (an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), or an alloy containing any of the above elements).

Here, an example is described in which a single layer of a 100-nm-thick tungsten film is used as the source electrode layer 405a and the drain electrode layer 405b, and the side surfaces of the source electrode layer 405a and the drain electrode layer 405b shown in FIG. 2 are formed using an ICP etching apparatus with a coil antenna.

In this embodiment, CF₄The gas flow rate was 25 sccm, and Cl₃The gas flow rate was 25 sccm, O₂The gas flow rate is set to 10 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-shaped electrode at a pressure of 1.5 Pa to generate plasma and perform etching. 10 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), applying a substantially negative self-bias voltage. By stopping this etching midway when at least some of the gate insulating film 102 is exposed, a stepped electrode side surface is formed.

Under the above etching conditions, the cross-sectional shape of the source electrode layer 405a can be such that the angle θ1 formed between the substrate surface and the side surface of the lower end of the source electrode layer 405a is 20° or more and less than 90°, and is approximately 40° as shown in FIG. 2. The angle formed between the substrate surface and the side surface of the upper end of the source electrode layer 405a is approximately 90°. Note that the cross-sectional shapes of the side surfaces of the source electrode layer 405a and the drain electrode layer 405b that face each other across the oxide semiconductor layer 403 are almost identical because they undergo the same etching process.

By making the angle of the side surface of the upper end of the source electrode layer 405a (and the drain electrode layer 405b) larger than that of the lower end of the source electrode layer 405a (and the drain electrode layer 405b), the distance between photomasks (or resist masks) used to form the source electrode layer 405a and the drain electrode layer 405b can be designed to be narrow. As a result, the channel length can be designed to be short, for example, to be 1 μm to 10 μm.

Furthermore, without being limited to the above-described method, a step can be formed on the side surface of the electrode by stacking materials having different etching rates when an etching gas is used for the source electrode layer 405a and the drain electrode layer 405b, with a lower layer being a material having a low etching rate and an upper layer being a material having a high etching rate.

By providing a step between the two electrode side surfaces facing each other across the oxide semiconductor layer 403, the distance from the upper end of the electrode to the lower end of the electrode on the side surface of the source electrode layer and the drain electrode layer is increased, thereby lengthening the length L3 of the first electric field concentration alleviation region 406a and the length L4 of the second electric field concentration alleviation region 406b, thereby alleviating electric field concentration.

Furthermore, in order to increase the distance from the upper end to the lower end of the electrode on the side surfaces of the source electrode layer and the drain electrode layer, wet etching may be further performed after the above-described dry etching so that part of the side surfaces of the two electrodes facing each other with the oxide semiconductor layer 403 sandwiched therebetween may be curved.

Alternatively, instead of the above-described dry etching, the source electrode layer and the drain electrode layer may be formed by wet etching so that at least the angle θ1 of the side surface of the lower end of the source electrode layer and the angle θ2 of the side surface of the lower end of the drain electrode layer are 20° or more and less than 90°, and the cross-sectional shape may be flared from the top surface of the electrode toward the substrate.

This embodiment mode can be freely combined with Embodiment Mode 1.

Embodiment Mode 3 In this embodiment mode, a thin film transistor and a manufacturing process thereof will be described with reference to FIGS.

In FIG. 3A, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used as a light-transmitting substrate 100.

Next, after forming a conductive layer over the entire surface of the substrate 100, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wirings and electrodes (gate wirings including the gate electrode 101, the capacitor wiring 108, and the first terminal 121). At this time, etching is performed so that at least the end of the gate electrode 101 has a tapered shape. A top view at this stage is shown in FIG. 3(A). Note that the top view at this stage corresponds to FIG. 5.

The gate wiring including the gate electrode 101, the capacitor wiring 108, and the first terminal 121 of the terminal section are formed of an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), aluminum (Al), and copper (Cu), or an alloy containing the above elements, an alloy film combining the above elements, or a nitride containing the above elements. Among these, it is preferable to form them from low-resistance conductive materials such as aluminum (Al) and copper (Cu), but Al alone has problems such as poor heat resistance and susceptibility to corrosion, so they are formed from an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), neodymium (Nd), or an alloy film combining the above elements, or a nitride containing the above elements.

Next, a gate insulating layer 102 is formed over the entire surface of the gate electrode 101. The gate insulating layer 102 is formed by sputtering or the like to a thickness of 50 to 250 nm.

For example, a silicon oxide film is formed by sputtering to a thickness of 100 nm as the gate insulating layer 102. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film, and other insulating films such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, or a tantalum oxide film may be used, and may be formed as a single layer or a multilayer structure made of these materials.

Next, a conductive film made of a metal material is formed on the gate insulating layer 102 by sputtering or vacuum deposition. Examples of materials for the conductive film include an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy containing the above elements, or an alloy film combining the above elements. Here, an aluminum (Al) film is used as the conductive film, and a Ti film is laminated on top of the aluminum (Al) film. The conductive film may also have a three-layer structure, or a titanium film may be laminated on a tungsten film. The conductive film may also have a single-layer structure of an aluminum film containing silicon, or a single-layer structure of a tungsten film.

Next, a first oxide semiconductor film (a first InGaZnO-based non-single-crystal film in this embodiment) is formed over the conductive film by a sputtering method.₂O₃:Ga₂O₃A target containing In:ZnO=1:1:1 was used, and the film formation was performed by sputtering under the conditions of a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm.₂O₃:Ga₂O₃Even though a target with a composition ratio of InGaZnO=1:1:1 is intentionally used, an InGaZnO-based non-single-crystal film containing crystal grains of 1 nm to 10 nm in size immediately after film formation may be formed. It should be noted that the presence or absence of crystal grains, as well as the density and diameter of the crystal grains, can be adjusted within the range of 1 nm to 10 nm by appropriately adjusting the target component ratio, film formation pressure (0.1 Pa to 2.0 Pa), power (250 W to 3000 W: 8 inches φ), temperature (room temperature to 100°C), and reactive sputtering film formation conditions. The film thickness of the first InGaZnO-based non-single-crystal film is 5 nm to 20 nm. Of course, if crystal grains are contained in the film, the size of the included crystal grains does not exceed the film thickness. In this embodiment, the film thickness of the first InGaZnO-based non-single-crystal film is 5 nm.

Next, a second photolithography process is performed to form a resist mask and etch the first In-Ga-Zn-O-based non-single-crystal film. Here, wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) is performed to remove unnecessary portions in the pixel area to form the first In-Ga-Zn-O-based non-single-crystal films 111a and 111b. Note that the etching here is not limited to wet etching, and dry etching may also be used.

Next, using the same resist mask as used in etching the first In-Ga-Zn-O-based non-single-crystal film, unnecessary portions are removed by etching to form the source electrode layer 105a and the drain electrode layer 105b. Wet etching or dry etching is used as the etching method. Here, SiCl₄and Cl₂and BCl₃The conductive film including the stacked Al film and Ti film is etched by dry etching using the mixed gas of the above as a reactive gas to form the source electrode layer 105a and the drain electrode layer 105b. A cross-sectional view at this stage is shown in FIG. 3(B). A top view at this stage corresponds to FIG. 6.

By this etching, the angle θ1 of the side surface of the source electrode layer 105a and the angle θ2 of the side surface of the drain electrode layer 105b, which are in contact with an oxide semiconductor layer to be formed later, are set to 20° or more and less than 90°. By tapering the side surfaces of two electrodes opposing each other with the oxide semiconductor layer sandwiched therebetween, regions of the oxide semiconductor layer which overlap with the side surfaces of the source electrode layer and the drain electrode layer can function as electric field concentration relaxation regions.

In addition, in this second photolithography process, the second terminal 122 made of the same material as the source electrode layer 105a and the drain electrode layer 105b remains in the terminal portion. The second terminal 122 is electrically connected to the source wiring (the source wiring including the source electrode layer 105a). In addition, in the terminal portion, the first InGaZnO-based non-single-crystal film 123 that exists above the second terminal 122 and overlaps with the second terminal 122 remains.

In the capacitive section, the capacitive electrode layer 124 made of the same material as the source electrode layer 105a and the drain electrode layer 105b is left. In the capacitive section, the first InGaZnO-based non-single-crystal film 111c that is above the capacitive electrode layer 124 and overlaps with the capacitive electrode layer 124 remains.

Next, after removing the resist mask, a second oxide semiconductor film (a second In-Ga-Zn-O-based non-single-crystal film in this embodiment) is formed without exposure to the air. Forming the second In-Ga-Zn-O-based non-single-crystal film without exposure to the air after the plasma treatment is useful in that dust and the like are not attached to the interface between the gate insulating layer and the semiconductor film. Here, an oxide semiconductor target (In₂O₃:Ga₂O₃The film is formed using a ZnO (ZnO=1:1:1) target with a substrate-to-target distance of 170 mm, a pressure of 0.4 Pa, a direct current (DC) power supply of 0.5 kW, and in an argon or oxygen atmosphere. The use of a pulsed direct current (DC) power supply is preferable because it reduces dust and provides a uniform film thickness distribution. The film thickness of the second In-Ga-Zn-O-based non-single-crystal film is 5 nm to 200 nm. In this embodiment, the film thickness of the second In-Ga-Zn-O-based non-single-crystal film is 100 nm.

The second In-Ga-Zn-O-based non-single-crystal film has a higher electrical resistance than the first In-Ga-Zn-O-based non-single-crystal film by using different deposition conditions from those for the first In-Ga-Zn-O-based non-single-crystal film. For example, the ratio of the oxygen gas flow rate to the argon gas flow rate under the deposition conditions for the second In-Ga-Zn-O-based non-single-crystal film is set to be higher than the ratio of the oxygen gas flow rate to the argon gas flow rate under the deposition conditions for the first In-Ga-Zn-O-based non-single-crystal film. Specifically, the deposition conditions for the first In-Ga-Zn-O-based non-single-crystal film are set to be in a rare gas (argon, helium, etc.) atmosphere (or 10% or less oxygen gas and 90% or more argon gas), and the deposition conditions for the second In-Ga-Zn-O-based non-single-crystal film are set to be in an oxygen atmosphere (or an oxygen gas flow rate to argon gas ratio of 1:1 or more).

Next, it is preferable to perform a heat treatment at 200°C to 600°C, typically 300°C to 500°C. Here, the film is placed in a furnace and heat treated at 350°C for 1 hour in a nitrogen or air atmosphere. This heat treatment causes rearrangement at the atomic level in the In-Ga-Zn-O based non-single-crystal film. This heat treatment (including photo-annealing) is important because it relieves distortion that inhibits carrier movement. The timing of the heat treatment is not particularly limited as long as it is performed after the formation of the second In-Ga-Zn-O based non-single-crystal film, and it may be performed, for example, after the formation of the pixel electrode.

Next, a third photolithography step is performed to form a resist mask, and unnecessary portions are removed by etching to form the semiconductor layer 103. Here, the second In-Ga-Zn-O-based non-single-crystal film is removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) to form the semiconductor layer 103. When removing by wet etching, the oxide semiconductor can be regenerated from the etching waste liquid and reused for target production.

Indium and gallium contained in oxide semiconductors are known to be rare metals, and reusing them can contribute to resource conservation and reduce the costs of products made using oxide semiconductors.

Since the same etchant is used for the first In-Ga-Zn-O-based non-single-crystalline film and the second In-Ga-Zn-O-based non-single-crystalline film, the first In-Ga-Zn-O-based non-single-crystalline film is removed by this etching. Therefore, the side surfaces of the first In-Ga-Zn-O-based non-single-crystalline film covered with the second In-Ga-Zn-O-based non-single-crystalline film are protected, but as shown in FIG. 4(A), the exposed first In-Ga-Zn-O-based non-single-crystalline films 111a and 111b are etched, forming the first buffer layer 104a and the second buffer layer 104b. The etching of the semiconductor layer 103 is not limited to wet etching; dry etching may also be used. Through the above steps, a thin-film transistor 170 is fabricated, with the semiconductor layer 103 serving as a channel formation region. A cross-sectional view at this stage is shown in FIG. 4(A). A top view at this stage corresponds to FIG. 7.

Next, the resist mask is removed, and the protective insulating film 107 that covers the semiconductor layer is formed. The protective insulating film 107 can be formed using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a tantalum oxide film, or the like by a sputtering method or the like.

Next, a fourth photolithography step is performed to form a resist mask, and the protective insulating film 107 is etched to form a contact hole 125 reaching the drain electrode layer 105b. This etching also forms a contact hole 127 reaching the second terminal 122. This etching also forms a contact hole 109 reaching the capacitor electrode layer 124. To reduce the number of masks, it is preferable to further etch the gate insulating layer using the same resist mask to form a contact hole 126 reaching the gate electrode. A cross-sectional view at this stage is shown in FIG. 4(B).

Next, after removing the resist mask, a transparent conductive film is formed. The transparent conductive film is made of indium oxide (In₂O₃) and indium oxide tin oxide alloy (In₂O₃- SnO₂These materials are formed using sputtering or vacuum deposition. Etching of these materials is performed using a hydrochloric acid solution. However, since etching of ITO is particularly prone to leaving residues, indium oxide zinc oxide alloys (InO2 and ITO) are used to improve etching processability.₂O₃-ZnO) may also be used.

Next, a fifth photolithography step is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode 110.

In this fifth photolithography step, a storage capacitor is formed by the capacitor electrode layer 124 and the pixel electrode 110, with the gate insulating layer 102 in the capacitor section serving as a dielectric. The capacitor wiring 108 is electrically connected to the capacitor electrode layer 124 through the contact hole 109.

In this fifth photolithography step, the first terminal and the second terminal are covered with a resist mask, leaving the transparent conductive films 128 and 129 formed on the terminal portions. The transparent conductive films 128 and 129 become electrodes or wiring used for connection with the FPC. The transparent conductive film 129 formed on the second terminal 122 is a terminal electrode for connection that functions as an input terminal for the source wiring.

Next, the resist mask is removed, and the cross-sectional view at this stage is shown in Fig. 4(C). Note that the top view at this stage corresponds to Fig. 8.

9(A1) and 9(A2) respectively show a top view and a cross-sectional view of the gate line terminal portion at this stage. FIG. 9(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 9(A2). In FIG. 9(A1), a transparent conductive film 155 formed on a protective insulating film 154 is a connection terminal electrode that functions as an input terminal. In FIG. 9(A1), a first terminal 151 made of the same material as the gate line and a connection electrode 153 made of the same material as the source line overlap with each other via a gate insulating layer 152, and are electrically connected by the transparent conductive film 155. The contact portion between the transparent conductive film 128 and the first terminal 121 shown in FIG. 4(C) corresponds to the contact portion between the transparent conductive film 155 and the first terminal 151 in FIG. 9(A1).

9B1 and 9B2 respectively show a top view and a cross-sectional view of a source wiring terminal portion different from the source wiring terminal portion shown in FIG. 4C. FIG. 9B1 corresponds to a cross-sectional view taken along line D1-D2 in FIG. 9B2. In FIG. 9B1, a transparent conductive film 155 formed on a protective insulating film 154 is a connection terminal electrode that functions as an input terminal. In FIG. 9B1, an electrode 156 made of the same material as the gate wiring overlaps a second terminal 150 electrically connected to the source wiring via a gate insulating layer 102. The electrode 156 is not electrically connected to the second terminal 150. Setting the electrode 156 to a potential different from that of the second terminal 150, such as floating, GND, or 0 V, can form a capacitance for noise reduction or static electricity reduction. The second terminal 150 is electrically connected to the transparent conductive film 155 via the protective insulating film 154.

A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal having the same potential as the gate wirings, a second terminal having the same potential as the source wirings, a third terminal having the same potential as the capacitance wirings, etc. are arranged in a line. The number of each terminal may be any number, and may be determined appropriately by the implementer.

In this way, five photolithography steps using five photomasks complete a pixel thin-film transistor portion having a thin-film transistor 170, which is a bottom-gate n-channel thin-film transistor, and a storage capacitor. These are then arranged in a matrix corresponding to each pixel to form a pixel portion, thereby forming one of the substrates for fabricating an active matrix display device. For convenience, this type of substrate will be referred to as an active matrix substrate in this specification.

When fabricating an active matrix liquid crystal display device, a liquid crystal layer is provided between an active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed together. A common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal section. This fourth terminal is a terminal for setting the common electrode to a fixed potential, such as GND or 0 V.

Furthermore, this embodiment is not limited to the pixel configuration of Fig. 8, and Fig. 10 shows an example of a top view different from that of Fig. 8. Fig. 10 shows an example in which a capacitance line is not provided, and a pixel electrode is formed by a gate line of an adjacent pixel and a capacitance electrode layer overlapping with the gate insulation layer via the gate insulation layer, using a gate insulation layer as a dielectric, and a storage capacitance is formed. In this case, the capacitance line and the third terminal connected to the capacitance line can be omitted. Note that in Fig. 10, the same parts as in Fig. 8 will be described using the same reference numerals.

In an active matrix liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between a selected pixel electrode and a corresponding counter electrode, which causes optical modulation of the liquid crystal layer arranged between the pixel electrode and the counter electrode, and this optical modulation is perceived by the viewer as a display pattern.

When displaying moving images on a liquid crystal display device, the slow response of the liquid crystal molecules themselves can cause problems such as afterimages or blurred moving images. To improve the moving image characteristics of liquid crystal display devices, a driving technology known as black insertion is available, which displays a full black screen every other frame.

There is also a driving technology called double-speed driving, which improves response speed by increasing the normal vertical period by 1.5 or more times and selects the gray scale to be written for each of the divided fields within each frame.

Furthermore, to improve the video characteristics of LCD devices, there is a driving technology that uses multiple LED (light-emitting diode) light sources or multiple EL light sources as a backlight to form a surface light source, and drives each light source that makes up the surface light source to light up intermittently independently within one frame period. Three or more types of LEDs may be used as a surface light source, or white-emitting LEDs may also be used. Because multiple LEDs can be controlled independently, the LED light emission timing can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. This driving technology can partially turn off the LEDs, which can reduce power consumption, especially when displaying images that occupy a large proportion of the screen in black.

By combining these driving techniques, it is possible to improve the display characteristics, such as the moving image characteristics, of a liquid crystal display device compared to conventional ones.

The n-channel transistor obtained in this embodiment uses an In-Ga-Zn-O-based non-single-crystal semiconductor layer in the channel formation region and has good dynamic characteristics, so that these driving techniques can be combined.

Furthermore, when a light-emitting display device is fabricated, one electrode (also referred to as a cathode) of the organic light-emitting element is set to a low power supply potential, such as GND or 0 V, and therefore a fourth terminal for setting the cathode to a low power supply potential, such as GND or 0 V, is provided in the terminal section. Furthermore, when a light-emitting display device is fabricated, a power supply line is provided in addition to the source wiring and the gate wiring. Therefore, a fifth terminal electrically connected to the power supply line is provided in the terminal section.

In this embodiment, a thin film transistor is formed having a stacked structure of a gate electrode layer, a gate insulating layer, a source electrode layer and a drain electrode layer, a source or drain region (an oxide semiconductor layer containing In, Ga, and Zn), and a semiconductor layer (an oxide semiconductor layer containing In, Ga, and Zn). By modifying the surface of the gate insulating layer by plasma treatment, the parasitic capacitance can be suppressed while keeping the semiconductor layer thin. Note that even if the semiconductor layer is thin, the proportion of the gate insulating layer to the semiconductor layer is sufficient, so that the parasitic capacitance is sufficiently suppressed.

According to this embodiment mode, a thin film transistor with a high on-off ratio and favorable dynamic characteristics can be obtained. Therefore, a semiconductor device including a thin film transistor with high electrical characteristics and high reliability can be provided.

(Embodiment 4) In this embodiment, an example of electronic paper will be shown as a semiconductor device.

11 shows active matrix electronic paper as an example of a semiconductor device different from a liquid crystal display device. A thin film transistor 581 used in a pixel portion of the semiconductor device can be manufactured in a manner similar to the thin film transistor of the pixel portion described in Embodiment 3 and is a thin film transistor including an In-Ga-Zn-O-based non-single-crystal film as a semiconductor layer. As described in Embodiment 1, by tapering the side surfaces of two electrodes opposing each other with an oxide semiconductor layer sandwiched therebetween, electronic paper including a highly reliable thin film transistor provided with an electric field relaxation region can be realized.

The electronic paper in Figure 11 is an example of a display device that uses the twist ball display method. The twist ball display method is a display method in which spherical particles painted black and white are placed between a first electrode layer and a second electrode layer, which are electrode layers used in a display element, and an electric potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

The thin film transistor 581 is a thin film transistor with a bottom gate structure, and the source electrode layer or the drain electrode layer is in contact with and electrically connected to a first electrode layer 587 through an opening formed in an insulating layer 585. A black region 590a and a white region 590b are provided between the first electrode layer 587 and the second electrode layer 588, and spherical particles 589 are provided around the spherical particles 589, each of which has a cavity 594 filled with a liquid, and the spherical particles 589 are surrounded by a filler 595 such as a resin (see FIG. 11).

Alternatively, an electrophoretic element can be used instead of a twist ball. This uses microcapsules with a diameter of approximately 10 μm to 200 μm, which contain a transparent liquid, positively charged white particles, and negatively charged black particles. When an electric field is applied by the first and second electrode layers to the microcapsules, the white and black particles move in opposite directions, displaying white or black. A display element that applies this principle is an electrophoretic display element, also known as electronic paper. Because electrophoretic display elements have a higher reflectivity than liquid crystal display elements, they do not require auxiliary lighting, consume less power, and allow the display to be viewed even in dimly lit places. Furthermore, since an image can be retained even when power is not supplied to the display, a displayed image can be preserved even when the semiconductor device with a display function (also simply referred to as a display device or a semiconductor device equipped with a display device) is moved away from the radio wave source.

Through the above steps, electronic paper can be manufactured as a semiconductor device at reduced manufacturing costs.

This embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3.

Embodiment Mode 5 In this embodiment mode, an example in which at least a part of a driver circuit and a thin film transistor disposed in a pixel portion are manufactured over the same substrate in a display device, which is an example of a semiconductor device, will be described below.

The thin film transistor disposed in the pixel portion is formed according to Embodiment 1 or 2. Since the thin film transistor described in Embodiment 1 or 2 is an n-channel TFT, part of the driver circuit, which can be configured using an n-channel TFT, is formed over the same substrate as the thin film transistor in the pixel portion.

12A shows an example of a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device. The display device shown in FIG. 12A includes a pixel portion 5301 having a plurality of pixels each having a display element over a substrate 5300, a scanning line driver circuit 5302 that selects each pixel, and a signal line driver circuit 5303 that controls input of a video signal to the selected pixel.

The pixel portion 5301 is connected to the signal line driver circuit 5303 by a plurality of signal lines S1 to Sm (not shown) arranged extending in the column direction from the signal line driver circuit 5303, and is connected to the scanning line driver circuit 5302 by a plurality of scanning lines G1 to Gn (not shown) arranged extending in the row direction from the scanning line driver circuit 5302, and has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. Each pixel is connected to a signal line Sj (one of the signal lines S1 to Sm) and a scanning line Gi (one of the scanning lines G1 to Gn).

The thin film transistor described in Embodiment 1 or 2 is an n-channel TFT, and a signal line driver circuit including an n-channel TFT will be described with reference to FIG.

13 includes a driver IC 5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c.

The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. The switch groups 5602_1 to 5602_M are connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and wirings 5621_1 to 5621_M corresponding to the switch groups 5602_1 to 5602_M, respectively. The wirings 5621_1 to 5621_M are connected to three signal lines via a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c. For example, the wiring 5621_J in the Jth column (any one of the wirings 5621_1 to 5621_M) is connected to the signal line Sj-1, the signal line Sj, and the signal line Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c of the switch group 5602_J.

Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

It is desirable that the driver IC 5601 be formed on a single crystal semiconductor substrate.

Furthermore, it is desirable that the switch group 5602_1 to 5602_M is formed on the same substrate as the pixel portion, and therefore the driver IC 5601 and the switch group 5602_1 to 5602_M should be connected via an FPC or the like.

Next, the operation of the signal line driver circuit shown in Fig. 13 will be described with reference to the timing chart in Fig. 14. Note that the timing chart in Fig. 14 shows the timing chart when the i-th row scanning line Gi is selected. Furthermore, the selection period of the i-th row scanning line Gi is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driver circuit in Fig. 13 operates in the same manner as in Fig. 14 even when a scanning line of another row is selected.

Note that the timing chart in Figure 14 shows a case where the Jth column wiring 5621_J is connected to the signal line Sj-1, the signal line Sj, and the signal line Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c.

The timing chart in Figure 14 shows the timing when the scanning line Gi in the i-th row is selected, the on/off timing 5703a of the first thin film transistor 5603a, the on/off timing 5703b of the second thin film transistor 5603b, the on/off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column.

Note that different video signals are input to the wirings 5621_1 to 5621_M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J in the third sub-selection period T3 is input to the signal line Sj+1. Furthermore, the video signals input to the wiring 5621_J in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are denoted as Data_j-1, Data_j, and Data_j+1, respectively.

As shown in FIG. 14, in the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c.

13 divides one gate selection period into three, allowing a video signal to be input from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driver circuit of FIG. 13 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about one-third of the number of signal lines. By reducing the number of connections to about one-third, the signal line driver circuit of FIG. 13 can improve reliability, yield, and the like.

As shown in Figure 13, as long as one gate selection period can be divided into multiple sub-selection periods and a video signal can be input from one wiring to multiple signal lines in each of the multiple sub-selection periods, the arrangement, number, driving method, etc. of the thin-film transistors are not limited.

For example, if a video signal is input from one wiring to three or more signal lines in each of three or more sub-selection periods, a thin film transistor and a wiring for controlling the thin film transistor can be added. However, if one gate selection period is divided into four or more sub-selection periods, each sub-selection period becomes shorter. Therefore, it is desirable to divide one gate selection period into two or three sub-selection periods.

As another example, as shown in the timing chart of Figure 15, one selection period may be divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Furthermore, the timing chart of Figure 15 shows the timing when the i-th scan line Gi is selected, the on/off timing 5803a of the first thin film transistor 5603a, the on/off timing 5803b of the second thin film transistor 5603b, the on/off timing 5803c of the third thin film transistor 5603c, and a signal 5821_J input to the J-th column wiring 5621_J. As shown in Figure 15, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on during the precharge period Tp. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal line Sj-1, the signal line Sj, and the signal line Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. During the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first thin film transistor 5603a. During the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c.

13 to which the timing chart of Fig. 15 is applied, a precharge selection period is provided before the sub-selection period, thereby enabling the signal lines to be precharged, and therefore video signals to be written to pixels at high speed. Note that in Fig. 15, the same components as those in Fig. 14 are denoted by the same reference numerals, and detailed descriptions of the same components or components having similar functions will be omitted.

Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register and a buffer. In some cases, it may also have a level shifter. In the scanning line driving circuit, a selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP) to the shift register. The generated selection signal is buffered and amplified in the buffer and supplied to the corresponding scanning line. The gate electrodes of the transistors of one line's worth of pixels are connected to the scanning line. And, because the transistors of one line's worth of pixels must all be turned on at the same time, a buffer capable of passing a large current is used.

One mode of a shift register used in a part of a scanning line driver circuit will be described with reference to FIGS.

Fig. 16 shows the circuit configuration of the shift register. The shift register shown in Fig. 16 is made up of a plurality of flip-flops 5701_i (one of flip-flops 5701_1 to 5701_n). The shift register operates by receiving a first clock signal, a second clock signal, a start pulse signal, and a reset signal.

The connection relationship of the shift register in Fig. 16 will be described. In the shift register in Fig. 16, in an i-th stage flip-flop 5701_i (one of flip-flops 5701_1 to 5701_n), the first wiring 5501 shown in Fig. 17 is connected to the seventh wiring 5717_i-1, the second wiring 5502 shown in Fig. 17 is connected to the seventh wiring 5717_i+1, the third wiring 5503 shown in Fig. 17 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in Fig. 17 is connected to the fifth wiring 5715.

In addition, the fourth wiring 5504 shown in Figure 17 is connected to the second wiring 5712 in odd-numbered flip-flops and to the third wiring 5713 in even-numbered flip-flops, and the fifth wiring 5505 shown in Figure 17 is connected to the fourth wiring 5714.

However, the first wiring 5501 shown in FIG. 17 of the first-stage flip-flop 5701_1 is connected to the first wiring 5711, and the second wiring 5502 shown in FIG. 17 of the n-th-stage flip-flop 5701_n is connected to the sixth wiring 5716.

The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be called a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may be called a first power supply line and a second power supply line, respectively.

Next, details of the flip-flop shown in Fig. 16 are shown in Fig. 17. The flip-flop shown in Fig. 17 has a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Note that the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 are n-channel transistors that are turned on when the gate-source voltage (Vgs) exceeds a threshold voltage (Vth).

Next, the connection configuration of the flip-flop shown in FIG. 16 will be described below.

A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to a third wiring 5503.

A first electrode of the second thin film transistor 5572 is connected to a sixth wiring 5506 , and a second electrode of the second thin film transistor 5572 is connected to a third wiring 5503 .

A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505, a second electrode of the third thin film transistor 5573 is connected to a gate electrode of the second thin film transistor 5572, and a gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.

A first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, a second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572, and a gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5571.

A first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, a second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571, and a gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501.

A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, a second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571, and a gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5572.

A first electrode of a seventh thin film transistor 5577 is connected to a sixth wiring 5506, a second electrode of the seventh thin film transistor 5577 is connected to a gate electrode of the first thin film transistor 5571, and a gate electrode of the seventh thin film transistor 5577 is connected to a second wiring 5502. A first electrode of an eighth thin film transistor 5578 is connected to the sixth wiring 5506, a second electrode of the eighth thin film transistor 5578 is connected to a gate electrode of the second thin film transistor 5572, and a gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501.

Note that a connection point between the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 is referred to as a node 5543. Furthermore, a connection point between the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 is referred to as a node 5544.

The first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be called a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be called a first power supply line, and the sixth wiring 5506 may be called a second power supply line.

Furthermore, the signal line driver circuit and the scan line driver circuit can also be formed using only the n-channel TFTs described in Embodiment 1 or 2. The mobility of a transistor using an oxide semiconductor layer is high, which enables the drive frequency of the driver circuit to be increased. Furthermore, the n-channel TFTs described in Embodiment 1 or 2 have high frequency characteristics (also called f characteristics) because the parasitic capacitance is reduced by the source region or the drain region. For example, the scan line driver circuit using the n-channel TFTs described in Embodiment 1 or 2 can be operated at high speed, which enables the frame frequency to be increased or black screen insertion to be realized.

Furthermore, an even higher frame frequency can be achieved by increasing the channel width of the transistors in the scanning line driver circuit, by arranging multiple scanning line driver circuits, etc. When multiple scanning line driver circuits are arranged, the frame frequency can be increased by arranging the scanning line driver circuits for driving even-numbered scanning lines on one side and the scanning line driver circuits for driving odd-numbered scanning lines on the opposite side.

In addition, when manufacturing an active matrix light-emitting display device, which is an example of a semiconductor device, it is preferable to provide a plurality of scanning line driver circuits in order to provide a plurality of thin film transistors in at least one pixel. An example of a block diagram of an active matrix light-emitting display device is shown in Figure 12(B).

The light-emitting display device shown in Figure 12(B) includes a pixel portion 5401 having a plurality of pixels each having a display element over a substrate 5400, a first scanning line driver circuit 5402 and a second scanning line driver circuit 5404 which select each pixel, and a signal line driver circuit 5403 which controls input of a video signal to the selected pixel.

When a video signal input to a pixel of the light-emitting display device shown in Figure 12(B) is in digital format, the pixel emits or does not emit light by switching a transistor on or off. Therefore, gradation can be displayed using area gray scale or time gray scale. Area gray scale is a driving method in which one pixel is divided into multiple sub-pixels and each sub-pixel is independently driven based on a video signal to display gradation. Time gray scale is a driving method in which gradation is displayed by controlling the period during which the pixel emits light.

Light-emitting elements have a faster response speed than liquid crystal elements, making them more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using time gray scale modulation, one frame period is divided into multiple sub-frame periods. Then, in each sub-frame period, the light-emitting elements of the pixels are made to emit or not emit light according to a video signal. By dividing the period into multiple sub-frame periods, the total length of the period during which the pixels actually emit light during one frame period can be controlled by the video signal, allowing gray scales to be displayed.

12(B) shows an example in which, when a pixel includes a switching TFT and a current-controlling TFT, a signal input to a first scan line, which is a gate wiring of the switching TFT, is generated by a first scan line driver circuit 5402, and a signal input to a second scan line, which is a gate wiring of the current-controlling TFT, is generated by a second scan line driver circuit 5404. However, both the signal input to the first scan line and the signal input to the second scan line may be generated by a single scan line driver circuit. Furthermore, depending on the number of transistors included in the switching element, a plurality of first scan lines used to control the operation of the switching element may be provided in each pixel. In this case, all the signals input to the plurality of first scan lines may be generated by a single scan line driver circuit, or may be generated by a plurality of scan line driver circuits.

In addition, in a light-emitting display device, part of the driver circuit, which can be configured with n-channel TFTs, can be formed over the same substrate as the thin film transistors in the pixel portion. Furthermore, the signal line driver circuit and the scan line driver circuit can also be manufactured using only the n-channel TFTs described in Embodiment 1 or 2.

Through the above steps, a highly reliable display device can be manufactured as a semiconductor device.

This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

(Embodiment 6) In this embodiment, an example of a light-emitting display device will be described as a semiconductor device. Here, a light-emitting element utilizing electroluminescence will be used as a display element of the display device. Light-emitting elements utilizing electroluminescence are classified depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

In organic EL elements, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, causing a current to flow. The recombination of these carriers (electrons and holes) causes the light-emitting organic compound to enter an excited state, and light is emitted when the excited state returns to the ground state. Due to this mechanism, such light-emitting elements are called current-excited light-emitting elements.

Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film inorganic EL elements based on their device structure. Dispersion-type inorganic EL elements have an emitting layer in which particles of emitting material are dispersed in a binder, and their emission mechanism is donor-acceptor recombination emission, which utilizes donor and acceptor levels. Thin-film inorganic EL elements have a structure in which an emitting layer is sandwiched between dielectric layers, which are in turn sandwiched between electrodes, and their emission mechanism is localized emission, which utilizes inner-shell electron transitions of metal ions. Note that the following explanation uses an organic EL element as the light-emitting element.

FIG. 18 is a diagram showing an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device.

The structure and operation of a pixel to which digital time gray scale driving can be applied are described below. Here, an example is shown in which one pixel uses two n-channel transistors that use an oxide semiconductor layer (In-Ga-Zn-O based non-single-crystal film) in the channel formation region.

The pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. The switching transistor 6401 has a gate connected to a scan line 6406, a first electrode (one of a source electrode and a drain electrode) connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) connected to the gate of the driving transistor 6402. The driving transistor 6402 has a gate connected to a power line 6407 via the capacitor 6403, a first electrode connected to the power line 6407, and a second electrode connected to a first electrode (pixel electrode) of the light-emitting element 6404.

The second electrode of the light emitting element 6404 corresponds to the common electrode 6408 .

A low power supply potential is set to the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is a potential that satisfies the condition that the low power supply potential is less than the high power supply potential with reference to the high power supply potential set to the power line 6407, and the low power supply potential may be set to, for example, GND or 0 V. The potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and cause the light-emitting element 6404 to emit light, so that the potential difference between the high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light-emitting element 6404.

It is to be noted that the capacitor 6403 can be omitted by substituting the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, capacitance may be formed between the channel region and the gate electrode.

In the case of a voltage input voltage driving method, a video signal is input to the gate of the driving transistor 6402 so that the driving transistor 6402 is in either one of two states, fully on or off. In other words, the driving transistor 6402 is operated in a linear region.

To operate the driving transistor 6402 in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied to the signal line 6405.

Furthermore, when analog gray scale driving is performed instead of digital time gray scale driving, the same pixel configuration as in FIG. 18 can be used by changing the signal input.

When analog gradation driving is performed, a voltage equal to or greater than the forward voltage of the light-emitting element 6404 plus the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to a voltage required for achieving a desired luminance, and includes at least a forward threshold voltage. Note that a current can be passed through the light-emitting element 6404 by inputting a video signal that causes the driving transistor 6402 to operate in a saturation region. To operate the driving transistor 6402 in a saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be passed through the light-emitting element 6404, thereby enabling analog gradation driving.

Note that the pixel configuration shown in Fig. 18 is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel shown in Fig. 18.

Next, the structure of a light-emitting element will be described with reference to Figures 19(A), 19(B), and 19(C). Here, a cross-sectional structure of a pixel will be described using an example in which the driving TFT is the thin film transistor 170 shown in Figure 1(B). TFTs 7001, 7011, and 7021, which are driving TFTs used in the semiconductor devices of Figures 19(A), 19(B), and 19(C), can be manufactured in the same manner as the thin film transistor 170 shown in Embodiment 1, and are thin film transistors that include an In-Ga-Zn-O-based non-single-crystal film as a semiconductor layer and have excellent electrical characteristics.

The light-emitting element only needs to have at least one of the anode or cathode transparent in order to extract light. The thin-film transistor and light-emitting element are formed on a substrate, and light-emitting elements can be of a top-emission structure in which light is extracted from the surface opposite the substrate, a bottom-emission structure in which light is extracted from the surface on the substrate side, or a double-emission structure in which light is extracted from both the substrate side and the surface opposite the substrate. The pixel configuration shown in Figure 18 can be applied to light-emitting elements of any emission structure.

A light emitting element with a top emission structure will be described with reference to FIG.

FIG. 19A shows a cross-sectional view of a pixel in which the driving TFT 7001 is the thin film transistor 170 shown in FIG. 1B and light emitted from the light-emitting element 7002 exits through the anode 7005. In FIG. 19A, the cathode 7003 of the light-emitting element 7002 is electrically connected to the driving TFT 7001. An emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as they have a low work function and are a conductive film that reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The emitting layer 7004 can be composed of a single layer or multiple layers. If the emitting layer 7004 is composed of multiple layers, an electron injection layer, an electron transport layer, an emitting layer, a hole transport layer, and a hole injection layer are stacked on the cathode 7003 in this order. It is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material, and a light-transmitting conductive film such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide added with silicon oxide may be used.

The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Figure 19(A), light emitted from the light-emitting element 7002 is emitted to the anode 7005 side as shown by the arrow.

Next, a light-emitting element with a bottom-emission structure will be described with reference to FIG. 19B. This figure shows a cross-sectional view of a pixel in which the driving TFT 7011 is the thin film transistor 170 shown in FIG. 1A and light emitted from the light-emitting element 7012 is emitted toward the cathode 7013. In FIG. 19B, the cathode 7013 of the light-emitting element 7012 is formed on a light-transmitting conductive film 7017 electrically connected to the driving TFT 7011. A light-emitting layer 7014 and an anode 7015 are sequentially stacked on the cathode 7013. If the anode 7015 is light-transmitting, a light-shielding film 7016 for reflecting or blocking light may be formed so as to cover the anode. As in the case of FIG. 19A, various conductive materials with a small work function can be used for the cathode 7013. However, the thickness of the cathode 7013 is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of either a single layer or a laminate of multiple layers, as in FIG. 19(A). The anode 7015 does not need to transmit light, but can be formed using a light-transmitting conductive material, as in FIG. 19(A). The shielding film 7016 can be made of, for example, a light-reflecting metal, but is not limited to a metal film. For example, a resin to which a black pigment is added can also be used.

The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel shown in Figure 19(B), light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side as shown by the arrow.

Next, a dual-emission light-emitting element will be described with reference to FIG. 19C. In FIG. 19C, a cathode 7023 of a light-emitting element 7022 is formed on a light-transmitting conductive film 7027 electrically connected to a driving TFT 7021. An light-emitting layer 7024 and an anode 7025 are sequentially stacked on the cathode 7023. As in FIG. 19A, the cathode 7023 can be made of various conductive materials with a low work function. However, the thickness of the cathode 7023 must be such that the light can pass through it. For example, Al having a thickness of 20 nm can be used for the cathode 7023. Similarly to FIG. 19A, the light-emitting layer 7024 may be composed of a single layer or multiple layers. Similarly to FIG. 19A, the anode 7025 can be formed using a light-transmitting conductive material.

The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7022. In the case of the pixel shown in Figure 19(C), light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be provided as light-emitting elements.

In this embodiment, an example has been shown in which a thin film transistor (driving TFT) that controls the driving of a light-emitting element is electrically connected to the light-emitting element, but a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used.

Note that the semiconductor device described in this embodiment mode is not limited to the configurations shown in Figures 19(A), 19(B), and 19(C), and various modifications based on the disclosed technical ideas are possible.

Next, a top view and a cross section of a light-emitting display panel (also referred to as a light-emitting panel), which corresponds to one embodiment of a semiconductor device, will be described with reference to Figures 22(A) and 22(B). Figure 22(A) is a top view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed between the first substrate and the second substrate with a sealant, and Figure 22(B) corresponds to a cross-sectional view taken along line HI in Figure 22(A).

A sealant 4505 is provided to surround the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b, which are provided over a first substrate 4501. A second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b are sealed together with a filler 4507 by the first substrate 4501, the sealant 4505, and the second substrate 4506. In this way, it is preferable to package (enclose) them with a protective film (such as a laminating film or an ultraviolet-cured resin film) or a cover material that is highly airtight and has little degassing property so as not to be exposed to the outside air.

The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b provided over the first substrate 4501 each include a plurality of thin film transistors. In FIG. 22B, a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503a are shown as examples.

The thin film transistors 4509 and 4510 can be the highly reliable thin film transistors described in Embodiment 1 which include an In-Ga-Zn-O-based non-single-crystal film as a semiconductor layer.

Further, 4511 corresponds to a light-emitting element, and a first electrode layer 4517 which is a pixel electrode of the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, an electroluminescent layer 4512, and a second electrode layer 4513, but is not limited to the structure shown in this embodiment mode. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4511, etc.

The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane.

In particular, it is preferable to form an opening over the first electrode layer 4517 using a photosensitive material, and to form the opening so that the sidewall of the opening becomes an inclined surface having a continuous curvature.

The electroluminescent layer 4512 may be configured as either a single layer or a stack of multiple layers.

A protective film may be formed over the second electrode layer 4513 and the partition wall 4520 to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, various signals and potentials applied to the signal line driver circuits 4503a and 4503b, the scanning line driver circuits 4504a and 4504b, or the pixel portion 4502 are supplied from FPCs 4518a and 4518b.

In this embodiment, the connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4509 and 4510.

The connection terminal electrode 4515 is electrically connected to a terminal of the FPC 4518 a via an anisotropic conductive film 4519 .

The second substrate must be light-transmitting, and is positioned in the direction in which light is extracted from the light-emitting element 4511. In this case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

In addition to inert gases such as nitrogen and argon, filler 4507 can be made of ultraviolet curable resin or thermosetting resin, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used.

If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptically polarizing plate), a retardation plate (λ/4 plate, λ/2 plate), or a color filter may be provided on the light-emitting surface of the light-emitting element. An anti-reflection film may also be provided on the polarizing plate or circular polarizing plate. For example, an anti-glare treatment can be applied to the surface, which diffuses reflected light by using unevenness to reduce glare.

The signal line driver circuits 4503a and 4503b and the scan line driver circuits 4504a and 4504b may be mounted using a separately prepared single crystal semiconductor substrate or a driver circuit formed using a single crystal semiconductor film or a polycrystalline semiconductor film over an insulating substrate. Only the signal line driver circuits or a part thereof, or only the scan line driver circuits or a part thereof may be separately formed and mounted, and this embodiment mode is not limited to the configurations in FIGS. 22A and 22B.

Through the above steps, a light-emitting display device (display panel) can be manufactured at reduced costs.

This embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3.

20A1, 20A2, and 20B illustrate a top view and a cross section of a liquid crystal display panel, which corresponds to one mode of a semiconductor device, with reference to Fig. 20A1, Fig. 20A2, and Fig. 20B. Fig. 20A1 and Fig. 20A2 are top views of a panel in which thin film transistors 4010 and 4011 including the In-Ga-Zn-O-based non-single-crystal film shown in Embodiment 1 formed over a first substrate 4001 as a semiconductor layer and a liquid crystal element 4013 are sealed between the first substrate 4001 and a second substrate 4006 and the panel with a sealant 4005. Fig. 20B corresponds to a cross section taken along line MN in Fig. 20A1 and Fig. 20A2.

A sealant 4005 is provided so as to surround a pixel portion 4002 and a scan line driver circuit 4004 provided over a first substrate 4001. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with a liquid crystal layer 4008 by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region on the first substrate 4001 different from the region surrounded by the sealant 4005.

The method for connecting the separately formed driver circuit is not particularly limited, and may be a COG method, a wire bonding method, a TAB method, etc. Fig. 20(A1) shows an example in which the signal line driver circuit 4003 is mounted by the COG method, and Fig. 20(A2) shows an example in which the signal line driver circuit 4003 is mounted by the TAB method.

20B shows a thin film transistor 4010 included in the pixel portion 4002 and a thin film transistor 4011 included in the scan line driver circuit 4004. Insulating layers 4020 and 4021 are provided over the thin film transistors 4010 and 4011.

The thin film transistor including an In-Ga-Zn-O-based non-single-crystal film as a semiconductor layer, which is described in Embodiment 1, can be applied to the thin film transistors 4010 and 4011. The thin film transistor 4011 corresponds to the thin film transistor 170 shown in FIG.

A pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on a second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. The pixel electrode layer 4030 and the counter electrode layer 4031 are provided with insulating layers 4032 and 4033 that function as alignment films, respectively, and the liquid crystal layer 4008 is sandwiched between the insulating layers 4032 and 4033.

Glass, metal (typically stainless steel), ceramics, or plastic can be used for the first substrate 4001 and the second substrate 4006. Examples of plastic that can be used include a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film. A sheet having a structure in which aluminum foil is sandwiched between PVF films or polyester films can also be used.

Reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers may also be used. The counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected using a common connection portion via conductive particles disposed between the pair of substrates. Note that the conductive particles are contained in the sealant 4005.

Alternatively, liquid crystals exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases that appears when cholesteric liquid crystals are heated, just before the transition from the cholesteric phase to the isotropic phase. Because the blue phase appears only within a narrow temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing liquid crystals exhibiting a blue phase and a chiral agent has a short response time of 10 μs to 100 μs, is optically isotropic, does not require alignment treatment, and has little viewing angle dependency.

Although this embodiment is an example of a transmissive liquid crystal display device, it can also be applied to a reflective liquid crystal display device or a semi-transmissive liquid crystal display device.

In the liquid crystal display device of this embodiment, an example is shown in which a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and an electrode layer used for the display element are provided on the inner side in this order, but the polarizing plate may also be provided on the inner side of the substrate. The stacked structure of the polarizing plate and the colored layer is not limited to that of this embodiment, and may be appropriately set depending on the materials of the polarizing plate and the colored layer and the manufacturing process conditions. A light-shielding film that functions as a black matrix may also be provided.

In this embodiment, the thin film transistor obtained in Embodiment 1 is covered with insulating layers (insulating layers 4020 and 4021) that function as a protective film or a planarizing insulating film in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor. Note that the protective film is used to prevent the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and is preferably a dense film. The protective film may be formed by a sputtering method as a single layer or a stack of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film. In this embodiment, an example in which the protective film is formed by sputtering is shown; however, the protective film may be formed by various methods such as a PCVD method without any particular limitation.

Here, an insulating layer 4020 having a stacked structure is formed as a protective film. Here, a silicon oxide film is formed by sputtering as a first layer of the insulating layer 4020. Using a silicon oxide film as a protective film is effective in preventing hillocks of an aluminum film used as a source electrode layer and a drain electrode layer.

An insulating layer is formed as the second layer of the protective film. Here, a silicon nitride film is formed by sputtering as the second layer of the insulating layer 4020. When a silicon nitride film is used as the protective film, it is possible to prevent ions such as sodium from entering the semiconductor region and changing the electrical characteristics of the TFT.

After forming the protective film, the semiconductor layer may be annealed (at 300° C. to 400° C.).

An insulating layer 4021 is formed as a planarization insulating film. The insulating layer 4021 can be formed using a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to the above organic materials, a low-dielectric-constant material (low-k material), a siloxane-based resin, PSG (phosphor glass), or BPSG (borophosphor glass) can also be used. The insulating layer 4021 can also be formed by stacking a plurality of insulating films made of these materials.

The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may have an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also have a fluoro group.

The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, sputtering, SOG, spin coating, dipping, spray coating, droplet discharging (such as inkjet printing, screen printing, or offset printing), doctor knife, roll coater, curtain coater, knife coater, or the like can be used. When the insulating layer 4021 is formed using a material liquid, the semiconductor layer may be annealed (at 300°C to 400°C) at the same time as the baking process. By combining the baking process of the insulating layer 4021 with the annealing process of the semiconductor layer, it is possible to efficiently manufacture a semiconductor device.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide added with silicon oxide.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer. The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω/ or less and a light transmittance of 70% or more at a wavelength of 550 nm. The resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

The conductive polymer may be a so-called π-electron conjugated conductive polymer, such as polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of these.

Various signals and potentials applied to a separately formed signal line driver circuit 4003, a scanning line driver circuit 4004 or the pixel portion 4002 are supplied from an FPC 4018.

In this embodiment mode, the connection terminal electrode 4015 is formed from the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019 .

20A1 and 20A2 show an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001, but this embodiment is not limited to this structure. The scanning line driver circuit may be formed separately and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted.

FIG. 21 shows an example of a liquid crystal display module configured as a semiconductor device using a TFT substrate 2600.

21 shows an example of a liquid crystal display module. A TFT substrate 2600 and a counter substrate 2601 are fixed together with a sealant 2602. A pixel section 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, a colored layer 2605, and a polarizing plate 2606 are disposed between them to form a display area. The colored layer 2605 is necessary for color display; in the case of the RGB system, colored layers corresponding to the colors red, green, and blue are provided for each pixel. Polarizing plates 2606, 2607, and a diffuser 2613 are disposed on the outer surfaces of the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611. A circuit board 2612 is connected to a wiring circuit section 2608 of the TFT substrate 2600 via a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated into the circuit board 2612. Furthermore, the polarizing plate and the liquid crystal layer may be laminated with a retardation plate interposed therebetween.

The liquid crystal display module can use TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal), etc.

Through the above steps, a liquid crystal display panel can be manufactured as a semiconductor device at reduced manufacturing costs.

This embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3.

(Embodiment 8) Electronic paper can be used in electronic devices in all fields as long as it displays information. For example, electronic paper can be used for electronic books, posters, advertisements inside vehicles such as trains, and displays on various cards such as credit cards. Examples of electronic devices are shown in Figs. 23 and 24.

Fig. 23(A) shows a poster 2631 made of electronic paper. When the advertising medium is a printed paper, the advertisement is changed manually, but by using electronic paper to which the third embodiment is applied, the advertisement display can be changed in a short time. In addition, a stable image can be obtained without display distortion. The poster may also be configured to be able to send and receive information wirelessly.

Also, Fig. 23(B) shows an in-car advertisement 2632 for a vehicle such as a train. When the advertising medium is a printed paper, the advertisement is changed manually, but if electronic paper to which the third embodiment is applied is used, the advertisement display can be changed in a short time without much manpower. In addition, a stable image can be obtained without display degradation. Note that the in-car advertisement may be configured to be able to send and receive information wirelessly.

24 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housings 2701 and 2703 are integrated by a pivot 2711, and can be opened and closed around the pivot 2711. This configuration allows the electronic book to operate like a paper book.

A display portion 2705 is incorporated in the housing 2701, and a display portion 2707 is incorporated in the housing 2703. The display portions 2705 and 2707 may be configured to display one screen or different screens. By displaying different screens, for example, text can be displayed on the right display portion (display portion 2705 in FIG. 24) and an image can be displayed on the left display portion (display portion 2707 in FIG. 24).

24 shows an example in which the housing 2701 is provided with an operation unit, etc. For example, the housing 2701 is provided with a power supply 2721, operation keys 2723, a speaker 2725, etc. Pages can be turned using the operation keys 2723. Note that a keyboard, pointing device, etc. may be provided on the same surface as the display unit of the housing. Furthermore, the rear or side of the housing may be provided with an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, etc. Furthermore, the electronic book 2700 may be configured to function as an electronic dictionary.

The electronic book 2700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure it so that desired book data can be purchased and downloaded wirelessly from an electronic book server.

(Embodiment 9) The semiconductor device can be applied to various electronic devices (including gaming machines). Examples of the electronic devices include television devices (also called televisions or television receivers), computer monitors, digital cameras, digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, personal digital assistants, sound players, and large game machines such as pachinko machines.

25A shows an example of a television set 9600. The television set 9600 has a display portion 9603 built into a housing 9601. Images can be displayed on the display portion 9603. In addition, in this example, the housing 9601 is supported by a stand 9605.

The television set 9600 can be operated using operation switches provided on the housing 9601 or a separate remote control 9610. Channels and volume can be controlled using operation keys 9609 provided on the remote control 9610, and images displayed on the display portion 9603 can be controlled. The remote control 9610 may be provided with a display portion 9607 that displays information output from the remote control 9610.

The television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

25B shows an example of a digital photo frame 9700. For example, the digital photo frame 9700 has a display portion 9703 built in a housing 9701. The display portion 9703 can display various images, and can function in the same way as a normal photo frame by displaying image data captured by a digital camera or the like, for example.

The digital photo frame 9700 is configured to include an operation unit, an external connection terminal (such as a USB terminal or a terminal connectable to various cables such as a USB cable), a recording medium insertion portion, etc. These components may be incorporated on the same surface as the display unit, but are preferably provided on the side or back to improve design. For example, a memory storing image data captured with a digital camera can be inserted into the recording medium insertion portion of the digital photo frame to import the image data, and the imported image data can be displayed on the display portion 9703.

The digital photo frame 9700 may also be configured to be capable of wirelessly transmitting and receiving information, and may be configured to wirelessly retrieve and display desired image data.

FIG. 26(A) shows a portable gaming machine, which is composed of two housings, housing 9881 and housing 9891, which are connected by a connecting part 9893 so that they can be opened and closed. A display part 9882 is incorporated into housing 9881, and a display part 9883 is incorporated into housing 9891. The portable gaming machine shown in FIG. 26(A) also includes a speaker part 9884, a recording medium insertion part 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9888 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be any configuration including at least a semiconductor device having the thin film transistor described in Embodiment 1 or 2, and may be configured to include other auxiliary equipment as appropriate. The portable gaming machine shown in Figure 26(A) has a function of reading out a program or data recorded on a recording medium and displaying it on a display unit, and a function of sharing information with other portable gaming machines through wireless communication. Note that the functions of the portable gaming machine shown in Figure 26(A) are not limited to these, and the portable gaming machine may have various functions.

26(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The slot machine 9900 has a display unit 9903 built in a housing 9901. The slot machine 9900 also includes operation means such as a start lever and a stop switch, a coin slot, a speaker, and the like. Of course, the configuration of the slot machine 9900 is not limited to the above, and may include at least a semiconductor device having the thin film transistor described in Embodiment 1 or 2, and other auxiliary equipment may be provided as appropriate.

27 shows an example of a mobile phone 1000. The mobile phone 1000 includes a display unit 1002 built into a housing 1001, as well as operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

27, information can be input by touching the display portion 1002 with a finger or the like. Operations such as making a call or typing an e-mail can also be performed by touching the display portion 1002 with a finger or the like.

The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images, the second is an input mode that mainly inputs information such as characters, and the third is a display + input mode that combines the display mode and the input mode.

For example, when making a call or composing an email, the display unit 1002 is set to a character input mode that mainly inputs characters, and characters displayed on the screen are input. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002.

In addition, by providing a detection device inside the mobile phone 1000 that has a sensor that detects tilt, such as a gyro or acceleration sensor, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the screen display of the display unit 1002 can be automatically switched.

The screen mode can be switched by touching the display unit 1002 or by operating the operation button 1003 on the housing 1001. The mode can also be switched depending on the type of image displayed on the display unit 1002. For example, if the image signal to be displayed on the display unit is video data, the display mode is selected, and if it is text data, the input mode is selected.

In addition, in input mode, a signal detected by an optical sensor of the display unit 1002 may be detected, and if there is no input by touch operation on the display unit 1002 for a certain period of time, the screen mode may be controlled to switch from input mode to display mode.

The display unit 1002 can also function as an image sensor. For example, by touching the palm or fingers to the display unit 1002, palm prints, fingerprints, etc. can be captured for personal authentication. Furthermore, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used in the display unit, finger veins, palm veins, etc. can also be captured.

(Embodiment 10) In Embodiment 1 or 2, an example in which a buffer layer is provided is shown, but in this embodiment, an example in which a buffer layer is not provided is shown. In addition, an example in which an inverter circuit is formed using two n-channel thin film transistors will be described below.

The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. An inverter circuit can be formed by combining two n-channel TFTs, by combining an enhancement-type transistor and a depletion-type transistor (hereinafter referred to as an EDMOS circuit), or by using only enhancement-type TFTs (hereinafter referred to as an EEMOS circuit). Note that if the threshold voltage of the n-channel TFT is positive, it is defined as an enhancement-type transistor, and if the threshold voltage of the n-channel TFT is negative, it is defined as a depletion-type transistor, and these definitions will be followed throughout this specification.

The pixel section and the driver circuit are formed on the same substrate, and in the pixel section, enhancement type transistors arranged in a matrix are used to switch on and off the voltage applied to the pixel electrode. The enhancement type transistors arranged in this pixel section use oxide semiconductors, and their electrical characteristics are such that the on/off ratio is 10 at a gate voltage of ±20V.⁹As a result, the leakage current is small and low power consumption driving can be achieved.

32A shows a cross-sectional structure of an inverter circuit of a driver circuit. In FIG. 32A, a first gate electrode 1401 and a second gate electrode 1402 are provided over a substrate 1400. The first gate electrode 1401 and the second gate electrode 1402 can be formed as a single layer or a stacked layer using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these as a main component.

For example, the two-layer stacked structure of the first gate electrode 1401 and the second gate electrode 1402 is preferably a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer stacked structure in which a molybdenum layer is stacked on a copper layer, a two-layer stacked structure in which a titanium nitride layer or tantalum nitride is stacked on a copper layer, or a two-layer stacked structure in which a titanium nitride layer and a molybdenum layer are stacked. The three-layer stacked structure is preferably a stacked structure in which a tungsten layer or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride or titanium layer are stacked.

In addition, a first wiring 1409, a second wiring 1410, and a third wiring 1411 are provided on a gate insulating layer 1403 covering the first gate electrode 1401 and the second gate electrode 1402, and the second wiring 1410 is directly connected to the second gate electrode 1402 through a contact hole 1404 formed in the gate insulating layer 1403.

In addition, a first oxide semiconductor layer 1405 is provided in contact with the first wiring 1409 and the second wiring 1410 at a position overlapping with the first gate electrode 1401, and a second oxide semiconductor layer 1407 is provided in contact with the second wiring 1410 and the third wiring 1411 at a position overlapping with the second gate electrode 1402.

The first thin film transistor 1430 has a first gate electrode 1401 and a first oxide semiconductor layer 1405 overlapping the first gate electrode 1401 with a gate insulating layer 1403 interposed therebetween, and the first wiring 1409 is a power supply line of ground potential (ground power supply line). This power supply line of ground potential may be a power supply line (negative power supply line) to which a negative voltage VDL is applied.

The second thin film transistor 1431 has a second gate electrode 1402 and a second oxide semiconductor layer 1407 overlapping the second gate electrode 1402 via a gate insulating layer 1403, and the third wiring 1411 is a power supply line (positive power supply line) to which a positive voltage VDD is applied.

The side surfaces of the first wiring 1409 and the second wiring 1410, which face each other across the first oxide semiconductor layer 1405, are tapered, so that regions of the oxide semiconductor layer that overlap with the side surfaces of the source electrode layer and the drain electrode layer function as electric field concentration relaxation regions.

Furthermore, by tapering the side surfaces of the second wiring 1410 and the third wiring 1411 that face each other across the second oxide semiconductor layer 1407, regions of the oxide semiconductor layer that overlap with the side surfaces of the source electrode layer and the drain electrode layer function as electric field concentration relaxation regions.

32A, a second wiring 1410 electrically connected to both the first oxide semiconductor layer 1405 and the second oxide semiconductor layer 1407 is directly connected to a second gate electrode 1402 of a second thin film transistor 1431 through a contact hole 1404 formed in a gate insulating layer 1403. Directly connecting the second wiring 1410 and the second gate electrode 1402 can provide good contact and reduce contact resistance. Compared to connecting the second gate electrode 1402 and the second wiring 1410 through another conductive film, for example, a transparent conductive film, the number of contact holes can be reduced, and the occupied area can be reduced by reducing the number of contact holes.

32(C) shows a top view of the inverter circuit of the drive circuit, in which the cross section taken along the chain line Z1-Z2 corresponds to FIG.

An equivalent circuit of the EDMOS circuit is shown in Fig. 32(B). The circuit connections shown in Fig. 32(A) and Fig. 32(C) correspond to Fig. 32(B), and are an example in which the first thin film transistor 1430 is an enhancement-type n-channel transistor and the second thin film transistor 1431 is a depletion-type n-channel transistor.

Although an example of an EDMOS circuit has been shown in this embodiment, a driver circuit may be configured using an EEMOS circuit in which both transistors are enhancement type n-channel transistors.

In addition, in this embodiment, an example is shown in which no buffer layer is provided, but this is not particularly limited, and buffer layers may be provided on the upper surface of the first wiring 1409, the upper surface of the second wiring 1410, and the upper surface of the third wiring 1411, as in embodiment 1.

This embodiment can be combined with any one of the first to ninth embodiments.

(Embodiment 11) In this embodiment, stress is applied to a thin film transistor having a model structure shown in FIG. 33, and the degree of deterioration of the electrical characteristics is found by calculation.

33A, a gate electrode layer 302 and a gate insulating layer 303 are stacked in this order over a glass substrate 301, and a source electrode layer 304 and a drain electrode layer 305 are formed thereover. An oxide layer 307 is provided on a side surface of the source electrode layer 304, and an oxide layer 308 is provided on a side surface of the drain electrode layer 305. Note that here, the oxide layers 307 and 308 are natural oxide films of the source electrode layer 304 and the drain electrode layer 305. An oxide semiconductor layer 306 is formed to cover the source electrode layer 304, the drain electrode layer 305, and the oxide layers 307 and 308.

The gate electrode layer 302 is made of molybdenum, and the source electrode layer 304 and the drain electrode layer 305 are made of the same material. The gate insulating layer 303 is a silicon oxide film with a thickness of 100 nm and a relative dielectric constant εr of 4.1. The oxide semiconductor layer 306 is made of an In-Ga-Zn-O-based non-single-crystal film with a thickness of 50 nm. The thin film transistor has a channel length L of 10 μm and a channel width W of 10 μm.

The stress applied to the thin film transistor is a gate voltage Vgs=2V and a voltage Vds between the source electrode and the drain electrode=20V. The time for applying this stress is set to 1000 seconds, and the electrical characteristics are compared before and after the application of the stress.

This calculation was performed using the simulation software "Atlas" manufactured by Silvaco.

The calculation was performed with the taper angle θ1 of the source electrode layer 304 set to 27 degrees, 45 degrees, or 63 degrees. The taper angle θ1 of the source electrode layer 304 was set to the same angle as the taper angle θ of the drain electrode layer 305.

FIG. 34 shows the calculation results when the taper angle θ1 of the source electrode layer 304 is 27 degrees.

FIG. 35 shows the calculation results when the taper angle θ1 of the source electrode layer 304 is 45 degrees.

FIG. 36 shows the calculation results when the taper angle θ1 of the source electrode layer 304 is 63 degrees.

From the results of FIGS. 34, 35, and 36, it can be seen that the smaller the taper angle θ1 of the source electrode layer 304, the less likely it is to deteriorate.

For comparison, the results of a similar calculation performed on the structure shown in Fig. 33(B) with an angle of 90 degrees are shown in Fig. 37(A). The structure shown in Fig. 33(B) is the same as Fig. 33(A) except for the angle.

For comparison, the same calculation was performed on the structure shown in FIG. 33(C) in which the taper angle θ1 was set to 27 degrees and an oxide layer was formed on the side surface of the source electrode layer 304 and no oxide layer was formed on the side surface of the drain electrode layer 305. The results are shown in FIG. 37(B). When there was no oxide layer on the side surface, the same results were obtained regardless of the taper angle θ1. When there was no oxide layer on the side surface, the interface between the gate insulating layer 303 and the oxide semiconductor layer 306 became a current path, and therefore, no matter how many degrees the taper angle of the side surface of the source electrode layer 304 was, the current path was not affected.

From these results, it can be said that the deterioration of the electrical characteristics of the thin film transistor can be suppressed by providing the oxide layer 307 on the side surface of the source electrode layer 304 and the oxide layer 308 on the side surface of the drain electrode layer 305 and further by making the taper angle θ1 smaller than 90 degrees.

The embodiment having the above configuration will be described in more detail with reference to the following examples.

<p>In this example, characteristics of a thin film transistor manufactured using an oxide semiconductor layer will be described.</p><p>A method for manufacturing the transistor used in this example will be described below.</p><p>First, a first conductive film was formed on a substrate, and then the first conductive film was patterned by photolithography to form a gate electrode 502. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. The second conductive film and the buffer layer were formed successively without exposing the substrate to the air. Subsequently, the second conductive film and the buffer layer were patterned by photolithography to form a source electrode layer 506a and a drain electrode layer 506b, each of which partially overlaps with the gate electrode. Subsequently, an oxide semiconductor layer was formed on the gate insulating layer, the source electrode layer, and the drain electrode layer, and then the oxide semiconductor layer was patterned by photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere.</p><p>A glass substrate (product name AN100) manufactured by Asahi Glass Co., Ltd. was used as the substrate.</p><p>As a first conductive film to be the gate electrode 502, a tungsten film having a thickness of 100 nm was formed by sputtering.</p><p>As the gate insulating layer 503, a silicon oxynitride film having a thickness of 100 nm was formed by plasma CVD.</p><p>As a second conductive film to be the source electrode layer 506a and the drain electrode layer 506b, a tungsten film was formed to a thickness of 100 nm by a sputtering method.</p><p>The buffer layer was formed by sputtering a 5-10 nm thick In-Ga-Zn-O system non-single crystal film. The film formation conditions were argon gas only, and the target was In.₂O₃:Ga₂O₃A target with a composition of ZnO=1:1:1 was used.</p><p>The oxide semiconductor layer was formed by sputtering a 150 nm In-Ga-Zn-O based non-single crystal film. The film formation conditions were a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of 25°C, an argon gas flow rate of 10 sccm, an oxygen flow rate of 5 sccm, a distance between the glass substrate and the target of 170 mm, and direct current (DC). The target was In₂O₃:Ga₂O₃A target with a composition of In:Ga:ZnO=1:1:1 (In:Ga:Zn=1:1:0.5) was used. After the plasma treatment, an oxide semiconductor layer was continuously formed without exposing the substrate 500 to the atmosphere. The composition of the oxide semiconductor layer obtained under these film formation conditions was measured by inductively coupled plasma mass spectrometry (ICP-MS analysis), and the result was that it was InGa_0.94Zn_0.40O_3.31It was.</p><p>28 shows the Vg-Id curve of the thin film transistor. In this example, the transistor was measured with the drain voltage (drain voltage relative to source voltage) set to 1V.</p><p>29. Specifically, the transistor had a channel length L of 100 μm, a channel width W of 100 μm, an overlapping length Ls between the source electrode layer 506a and the gate electrode 502 of 5 μm, an overlapping length Ld between the drain electrode layer 506b and the gate electrode 502 of 5 μm, and a length A of a region in which the oxide semiconductor layer 510 did not overlap with the source electrode layer 506a and the drain electrode layer 506b in a direction parallel to the channel width direction of 5 μm.</p><p>From the above, it was found that by forming the second conductive film and the buffer layer in succession without exposing the substrate to the air, the on-off ratio of the transistor can be increased and the field-effect mobility can be increased.</p>

<p>In addition, this example shows an example of the electrode shape after etching. First, a process for fabricating a sample will be described with reference to Fig. 30. Note that this example differs from Example 1 only in that the cross-sectional shapes of the source and drain electrode layers are different and that a buffer layer is not formed, and therefore the same reference numerals will be used for the same parts in the description.</p><p>First, a first conductive film was formed over a substrate and then patterned by photolithography to form a gate electrode 502. Subsequently, a gate insulating layer 503 was formed over the gate electrode 502 (see FIG. 30A). Subsequently, a second conductive film was formed over the gate insulating layer 503. Subsequently, the second conductive film was patterned by photolithography to form a source electrode layer 606a and a drain electrode layer 606b that partly overlap with the gate electrode (see FIG. 30B). Subsequently, an oxide semiconductor layer was formed over the gate insulating layer, the source electrode layer, and the drain electrode layer, and then the oxide semiconductor layer was patterned by photolithography to form an island-shaped oxide semiconductor layer 610 that functions as a channel formation region (see FIG. 30C).</p><p>A glass substrate (product name AN100) manufactured by Asahi Glass Co., Ltd. was used as the substrate.</p><p>As a first conductive film to be the gate electrode 502, a tungsten film having a thickness of 100 nm was formed by sputtering.</p><p>As the gate insulating layer 503, a silicon oxynitride film having a thickness of 100 nm was formed by plasma CVD.</p><p>As a second conductive film to be the source electrode layer 606a and the drain electrode layer 606b, a tungsten film was formed to a thickness of 100 nm by a sputtering method.</p><p>The oxide semiconductor layer was formed by sputtering an In-Ga-Zn-O-based non-single crystal film with a thickness of 150 nm under the same film forming conditions as in Example 1.</p><p>The source electrode layer 606a and the drain electrode layer 606b were etched using an ICP etching apparatus with a coil antenna.₄The gas flow rate was 25 sccm, and Cl₂The gas flow rate was 25 sccm, O₂The gas flow rate is set to 10 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-shaped electrode at a pressure of 1.5 Pa to generate plasma and perform etching. 10 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), applying a substantially negative self-bias voltage. By stopping this etching midway when at least some of the gate insulating film 503 is exposed, a stepped electrode side surface is formed.</p><p>Under the above etching conditions, the cross-sectional shape of the source electrode layer 606a can be such that the angle θ1 between the substrate surface of the substrate and the side surface of the lower end of the source electrode layer 606a is 20° or more and less than 90°. FIG. 31A shows a cross-sectional photograph of the portion surrounded by the dotted line in FIG. 30C. FIG. 31B is a schematic diagram of FIG. 31A. As shown in FIG. 31A, θ1 is approximately 40°. Also, as shown in FIG. 31A, the angle between the substrate surface of the substrate and the side surface of the upper end of the source electrode layer 606a is approximately 90°. Note that the cross-sectional shapes of the side surfaces of the source electrode layer 606a and the drain electrode layer 606b that face each other across the oxide semiconductor layer 610 are almost identical because they undergo the same etching process.</p><p>It can be said that this example suggests that the cross-sectional shapes of the source and drain electrode layers described in Embodiment 2 can be manufactured.</p>

100: Substrate

101: Gate electrode

102: Gate insulating layer

103: Oxide semiconductor layer

104a: First buffer layer

104b: second buffer layer

105a: Source electrode layer

105b: Drain electrode layer