Semiconductor device

The present invention relates to a semiconductor device having a circuit composed of thin film transistors, and, for example, to electronic equipment incorporating an electro-optical device such as a liquid crystal display panel or a display device having organic light-emitting elements (EL: electroluminescence elements) as a component.

In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all classified as semiconductor devices.

In recent years, attention has been focused on a technology that constructs thin-film transistors (TFTs) using a semiconductor thin film (with a thickness of several to several hundred nm) formed on a substrate with an insulating surface. Thin-film transistors are widely used in electronic devices such as ICs and electro-optical devices, and their development as switching elements in image display devices is particularly urgent.

In particular, active matrix display devices (liquid crystal display devices and light emitting display devices) in which a switching element made of a transistor is provided for each display pixel arranged in a matrix are being actively developed.

In addition, in order to reduce manufacturing costs, development is also underway to integrate the driver circuitry and pixel section on the same substrate. Among these, transistors using polysilicon film have higher field effect mobility than transistors using amorphous silicon film, enabling high-speed operation.

The modules mounted on the display device have pixel units that display images for each functional block, and driver circuits for controlling the pixel units, such as shift register circuits based on CMOS circuits, level shifter circuits, buffer circuits, and sampling circuits, formed on a single substrate.

In particular, in a light-emitting display device in which organic light-emitting elements are arranged in a matrix, a single pixel requires a plurality of transistors with different functions. Also, in a liquid crystal display device, an attempt is being made to form a switching transistor and a memory element such as an SRAM in a single pixel.

Patent Document 1 describes the use of a transistor with a multi-gate structure as a switching element in an EL display device.

<p><patcit num="1"><text>JP 2001-013893 A</text></patcit></p>

<p>In general, the current flowing between the source and drain regions (channel formation region) of a transistor is controlled by the voltage applied to the gate electrode. If the channel length is sufficiently large, and the voltage applied to the gate electrode is below a certain value (threshold), almost no current flows in the channel formation region. After that, when the voltage applied to the gate electrode exceeds the threshold, the current flowing in the channel formation region begins to increase almost linearly.</p><p>As mentioned above, when the channel length is sufficiently long, the threshold voltage is almost constant, but when the channel length is short, current flows even if the voltage applied to the gate electrode is below the threshold voltage. This is because as the channel length becomes shorter, the drain voltage lowers the voltage barrier at the boundary between the source region and the channel formation region. This phenomenon means that the threshold voltage decreases as the channel length becomes shorter, and is known as a typical example of the short channel effect.</p><p>If the short channel effect occurs in any of the channel formation regions included in a transistor with a multi-gate structure, the transistor characteristics will be impaired, particularly if the short channel effect occurs in the channel formation region adjacent to the source region.</p><p>The present invention has been made in view of the above circumstances, and has an object to provide a novel multi-gate structure transistor with improved operating characteristics and reliability.</p><p>The present invention also provides a novel active matrix type light emitting device structure that can achieve improved reliability.</p>

<p>The present invention prevents the occurrence of defective transistor characteristics by appropriately adjusting the channel lengths of a plurality of channel formation regions.</p><p>One of the features of the present invention is that in a transistor with a multi-gate structure (a structure having a semiconductor layer including at least two or more channel formation regions connected in series and at least two or more gate electrodes that apply an electric field to each of the channel formation regions), the channel length of the channel formation region adjacent to the source region among the multiple channel formation regions is made longer than the channel length of the channel formation region adjacent to the drain region.</p><p>Another feature of the present invention is that at least the channel length of the channel formation region adjacent to the source region is set to a length that does not cause a short channel effect.</p><p>One of the features of the present invention is that a semiconductor layer, two gate electrodes, and a source electrode and a drain electrode are provided on a substrate having an insulating surface, the semiconductor layer having a source region, a drain region, a first channel formation region in contact with the source region, a second channel formation region in contact with the drain region, and a high-concentration impurity region located between the first channel formation region and the second channel formation region, the two gate electrodes are located on the first channel formation region or the second channel formation region via a first insulating film, the source electrode and the drain electrode are connected to the semiconductor layer via contact holes provided in a second insulating film, the first channel formation region and the second channel formation region are connected in series, and the channel length of the first channel formation region is longer than the channel length of the second channel formation region.</p><p>The present invention also relates to a semiconductor device having a semiconductor layer, two gate electrodes, and a source electrode and a drain electrode on a substrate having an insulating surface, the semiconductor layer having a source region, a drain region, a first channel formation region in contact with the source region, a second channel formation region in contact with the drain region, and a high-concentration impurity region located between the first channel formation region and the second channel formation region, the two gate electrodes are located on the first channel formation region or the second channel formation region via a first insulating film, the source electrode and the drain electrode are connected to the semiconductor layer via contact holes provided in the second insulating film, the first channel formation region and the second channel formation region are connected in series, and a channel length of the first channel formation region is defined as L.₁The channel length of the second channel forming region is L₂When L₁2×L₂One of the features of this method is that the following relation holds true:</p><p>The present invention also has one feature that a semiconductor layer, two gate electrodes, and a source electrode and a drain electrode are provided on a substrate having an insulating surface, the semiconductor layer having a source region, a drain region, a first low concentration impurity region in contact with the source region, a first channel formation region in contact with the first low concentration impurity region, a second low concentration impurity region in contact with the drain region, a second channel formation region in contact with the second low concentration impurity region, and a high concentration impurity region located between the first channel formation region and the second channel formation region, the two gate electrodes are located on the first channel formation region or the second channel formation region via a first insulating film, the source electrode and the drain electrode are connected to the semiconductor layer via a second insulating film, the first channel formation region and the second channel formation region are connected in series, and a channel length of the first channel formation region is longer than a channel length of the second channel formation region.</p><p>The present invention also relates to a semiconductor device having a semiconductor layer, two gate electrodes, and a source electrode and a drain electrode on a substrate having an insulating surface, the semiconductor layer having a source region, a drain region, a first low concentration impurity region in contact with the source region, a first channel formation region in contact with the first low concentration impurity region, a second low concentration impurity region in contact with the drain region, a second channel formation region in contact with the second low concentration impurity region, and a high concentration impurity region located between the first channel formation region and the second channel formation region, the two gate electrodes are located on the first channel formation region or the second channel formation region via a first insulating film, the source electrode and the drain electrode are connected to the semiconductor layer via a second insulating film, the first channel formation region and the second channel formation region are connected in series, and a channel length of the first channel formation region is defined as L.₁The channel length of the second channel forming region is L₂When L₁2×L₂One of the features of this method is that the following relation holds true:</p><p>Another feature of the present invention is a semiconductor layer, two gate electrodes, and a source electrode and a drain electrode on a substrate having an insulating surface, the semiconductor layer having a source region, a drain region, a first low concentration impurity region in contact with the source region, a first channel formation region in contact with the first low concentration impurity region, a second low concentration impurity region in contact with the drain region, a second channel formation region in contact with the second low concentration impurity region, and a high concentration impurity region located between the first channel formation region and the second channel formation region, the first low concentration impurity region and the second low concentration impurity region having portions overlapping with the gate electrode, the source electrode and the drain electrode are connected to the semiconductor layer via a second insulating film, the first channel formation region and the second channel formation region are connected in series, and a channel length of the first channel formation region is longer than a channel length of the second channel formation region.</p><p>The present invention also relates to a semiconductor device having a semiconductor layer, two gate electrodes, and a source electrode and a drain electrode on a substrate having an insulating surface, the semiconductor layer having a source region, a drain region, a first low concentration impurity region in contact with the source region, a first channel formation region in contact with the first low concentration impurity region, a second low concentration impurity region in contact with the drain region, a second channel formation region in contact with the second low concentration impurity region, and a high concentration impurity region located between the first channel formation region and the second channel formation region, the first low concentration impurity region and the second low concentration impurity region having portions overlapping with the gate electrode, the source electrode and the drain electrode are connected to the semiconductor layer via a second insulating film, the first channel formation region and the second channel formation region are connected in series, and a channel length of the first channel formation region is L.₁The channel length of the second channel forming region is L₂When L₁2×L₂One of the features of this method is that the following relation holds true:</p><p>In the present invention, specifically, the channel length L₁has a length of 2 μm or more and 10 μm or less, and the channel length L₂has a length of 1 μm or more, and the channel length L₁Another feature is that it is at least 0.5 μm smaller than the</p><p>Another feature of the present invention is that the impurity is an impurity that imparts p-type conductivity and belongs to Group 13 of the periodic table, such as boron.</p><p>In the present invention, the two gate electrodes are electrically connected to each other.</p><p>In the present invention, the high concentration impurity region has a concentration similar to that of the source region or the drain region, and the first low concentration impurity region and the second low concentration impurity region have a concentration lower than that of the source region or the drain region.</p><p>In an active matrix light-emitting device including a thin film transistor and a light-emitting element, it is desirable to reduce the thickness of the partition wall arranged to cover the end of the first electrode of the light-emitting element in terms of manufacturing costs. If the thickness of the partition wall is made too thin, the partition wall may not be able to cover the steps caused by the wiring or the residues generated during the wiring formation, which may cause a short circuit between the second electrode formed on the partition wall and the first electrode.</p><p>Therefore, the inventors have devised a structure for preventing short circuits by forming a partition wall after forming an inorganic insulating film with a thickness of less than 300 nm. The inorganic insulating film covers at least the upper end of the wiring electrically connected to the TFT, and a first electrode is formed on the inorganic insulating film.</p><p>Another configuration of the present invention disclosed in this specification, as shown in FIG. 10 , is a semiconductor device having one of the features, comprising: a semiconductor layer on a substrate having an insulating surface; a gate insulating film on the semiconductor layer; a gate electrode on the gate insulating film; a first insulating film on the gate electrode; a wiring electrically connected to the semiconductor layer on the first insulating film through an opening formed in the first insulating film; a second insulating film in contact with a part of an upper surface of the wiring and an upper surface of the first insulating film; a first electrode electrically connected to the wiring through an opening formed in the second insulating film and in contact with the upper surface of the second insulating film; a partition wall covering an end of the first electrode on the second insulating film; a layer having an organic compound on the first electrode; and a second electrode on the partition wall and the layer having the organic compound, and the opening formed in the first insulating film is located at a position overlapping with an opening in the second insulating film.</p><p>By providing a fourth interlayer insulating film 700 made of a thin inorganic insulating film as shown in FIG. 10, steps caused by wiring and residues generated during wiring formation can be covered, preventing short circuits and improving the reliability of the light emitting device.</p><p>Furthermore, the TFT electrically connected to the first electrode is not limited to a single-gate structure, but may be a multi-gate structure having a plurality of gate electrodes on a gate insulating film.</p><p>In the above configuration, one of the features is that the first electrode is in contact with at least a part of the upper surface of the wiring (i.e., the drain electrode) connected to the semiconductor layer. If the first electrode is formed so as to cover the opening of the second insulating film, there is an advantage that the contact area can be made constant even if the formation position of the first electrode is slightly shifted, and the manufacturing margin can be made wider.</p><p>In order to increase the contact area and reduce resistance, the first electrode may contact the side surface as well as the top surface of the wiring. In the above configuration, one of the features is that the first electrode contacts at least a portion of the side surface of the wiring that is connected to the semiconductor layer.</p><p>Furthermore, if the contact area is sufficient, there is no particular need for the first electrode to cover the opening in the second insulating film. If it does not cover it, the structure will be such that the wiring connected to the semiconductor layer contacts the partition wall through the opening in the second insulating film.</p><p>Another feature of the above configuration is that the first insulating film has an opening on the semiconductor layer, the semiconductor layer and the wiring are in contact with each other through the opening, and the opening of the first insulating film overlaps with the opening of the second insulating film. By overlapping the positions of the opening of the first insulating film and the opening of the second insulating film, the area required for connecting the TFT and the light-emitting element is reduced, and the aperture ratio of the light-emitting display device is improved. Even if the opening of the first insulating film and the opening of the second insulating film overlap, the recessed portion is covered with a partition wall, so that short circuits can be prevented.</p><p>The second insulating film is thinner than the first insulating film, and is 50 nm or more and less than 300 nm in thickness. It is preferable that the second insulating film is thinner than the wiring connected to the semiconductor layer.</p><p>The first insulating film and the second insulating film are preferably a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO_xN_yCompared to organic insulating films, these inorganic insulating films are able to protect light emitting elements from moisture and oxygen, which are believed to be the causes of deterioration of light emitting elements.</p>

<p>According to the present invention, it is possible to provide an n-channel transistor having a multi-gate structure with reduced off-current and improved transistor characteristics. Furthermore, it is possible to improve the reliability of a semiconductor device including an n-channel transistor having this multi-gate structure, and also to improve the reliability of an electronic device including the semiconductor device. The off-current is a leakage current that flows when a potential of a polarity that does not form an inversion layer is applied to a transistor. The off-current also refers to a current that flows in a place where it should not flow when a transistor is used as a switching element. Furthermore, according to the present invention, it is possible to suppress characteristic defects of p-channel transistors (specifically, characteristic defects in the form of a lump that occurs in the rising region of the Id-Vg curve).</p><p>In addition, the present invention, which covers the upper end of the wiring with an inorganic insulating film having a thickness of less than 300 nm, can reduce display defects called dark spots caused by residues generated during wiring formation in the manufacture of a light-emitting display device. Note that display defects called dark spots refer to pixels that do not achieve the desired emission luminance when the light-emitting display device is operated, and have a lower emission luminance than other pixels.</p>

<figref num="1">FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to the present invention.</figref><figref num="2">1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device of the present invention.</figref><figref num="3">1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device of the present invention.</figref><figref num="4">FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to the present invention.</figref><figref num="5">1 is a diagram showing an example of a method for manufacturing a semiconductor device of the present invention;</figref><figref num="6">1 is a diagram showing an example of a method for manufacturing a semiconductor device of the present invention;</figref><figref num="7">FIG. 1 is a cross-sectional view showing an example of a light-emitting device of the present invention.</figref><figref num="8">FIG. 1 is a top view of a pixel portion of a light-emitting device according to the present invention.</figref><figref num="9">FIG. 1 is a diagram showing an example of an equivalent circuit of a pixel portion of a light-emitting device.</figref><figref num="10">FIG. 1 is a cross-sectional view showing an example of a light-emitting device of the present invention.</figref><figref num="11">FIG. 1 is a cross-sectional view showing an example of a light-emitting device of the present invention.</figref><figref num="12">FIG. 1 shows an example of a module of the present invention.</figref><figref num="13">FIG. 1 is a cross-sectional view showing an example of a module of the present invention.</figref><figref num="14">FIG. 1 is a diagram showing an example of an electronic device.</figref><figref num="15">FIG. 1 is a diagram showing an example of an electronic device.</figref><figref num="16">FIG. 1 is a diagram showing an example of the gate voltage dependency of the drain current of a semiconductor device according to the present invention.</figref><figref num="17">A diagram showing an example of calculation results for characteristic failure</figref><figref num="18">3A and 3B are a schematic cross-sectional view and a cross-sectional STEM image of a connection portion between a first electrode of a light-emitting element and a wiring.</figref><figref num="19">3A and 3B are a schematic cross-sectional view and a cross-sectional STEM image of a connection portion between a first electrode of a light-emitting element and a wiring.</figref><figref num="20">3A and 3B are a schematic cross-sectional view and a cross-sectional STEM image of a connection portion between a first electrode of a light-emitting element and a wiring.</figref>

Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In addition, in the configuration of the present invention described below, the same reference numerals are used in common between different drawings to indicate the same parts.

(Embodiment 1) The present invention relates to a transistor having a multi-gate structure. Hereinafter, the transistor will be referred to as a TFT. An embodiment of the present invention will be specifically described with reference to FIG.

Fig. 1(a) shows an example of a cross-sectional view of a TFT having a multi-gate structure of the present invention, and Fig. 1(b) shows a schematic diagram of the top surface. The cross-section taken along the chain line A-A' in Fig. 1(b) corresponds to the cross-sectional view in Fig. 1(a). In this embodiment, an example of a TFT having two gate electrodes and two channel formation regions connected in series will be described.

In the TFT of the present invention, a first insulating film 11 is formed on a substrate 10, and a semiconductor layer 12 is formed on the first insulating film 11. A second insulating film 13 is formed on the semiconductor layer 12, and two gate electrodes are formed on the second insulating film 13. A third insulating film 16 and a fourth insulating film 17 are formed as interlayer insulating films on the two gate electrodes.

The semiconductor layer 12 includes a source region 24 and a drain region 25 located outside the two gate electrodes via the second insulating film 13, two channel formation regions connected in series and located between the source region 24 and the drain region 25, and a high concentration impurity region 23 located between the two channel formation regions. The high concentration impurity region 23 is a region containing impurities at a concentration similar to that of the source region 24 or the drain region 25.

In this embodiment, of the two channel formation regions, the channel formation region in contact with the source region 24 is defined as a first channel formation region 21, and the channel formation region in contact with the drain region 25 is defined as a second channel formation region 22. Of the two gate electrodes, the gate electrode located on the first channel formation region 21 via the second insulating film 13 is defined as a first gate electrode 14, and the gate electrode located on the second channel formation region 22 via the second insulating film 13 is defined as a second gate electrode 15.

In this embodiment, the two gate electrodes have a laminated structure made up of two conductive layers 31a, 31b, and 32a, 32b, but the present invention is not limited to this, and may have a single layer structure or a laminated structure made up of three or more conductive layers. The two gate electrodes are electrically connected to each other.

Contact holes are opened in the second insulating film 13, the third insulating film 16, and the fourth insulating film 17 so as to reach the source region 24 and the drain region 25, respectively. A source electrode 18 is formed in the contact hole portion reaching the source region 24, and a drain electrode 19 is formed in the contact hole portion reaching the drain region 25.

In the present invention, the impurity region located between the two channel formation regions 21, 22 is defined as a high-concentration impurity region 23, and the high-concentration impurity region 23 functions as a drain region for a source region 24 of a TFT having a first gate electrode 14 (hereinafter referred to as a first TFT).

On the other hand, it functions as a source region for the drain region 25 of the TFT (second TFT) having the second gate electrode 15. In addition, the high-concentration impurity region 23 located between the two channel formation regions 21 and 22 is very effective in reducing the off-current of the n-channel TFT.

The TFT of the present invention is characterized in that the channel length L₁is the channel length L of the second channel forming region 22₂The channel length means the length of a channel forming region which is a current path connecting a source region and a drain region formed under a gate electrode, and in the TFT of this embodiment, the distance between the source region 24 and the high concentration impurity region 23 (drain region) is called the channel length L₁The distance between the high concentration impurity region 23 (source region) and the drain region 25 is defined as the channel length L₂Let us assume that.

In addition, the TFT of the present invention has a channel length L₁, L₂In L₁&gt;L₂(Preferably 3 x L₁5×L₂, more preferably L₁2×L₂) is one of the features of this system.

In the present invention, the channel length L₁, L₂is not limited to a specific numerical range, but is at least the channel length L₁has a length that does not cause short channel effects, specifically, L₁The channel length L₂has a length of 1 μm or more, and L₁The channel width is set to 1 to 50 μm (preferably 5 to 30 μm).

In addition, the channel length L₁has approximately the same length as the first gate electrode 14 (first conductive layer 31a), and the channel length L₂has substantially the same length as the second gate electrode 15 (first conductive layer 31b). Therefore, one of the features of the TFT of the present invention is that the size of the first gate electrode 14 in the channel length direction is larger than that of the second gate electrode 15.

In the present embodiment, a multi-gate TFT having two gate electrodes 14, 15 and two channel formation regions 21, 22 connected in series has been described, but the present invention is not limited to this, and a multi-gate TFT having three or more gate electrodes and three or more channel formation regions connected in series may also be used. Note that even when three or more gate electrodes are provided, the gate electrodes are considered to be electrically connected.

In this embodiment, by applying the TFT having the multi-gate structure of the present invention, it is possible to prevent the TFT from having poor characteristics, and as a result, it is possible to improve the operating characteristics and reliability of the TFT.

The TFT of the present invention can be applied to both n-channel TFTs and p-channel TFTs. When the n-channel TFT has a multi-gate structure, the off-current can be reduced. When the p-channel TFT has a multi-gate structure, the occurrence of characteristic defects (specifically, characteristic defects in the form of lumps occurring in the rising region of the Id-Vg curve) can be prevented.

(Embodiment Mode 2) In this embodiment mode, an example of a method for manufacturing a TFT having a multi-gate structure of the present invention will be described with reference to FIGS.

First, a first insulating film 101 is formed on a substrate 100 having an insulating surface. As the substrate 100 having an insulating surface, a substrate having light transmission properties, for example, a glass substrate, a crystallized glass substrate, or a plastic substrate (polyimide, acrylic, polyethylene terephthalate, polycarbonate, polyarylate, polyethersulfone, etc.) can be used. When the TFT formed later is applied to a top emission type (upward emission type) light emitting display device or a reflective type liquid crystal display device, a ceramic substrate, a semiconductor substrate, a metal substrate (tantalum, tungsten, molybdenum, etc.) can also be used. Note that it is sufficient to use a substrate that can withstand at least the heat generated during the process.

The first insulating film 101 is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO_xN_yThe first insulating film 101 may be formed by a known method (such as a sputtering method, an LPCVD method, or a plasma CVD method). In this embodiment, the first insulating film 101 is a single layer, but it may be a multi-layer structure of two or more layers.

Next, as shown in FIG. 2( a ), a semiconductor layer 102 is formed on the first insulating film 101 .

Silicon or a silicon germanium (SiGe) alloy can be used as the semiconductor layer 102. First, an amorphous semiconductor film is formed by a known means (such as a sputtering method, an LPCVD method, or a plasma CVD method), and then crystallized by a known crystallization process (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalytic element such as nickel) to obtain a crystalline semiconductor film.

When a crystalline semiconductor film is formed by thermal crystallization, a heating furnace, laser irradiation, or RTA (Rapid Thermal Annealing), or a combination of these, can be used.

Furthermore, when the crystalline semiconductor film is formed by thermal crystallization using a catalytic element such as nickel, it is preferable to perform a gettering process for removing the catalytic element such as nickel after crystallization.

In addition, when forming a crystalline semiconductor film by the laser crystallization method, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beams that can be used here include gas lasers such as Ar lasers, Kr lasers, and excimer lasers, and single crystal YAG and YVO₄, forsterite (Mg₂SiO₄), YAlO₃, GdVO₄, or polycrystalline (ceramic) YAG, Y₂O₃, YVO₄, YAlO₃, GdVO₄The laser used may be one or more of a laser medium containing one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta as a dopant, a glass laser, a ruby laser, an alexandrite laser, a Ti:sapphire laser, a copper vapor laser, or a gold vapor laser. By irradiating the fundamental wave of such a laser beam, or a laser beam of the second to fourth harmonics of the fundamental wave, it is possible to obtain crystals with a large grain size. For example, Nd:YVO₄The second harmonic (532 nm) or third harmonic (355 nm) of a laser (fundamental wave 1064 nm) can be used. In this case, the power density of the laser is 0.01 to 100 MW/cm.²(preferably 0.1 to 10 MW/cm²) is necessary. The scanning speed is set to about 10 to 2000 cm/sec for irradiation.

In addition, single crystal YAG and YVO₄, forsterite (Mg₂SiO₄), YAlO₃, GdVO₄, or polycrystalline (ceramic) YAG, Y₂O₃, YVO₄, YAlO₃, GdVO₄Lasers using a medium containing one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta as dopants, Ar ion lasers, and Ti:sapphire lasers can be made to oscillate continuously, and can also be made to oscillate in pulses at an oscillation frequency of 10 MHz or more by performing Q-switching, mode locking, etc. When a laser beam is oscillated at an oscillation frequency of 10 MHz or more, the next pulse is irradiated onto the semiconductor film between the time when the semiconductor film is melted by the laser and the time when it solidifies.

Therefore, unlike the case where a pulsed laser with a low oscillation frequency is used, the solid-liquid interface can be moved continuously in the semiconductor film, so that crystal grains that grow continuously in the scanning direction can be obtained.

When ceramics (polycrystal) is used as the medium, it is possible to form the medium into any shape at low cost and in a short time. When using a single crystal, a cylindrical medium with a diameter of several mm and a length of several tens of mm is usually used, but when using ceramics, it is possible to make something even larger.

The concentration of dopants such as Nd and Yb in the medium, which directly contributes to light emission, cannot be changed significantly in either single crystal or polycrystal, so there is a certain limit to how much the laser output can be improved by increasing the concentration. However, in the case of ceramics, the size of the medium can be significantly larger than in single crystals, so a significant increase in output can be expected.

Furthermore, in the case of ceramics, it is possible to easily form a medium in the shape of a parallelepiped or a rectangular parallelepiped. If a medium of such a shape is used and the oscillation light is made to proceed in a zigzag manner inside the medium, the oscillation light path can be made longer. Therefore, the amplification becomes large and it becomes possible to oscillate with a high output. In addition, since the cross-sectional shape of the laser beam emitted from a medium of such a shape is a square shape at the time of emission, it is advantageous to shape it into a linear beam compared to a round beam. By shaping the laser beam thus emitted using an optical system, it is possible to easily obtain a linear beam with a short side length of 1 mm or less and a long side length of several mm to several meters. In addition, by uniformly irradiating the medium with excitation light, the linear beam has a uniform energy distribution in the long side direction.

By irradiating the semiconductor film with this linear beam, it is possible to perform a more uniform heat treatment over the entire surface of the semiconductor film. If uniform heat treatment is required up to both ends of the linear beam, it is necessary to devise a method such as placing slits on both ends to block the areas where the energy is attenuated.

When a semiconductor film is heat-treated using the linear beam having a uniform intensity thus obtained, and an electronic device is manufactured using this semiconductor film, the characteristics of the electronic device are excellent and uniform.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped into the crystalline semiconductor film obtained in the above crystallization step in order to control the threshold voltage of the TFT.₂H₆) is plasma-excited without being mass-separated, using an ion doping method.

Furthermore, if necessary, the surface of the crystalline semiconductor film is washed with an etchant containing hydrofluoric acid, and then a first resist mask is formed on the crystalline semiconductor film. Then, the crystalline semiconductor film is patterned into a desired shape using the first resist mask to form the semiconductor layer 102.

This semiconductor layer 102 may be formed to a thickness of 25 to 80 nm (preferably 30 to 70 nm), and then the first resist mask is removed.

Next, a second insulating film 103 (a film that functions as a gate insulating film) is formed to cover the semiconductor layer 102. As the second insulating film 103, an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used. The second insulating film 103 may be formed to a thickness of 1 to 200 nm (preferably 50 to 120 nm) by using a plasma CVD method, a sputtering method, or a thermal oxidation method.

Next, the first gate electrode 107a and the second gate electrode 107b are formed. First, as shown in FIG. 2(b), the first conductive layer 104 and the second conductive layer 105 are laminated on the second insulating film 103. The first conductive layer 104 and the second conductive layer 105 can be made of a conductive material such as a high-melting point metal, such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound mainly containing a high-melting point metal. The first conductive layer 104 and the second conductive layer 105 may be made of the same conductive material or different conductive materials. In addition, although the laminated structure of two conductive layers is used in this embodiment, it may be made of one layer, or may be made of three or more layers. The first conductive layer 104 and the second conductive layer 105 can be formed by known methods such as sputtering and vapor deposition, and the first conductive layer 104 can be formed to a thickness in the range of 10 to 100 nm (preferably 20 to 50 nm), and the second conductive layer 105 can be formed to a thickness in the range of 100 to 600 nm (preferably 300 to 500 nm).

Next, second resist masks 106 a and 106 b are formed over the second conductive layer 105 .

At this time, the second resist mask 106a is formed above the second conductive layer 105a on which the first gate electrode 107a will be formed later, and the second resist mask 106b is formed above the second conductive layer 105b on which the second gate electrode 107b will be formed later. The second resist mask 106a is formed to be larger than the second resist mask 106b.

Next, the first etching process and the second etching process are performed using the second resist masks 106a and 106b. The first etching process forms the shape shown in FIG. 2(c), and then the second etching process is performed. The etching method used in the first etching process and the second etching process may be appropriately selected, but in order to improve the etching rate, a dry etching device using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) may be used. By appropriately adjusting the etching conditions of the first etching process and the second etching process, the ends of the first conductive layer 104 and the second conductive layer 105 can be formed to have a desired tapered shape. Through the above steps, as shown in FIG. 2(d), a first gate electrode 107a made of a stack of the first conductive layer 104a and the second conductive layer 105a and a second gate electrode 107b made of a stack of the first conductive layer 104b and the second conductive layer 105b are formed. Thereafter, the second resist masks 106a and 106b are removed.

Next, using the first gate electrode 107a and the second gate electrode 107b as a mask, one conductivity type impurity is added to the semiconductor layer 102 to form a source region 108, a drain region 109, and a high concentration impurity region 110. At this time, as shown in FIG. 3(a), a region to which the one conductivity type impurity ions are not added becomes a channel formation region. A plurality of channel formation regions, two in this case, are formed in the semiconductor layer 102. In this specification, the channel formation region located under the first gate electrode 107a is referred to as a first channel formation region 111, and the channel formation region located under the second gate electrode 107b is referred to as a second channel formation region 112.

A one-conductivity type impurity region sandwiched between the first channel formation region 111 and the second channel formation region 112 is defined as a high-concentration impurity region 110. The one-conductivity type impurity to be added may be either a p-type impurity or an n-type impurity.

Here, the channel length L of the first channel forming region 111 of the TFT formed in this embodiment₁is the channel length L of the second channel formation region 112₂Specifically, the channel length L₁, L₂In L₁&gt;L₂(Preferably 3 x L₁5×L₂, more preferably L₁2×L₂) should be formed so that the following relation holds true.

In addition, the channel length L₁, L₂is not limited to a specific range, and should be at least as long as the channel length L₁It is sufficient that the length of L does not cause the short channel effect.₁It is preferable that the channel length L is in the range of 2 to 8 μm (typically 4 to 6 μm).₂has a length of 1 μm or more, and L₁It is preferable to form the channel width so that it is 0.5 μm or more shorter than the channel width. The channel width may be formed in the range of 1 to 50 μm (preferably 5 to 30 μm).

In addition, the channel length L of the first channel formation region 111₁, the channel length L of the second channel formation region 112₂In L₁&gt;L₂(Preferably 3 x L₁5×L₂, more preferably L₁2×L₂It is necessary to design the size (shape) of the first conductive layers 104a and 104b in advance so that the following relational expression holds true.

Furthermore, low concentration impurity regions (hereinafter referred to as LDD regions) may be formed in the semiconductor layer 102. The LDD regions may be formed in a self-aligned manner using the patterns of the second conductive layers 105a and 105b, or may be formed using a new resist mask.

Next, an interlayer insulating film is formed. In this embodiment, as shown in FIG. 3(b), a third insulating film 113 and a fourth insulating film 114 are laminated as the interlayer insulating film. As the third insulating film 113 and the fourth insulating film 114, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO_xN_y), or a low-dielectric-constant organic resin film (photosensitive or non-photosensitive organic resin film). A film containing siloxane may also be used. Siloxane is a material whose skeletal structure is formed by bonds between silicon (Si) and oxygen (O). An organic group (e.g., an alkyl group, an aromatic hydrocarbon) is used as the substituent. A fluoro group may also be used as the substituent. Alternatively, an organic group and a fluoro group may both be used as the substituent.

Note that the third insulating film 113 and the fourth insulating film 114 may be the same or different insulating films. In addition, although the interlayer insulating film has a two-layer structure in this embodiment, it may have a one-layer structure or a three-layer or more layer structure.

The third insulating film 113 and the fourth insulating film 114 may be formed by using a known method (sputtering, LPCVD, plasma CVD, spin coating, etc.), and when an organic resin film or a film containing siloxane is used, they may be formed by using a coating method.

Next, the semiconductor layer to which the impurity element is added is activated and hydrogenated. When crystallization is performed by a thermal crystallization method using a catalytic element such as nickel, gettering can be performed simultaneously with activation to reduce nickel in the channel formation region. Specifically, nickel contained in the channel formation region can be moved to the source region or drain region by heat treatment during activation. As a result, nickel contained in the channel formation region can be reduced.

Next, a third resist mask is formed on the fourth insulating film (interlayer insulating film) 114. Then, the second insulating film 103, the third insulating film 113, and the fourth insulating film 114 are selectively etched using the third resist mask to form contact holes reaching the semiconductor layer 102 (the source region 108 or the drain region 109). Thereafter, the third resist mask is removed.

Next, as shown in FIG. 3(c), a source electrode 115 and a drain electrode 116 are formed.

First, a metal laminate film is formed on the fourth insulating film 114 (a film that functions as an interlayer insulating film).

As the metal laminate film, metals such as gold (Ag), silver (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), rhodium (Rh), tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), cadmium (Cd), zinc (Zn), iron (Fe), titanium (Ti), silicon (Si), germanium (Ge), zirconium (Zr), barium (Ba), or alloys thereof, or metal nitrides thereof, or laminate films thereof, can be used.

In this embodiment, the metal laminated film has a three-layer structure. The metal laminated film may be formed by a known method such as PVD, CVD, sputtering, or vapor deposition, with the total thickness of the laminated film being in the range of 500 nm to 2 μm (preferably 800 nm to 1 μm). It is preferable to form the layers continuously in the same metal sputtering device. The metal laminated film may have one or two layers, or may have a four or more layer structure.

Next, a fourth resist mask is formed on the metal laminate film. Then, the metal laminate film is selectively etched using the fourth resist mask to form a source electrode 115 electrically connected to the source region 108 and a drain electrode 116 electrically connected to the drain region 109. Then, the fourth resist mask is removed.

In addition, connection electrodes (electrodes that electrically connect multiple TFTs) and terminal electrodes (electrodes for connecting to an external power source) can also be formed on the fourth insulating film 114 at the same time as the source electrodes 115 and drain electrodes 116 of the TFTs.

Through the above steps, a TFT having a multi-gate structure is completed.

(Embodiment 3) In this embodiment, a case where a semiconductor layer includes an LDD region will be described with reference to FIG.

Since the structure other than the semiconductor layer is the same as that of the first or second embodiment, a description thereof will be omitted.

The semiconductor layer of the TFT shown in Fig. 4(a) of this embodiment includes two channel formation regions (first channel formation region 401, second channel formation region 402) connected in series, a high concentration impurity region 403 located between the two channel formation regions, a source region 404 and a drain region 405 located outside the two gate electrodes (first gate electrode, second gate electrode) via a second insulating film, a pair of first LDD regions 406a, 406b located between the source region 404 and the first channel formation region 401 and between the first channel formation region 401 and the high concentration impurity region 403, and a pair of second LDD regions 407a, 407b located between the drain region 405 and the second channel formation region 402 and between the second channel formation region 402 and the high concentration impurity region 403. The first gate electrode and the second gate electrode are electrically connected.

In the TFT shown in FIG. 4(a) of this embodiment, the channel length L₁is the channel length L of the second channel forming region 402₂That is, the channel length L₁, L₂In,,L₁&gt;L₂(Preferably 3 x L₁5×L₂, more preferably L₁2×L₂One of the features of this method is that the following relationship holds:

In the TFT shown in FIG. 4(a) of this embodiment, the channel length L₁is approximately the same length as the second conductive layer forming the first gate electrode, and the channel length L₂The channel length L of the first channel forming region 401 is approximately the same as that of the second conductive layer forming the second gate electrode, but is not limited to this.₁is the channel length L of the second channel forming region 402₂The bigger the better.

Furthermore, the TFT shown in FIG. 4(a) of this embodiment is also characterized in that the first LDD regions 406a, 406b have a region overlapping the first gate electrode via a second insulating film, and the second LDD regions 407a, 407b have a region overlapping the second gate electrode via a second insulating film.

In the TFT shown in Fig. 4(a) of this embodiment, the first LDD regions 406a and 406b have substantially the same length as the first conductive layer portion not overlapping the second conductive layer forming the first gate electrode, and the second LDD regions 407a and 407b have substantially the same length as the first conductive layer portion not overlapping the second conductive layer forming the second gate electrode, but the present invention is not limited to this. That is, it is sufficient that the first LDD regions 406a and 406b have a region overlapping the first gate electrode, and the second LDD regions 407a and 407b have a region overlapping the second gate electrode.

4(a) of this embodiment, a pair of first LDD regions 406a and 406b are provided on either side of the first channel formation region 401, but the present invention is not limited to this, and the first LDD regions 406a and 406b may be provided on only one side. Similarly, the second LDD regions 407a and 407b may be provided on only one side.

4(a), the concentration of the high concentration impurity region 403 is approximately the same as that of the source region 404 or the drain region 405. The concentrations of the first low concentration impurity regions 406a, 406b and the second low concentration impurity regions 407a, 407b are lower than that of the source region 404 or the drain region 405.

Next, a case where a semiconductor layer includes two channel formation regions 411 and 412, a high concentration impurity region 413, a source region 414, a drain region 415, first LDD regions 416a and 416b, and second LDD regions 417a and 417b will be described with reference to Fig. 4(b). Fig. 4(b) has the same structure as Fig. 4(a) except for the positions where the LDD regions are provided, so the description will be omitted.

In FIG. 4(b), first LDD regions 416a, 416b are located outside the first gate electrode via a second insulating film, and similarly, second LDD regions 417a, 417b are located outside the second gate electrode via a second insulating film.

4(b), one of the features is that the first LDD regions 416a and 416b have regions that do not overlap the first gate electrode through the second insulating film, and the second LDD regions 417a and 417b have regions that do not overlap the second gate electrode through the second insulating film. Note that the first gate electrode and the second gate electrode are electrically connected.

In FIG. 4B, the first LDD regions 416a and 416b are formed outside the first gate electrode via the second insulating film, so that the channel length L₁The length of the second LDD regions 417a and 417b is approximately the same as that of the first gate electrode (first conductive layer). Similarly, the second LDD regions 417a and 417b are formed outside the second gate electrode via the second insulating film, so that the channel length L₂The channel length L of the first channel forming region 411 is approximately the same as that of the second gate electrode (first conductive layer). However, the present invention is not limited to this.₁is the channel length L of the second channel forming region 412.₂That is, the channel length L₁, L₂In L₁&gt;L₂(Preferably 3 x L₁5×L₂, more preferably L₁2×L₂) is a characteristic of the present invention.

4B, a pair of first LDD regions 406a and 406b are provided on either side of the first channel formation region 411, but the present invention is not limited to this, and the first LDD regions 406a and 406b may be provided on only one side. Similarly, the second LDD regions 407a and 407b may be provided on only one side.

4(b), the concentration of the high concentration impurity region 413 is approximately the same as that of the source region 414 or the drain region 415. The concentrations of the first low concentration impurity regions 416a, 416b and the second low concentration impurity regions 417a, 417b are lower than that of the source region 414 or the drain region 415.

(Embodiment Mode 4) In this embodiment mode, a structure and a manufacturing method of an active matrix light emitting device in which a pixel portion and a driver circuit portion are formed over the same substrate will be described with reference to FIGS.

Each pixel is formed with a first TFT (hereinafter referred to as a switching TFT) that functions as a switching element that determines whether a video signal is input to the pixel or not, and a second TFT (hereinafter referred to as a driving TFT) that controls a current to the light-emitting element. Furthermore, a TFT that drives the pixel section is formed in the driving circuit section. One of the features of this embodiment is that the TFT of the present invention is used as a driving TFT formed in the pixel section.

First, base insulating films 501a and 501b are formed on a substrate 500. When the substrate 500 side is used as a display surface to extract light emission, a light-transmitting glass substrate or a quartz substrate may be used as the substrate 500. A light-transmitting plastic substrate having heat resistance capable of withstanding the processing temperature during the process may also be used. When the surface opposite to the substrate 500 side is used as a display surface to extract light emission, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may also be used in addition to the above-mentioned substrates. A substrate capable of withstanding at least the heat generated during the process may be used, and in this embodiment, a glass substrate is used as the substrate 500. The refractive index of the glass substrate is about 1.55.

The base insulating films 501a and 501b are formed of insulating films such as silicon oxide film, silicon nitride film, or silicon oxynitride film, and are formed as a single layer or two or more layers. The base insulating films 501a and 501b are formed by known means such as sputtering, LPCVD, or plasma CVD. In this embodiment, the base insulating films 501a and 501b have a two-layer structure of silicon oxynitride films with different composition ratios. The first layer base insulating film 501a is formed by plasma CVD, and SiH₄, N.H.₃, and N₂A silicon oxynitride film (composition ratio: Si=32%, O=27%, N=24%, H=17%) is formed to a thickness of 140 nm using O as a reactive gas. Then, a second layer of the base insulating film 501b is formed by plasma CVD using SiH₄and N₂A silicon oxynitride film (composition ratio: Si=32%, O=59%, N=7%, H=2%) is formed to a thickness of 100 nm using O as a reactive gas. Note that in this embodiment, the base insulating film has a two-layer laminated structure, but it may of course be a single layer or a multi-layer structure of three or more layers. Also, if the unevenness of the substrate or the diffusion of impurities from the substrate do not pose a problem, it is not necessary to form a base insulating film.

Next, semiconductor layers 502, 503, 504, and 505 are formed on the base insulating film 501b.

The semiconductor layers 502 to 505 are formed by first forming an amorphous semiconductor film by a known means (such as sputtering, LPCVD, or plasma CVD), and then crystallizing the film by a known crystallization process (such as laser crystallization, thermal crystallization, or thermal crystallization using a catalytic element such as nickel) to obtain a crystalline semiconductor film. Then, a first resist mask is formed, and the crystalline semiconductor film is patterned into a desired shape.

In this embodiment, a thermal crystallization method using nickel as a catalytic element is used as the crystallization process of the amorphous semiconductor film. A method of forming a crystalline semiconductor film by the thermal crystallization method using nickel will be described below.

First, an amorphous semiconductor film having a thickness of 50 nm is formed on an insulating base film by using a plasma CVD method. Note that by using the plasma CVD method, the insulating base film and the amorphous semiconductor film can be continuously laminated without being exposed to the air. The amorphous semiconductor film may be formed to a thickness in the range of 25 to 80 nm (preferably 30 to 70 nm). In addition, the material of the amorphous semiconductor film is not limited, but it is preferable to use silicon or a silicon germanium (SiGe) alloy.

Next, a solution containing nickel (aqueous solution or acetic acid solution) is applied onto the amorphous semiconductor film by a coating method such as spin coating or dip coating to form a film containing nickel. Note that the catalyst element is not limited to nickel, and elements such as germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold (Au) may also be used. The film containing nickel is extremely thin, so it may not be possible to observe it as a film.

The method for forming the nickel-containing film is not limited to the coating method, and may be a plasma CVD method, a sputtering method, or a vapor deposition method. Here, a nickel acetate solution containing 1 to 100 ppm (preferably 10 ppm) of nickel by weight is applied to the entire surface of the amorphous semiconductor film by a spin coating method.

Furthermore, before applying the nickel acetate solution to one surface, an oxide film having a thickness of 1 to 5 nm may be formed on the amorphous semiconductor film by performing irradiation with ultraviolet light in an oxygen atmosphere, a thermal oxidation method, or treatment with ozone water or hydrogen peroxide containing hydroxyl radicals, etc. By forming such a thin oxide film, the wettability between the amorphous semiconductor film and the nickel acetate solution can be increased, and the aqueous solution containing nickel can be applied uniformly onto the amorphous semiconductor film.

Next, the amorphous semiconductor film coated with the aqueous solution containing nickel is heat-treated to crystallize it, thereby forming a crystalline semiconductor film. The heat treatment can be performed using a heating furnace, laser irradiation, or irradiation with light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination of these.

Here, crystallization is performed by combining two heat treatments. First, a first heat treatment is performed at 650°C for 6 minutes by thermal crystallization using RTA. Next, a second heat treatment is performed by laser irradiation using an ultraviolet laser with a wavelength of 308 nm. By performing laser irradiation as the second heat treatment, the crystallization rate of the crystalline semiconductor film can be increased.

Next, gettering of nickel (catalytic element) present in the obtained crystalline semiconductor film is performed, which makes it possible to remove nickel present in the crystalline semiconductor film.

First, an amorphous semiconductor film for gettering containing argon is formed on the obtained crystalline semiconductor film by using a plasma CVD method to a thickness of 30 nm. Note that, although argon is added to the amorphous semiconductor film for gettering in this embodiment, it is not limited thereto, and a rare gas element such as helium (He), neon (Ne), krypton (Kr), or xenon (Xe) may be added.

The method for forming the gettering amorphous semiconductor film is not limited to the plasma CVD method, and it is acceptable for the film to be formed to a thickness in the range of 20 to 250 nm using known methods such as the LPCVD method and sputtering method.

Next, a heat treatment is performed at 650°C for 3 minutes using a thermal crystallization method using RTA, and nickel (catalytic element) in the crystalline semiconductor film is gettered into the amorphous semiconductor film for gettering. Note that the heat treatment during gettering may be performed in the range of 400 to 1000°C using a known heating means such as a heating furnace, laser irradiation, furnace annealing method, etc., in addition to the thermal crystallization method using RTA.

Heat treatment may also be performed before forming the amorphous semiconductor film for gettering. By performing heat treatment before forming the amorphous semiconductor film for gettering, distortion of the crystalline semiconductor film can be reduced. As a result, nickel (catalytic element) is easily gettered during gettering.

Next, the gettering amorphous semiconductor film is selectively etched away.₃Dry etching without plasma using fluorine, hydrazine, or tetramethylammonium hydroxide ((CH₃)₄This can be achieved by wet etching using an alkaline solution such as an aqueous solution containing NOH.

Next, in order to control the threshold voltage of the TFT, a small amount of impurity element (boron or phosphorus) may be doped into the crystalline semiconductor film. For example, in the case of fabricating a P-channel TFT, diborane (B₂H₆A trace amount of an impurity element (boron) may be doped into the crystalline semiconductor film by using an ion doping method in which the impurity element is plasma excited without being mass-separated.

Next, the oxide film on the surface of the crystalline semiconductor film is removed with an etchant containing hydrofluoric acid, and the surface of the crystalline semiconductor film is simultaneously washed. Then, a first resist mask is formed on the crystalline semiconductor film, and the first resist mask is used to pattern the crystalline semiconductor film into a desired shape, thereby forming semiconductor layers 502 to 505.

Next, as shown in FIG. 5A, a gate insulating film 506 is formed to cover the semiconductor layers 502 to 505. The gate insulating film 506 is formed to a thickness of 1 to 200 nm by using a plasma CVD method or a sputtering method. Alternatively, the gate insulating film 506 may be formed to a thickness as thin as 10 to 50 nm by forming a single layer or a multilayer structure of an insulating film containing silicon, and then performing a surface nitriding treatment using microwave plasma. In this embodiment, a silicon oxide film is formed to a thickness of 80 nm by using a plasma CVD method and TEOS (Tetra-Ethyl-Ortho-Silicate) as a reactive gas.

Next, the gate electrodes are formed. First, a first conductive layer and a second conductive layer are laminated on the gate insulating film 506. The first conductive layer and the second conductive layer may be formed by using a known method such as a sputtering method or a vapor deposition method. The first conductive layer may be formed to a thickness in the range of 10 to 100 nm, and the second conductive layer may be formed to a thickness in the range of 100 to 600 nm. In this embodiment, a tantalum nitride film having a thickness of 30 nm and a tungsten film having a thickness of 370 nm are laminated in this order on the gate insulating film 506, and patterning is performed according to the procedure shown below to form the gate electrodes and wiring of each TFT.

In this embodiment, the conductive layer is a laminate of a tantalum nitride film and a tungsten film, but the conductive layer is not limited to this and may be a high-melting point metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound mainly composed of a high-melting point metal. The conductive layer is not limited to a two-layer structure, and may be a three-layer structure in which, for example, a 50 nm-thick tungsten film, a 500 nm-thick aluminum-silicon alloy (Al-Si) film, and a 30 nm-thick titanium nitride film are laminated in this order.

The first conductive layer and the second conductive layer are preferably etched using an ICP (Inductively Coupled Plasma) etching method. By using the ICP etching method and appropriately adjusting the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.), the conductive layer can be etched into a desired tapered shape.

Next, second resist masks 507a, 507b, 507c, 507d, 507e, and 507f are formed on the second conductive layer. At this time, the second resist mask 507a is formed above the second conductive layer on which the first gate electrode of the driving TFT will be formed later, and the second resist mask 507b is formed above the second conductive layer on which the second gate electrode of the driving TFT will be formed later. Note that the second resist mask 507a is formed to be larger than the second resist mask 507b.

Next, a first etching process and a second etching process are performed using the second resist masks 507a to 507f. The first etching process is performed under first and second etching conditions, and the second etching process is performed under third and fourth etching conditions. The first to fourth etching conditions may be appropriately selected, but to improve the etching rate, a dry etching device using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) may be used.

In this embodiment, the first etching condition is to apply 700 W of RF (13.56 MHz) power to the coil-shaped electrode at a pressure of 1 Pa, and to use CF₄and Cl₂and O₂and are used with a gas flow ratio of 25:25:10 (sccm), and 150 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), applying a substantially negative self-bias voltage. The electrode area size on the substrate side is 12.5 cm x 12.5 cm, and the coil-type electrode area size (here, a quartz disk with a coil) is a disk with a diameter of 25 cm. Under these first etching conditions, the tungsten film, which is the second conductive layer, is etched to form a tapered edge. Thereafter, the second etching conditions are changed to the second etching conditions without removing the second resist masks 507a to 507g, and CF is used as the etching gas.₄and Cl₂The gas flow ratio is set to 30:30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-shaped electrode at a pressure of 1 Pa to generate plasma and perform etching for about 30 seconds. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF₄and Cl₂Under the second etching conditions, which are a mixture of the above, the tungsten film, which is the second conductive layer, and the tantalum nitride film, which is the first conductive layer, are both etched to the same extent. A cross-sectional view at the stage where the first etching process is completed is shown in Figure 5(B). At this stage, the first conductive layers are designated as 508a, 508b, 508c, 508d, 508e, and 508f, and the second conductive layers are designated as 509a, 509b, 509c, 509d, 509e, and 509f.

Next, a second etching process is performed without removing the second resist masks 507a to 507f. Here, the third etching condition is set to CF₄and Cl₂and , with the gas flow ratio of 30:30 (sccm), 500 W of RF (3.56 MHz) power is applied to the coil-shaped electrode at a pressure of 1 Pa to generate plasma and perform etching for 60 seconds. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. After this, the etching conditions are changed to the fourth without removing the second resist mask, and CF₄and Cl₂and O₂The gas flow ratio is set to 20:20:20 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-shaped electrode at a pressure of 1 Pa to generate plasma and perform etching for about 20 seconds. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.

5(C) shows a cross-sectional view at the stage where the second etching process is completed. At this stage, gate electrodes 512a, 512b, 512c, 512d, 512e, 512f and wiring are formed with the first conductive layers 510a, 510b, 510c, 510d, 510e, 510f as lower layers and the second conductive layers 511a, 511b, 511c, 511d, 511e, 511f as upper layers. Also, terminal electrodes are formed in the terminal parts with the first conductive layers as lower layers and the second conductive layers as upper layers.

Next, after removing the second resist masks 507a to 507f, a first doping process is performed in which impurity elements that impart n-type conductivity (elements belonging to Group 15 of the periodic table, such as phosphorus and arsenic) are doped onto the entire surface of the semiconductor layers 502 to 505 using the gate electrodes 512a to 512f as masks. The first doping process may be performed by ion doping or ion implantation. The conditions for the ion doping process are a dose of 1.5×10¹³atoms/cm²The first doping step is performed at an acceleration voltage of 50 to 100 kV. As an impurity element for imparting n-type conductivity, typically phosphorus (P) or arsenic (As) is used. As shown in FIG. 5(D), in this first doping step, doping is performed through the gate insulating film 506, and a first impurity region 513 (n^--area).

6(A), third resist masks 514a to 514d are formed, and then a second doping process is performed to dope the semiconductor layer with an impurity element that imparts n-type conductivity at a high concentration. The third resist masks 514a to 514d are provided to protect a channel formation region and its surrounding region of the semiconductor layer 502 that forms the driving (p-channel) TFT of the pixel portion, a part of the switching (n-channel) TFT of the pixel portion, and a channel formation region and its surrounding region of the semiconductor layer 505 that forms the p-channel TFT of the driving circuit portion.

The condition of the ion doping method for the second doping process is a dose of 1×10¹³~5×10¹⁵/cm²The second doping step is performed at an acceleration voltage of 60 to 100 kV. The second doping step is performed to form a second impurity region 515 (n⁺and a third impurity region 516 (n^-Since the n-channel TFT in the pixel portion is partially covered with a mask, a first impurity region 513 (n^--In the n-channel TFT of the driving circuit section, a third impurity region 516 and a second impurity region 515 are formed by doping in a self-aligned manner and overlapping with the gate electrode (first conductive layer 510). The boundary between the third impurity region 516 and the second impurity region 515 roughly coincides with the end of the first conductive layer 510.

Next, after removing the third resist masks 514a to 514d, a fourth resist mask 517 is newly formed, and a third doping process is performed to dope the semiconductor layers 502 and 505 with a high concentration of an impurity element (an element belonging to group 13 of the periodic table, such as boron) that imparts p-type conductivity. As shown in Fig. 6(B), the fourth resist mask 517 is provided to protect a channel formation region and its surrounding region of the semiconductor layer 503 that forms an n-channel type (switching) TFT in the pixel section, and a channel formation region and its surrounding region of the semiconductor layer 504 that forms an n-channel type TFT in the driver circuit section.

This third doping step forms fourth impurity regions 518, 519, 520, 521, and 522 (p⁺region), and fifth impurity regions 523a, 523b, 524a, 524b, 525a, 525b (P^-The fourth impurity regions 518 to 522 and the fifth impurity regions 523a, 523b, 524a, 524b, 525a, and 525b are regions doped with phosphorus (P) in the previous first doping step (n^--region), but the concentration of impurity elements that give it p-type is 1.5 to 3 times that of the original, making the conductivity type p-type.

Moreover, the boundary between the fifth impurity region and the fourth impurity region overlapping with the first conductive layer 510a, 510b, or 510f roughly coincides with the end of the first conductive layer. That is, for example, the boundary between the fifth impurity region 523a and the fourth impurity region 518 roughly coincides with the end of the first conductive layer 510a. Furthermore, the boundary between the fifth impurity region and the channel formation region overlapping with the second conductive layer 511a, 511b, or 511f roughly coincides with the end of the second conductive layer. That is, for example, the boundary between the fifth impurity region 523a and the channel formation region 526 roughly coincides with the end of the second conductive layer 511a.

By the third doping process, a source region (fourth impurity region 520), a drain region (fourth impurity region 518), a high concentration impurity region (fourth impurity region 519), two pairs of LDD regions (fifth impurity regions 523a, 523b, 524a, 524b), a first channel formation region 527, and a second channel formation region 526 of a driving TFT having the TFT structure of the present invention are formed.

In this embodiment, the channel length L of the first channel forming region 527 of the driving TFT₁is the channel length L of the second channel forming region 526₂The channel length L₁It is sufficient that the channel length L₁The channel length L may be set to a value in the range of 2 to 8 μm (preferably 4 to 6 μm).₂has a length of 1 μm or more, and L₁The channel width may be formed to be 0.5 μm or more shorter than the channel length L. The channel width may be formed to be in the range of 1 to 50 μm (preferably 5 to 30 μm).₁is 3.5 μm, and the channel length L₂The thickness is 1.5 μm. The channel width is 25 μm.

In this embodiment, the channel length L₁, L₂In L₁&gt;L₂(Preferably 3 x L₁5×L₂, more preferably L₁2×L₂It is necessary to design the size (shape) of the second conductive layers 511a and 511b in advance so that the following relational expression holds true.

Next, the fourth resist mask 517 is removed. Through the above steps, impurity regions having n-type or p-type conductivity are formed in parts of the semiconductor layers 502 to 505 of the TFTs formed in the pixel portion and the driver circuit portion.

Next, an interlayer insulating film is formed. As the interlayer insulating film, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, an organic resin film, or a film containing siloxane can be used, and these insulating films may be formed in a single layer or in a multi-layer structure of two or more layers. Siloxane is a material whose skeletal structure is formed by the bond between silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (e.g., an alkyl group, an aromatic hydrocarbon) is used.

A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. In addition, when forming an inorganic insulating film, a sputtering method, an LPCVD method, a plasma CVD method, or the like may be used, and when forming an organic resin film or a film containing siloxane, a coating method may be used.

In this embodiment, the interlayer insulating film has a three-layer structure of silicon oxynitride films having different composition ratios. The first interlayer insulating film 528a is formed by plasma CVD using SiH₄and N₂A silicon oxynitride film (composition ratio: Si=32%, O=59%, N=7%, H=2%) is formed to a thickness of 80 nm using O as a reactive gas. Then, a second interlayer insulating film 528b is formed by using a plasma CVD method using SiH₄, N.H.₃, and N₂A silicon oxynitride film (composition ratio: Si=32%, O=27%, N=24%, H=17%) is formed to a thickness of 140 nm using O as a reactive gas. Then, a third interlayer insulating film 528c is formed by using a plasma CVD method using SiH₄and N₂A silicon oxynitride film (composition ratios: Si=32%, O=59%, N=7%, H=2%) is formed to a thickness of 670 nm using O as a reactive gas. In this embodiment, the interlayer insulating film has a three-layered structure, but it may have a single layer or two layers, or may have a four-layered or more layered structure. The first interlayer insulating film 528a may have a thickness of 50 nm to 150 nm (preferably 70 to 100 nm), the second interlayer insulating film 528b may have a thickness of 100 to 200 nm (preferably 130 to 160 nm), and the third interlayer insulating film 528c may have a thickness of 600 nm to 800 nm (preferably 650 to 750 nm).

Next, a fifth resist mask is formed on the interlayer insulating film (third interlayer insulating film 528c), and the interlayer insulating films 528a to 528c are selectively etched to form contact holes that reach the semiconductor layers 502 to 505, respectively. Then, the fifth resist mask is removed.

Next, as shown in FIG. 6(C), after laminating a metal film by sputtering, a sixth resist mask is formed, and the metal laminate film is selectively etched to form electrodes 529, 530, 531, 532, 533, 534, 535, and 536 that function as source and drain electrodes of the TFT. In addition, an electrode 560 that will later become a terminal electrode is also formed at the same time in the terminal portion. In this embodiment, the metal film has a three-layer structure of a Ti film, an Al film, and a Ti film. Specifically, a Ti film of 100 nm, an Al film of 700 nm, and a Ti film of 100 nm are formed successively in the same metal sputtering device. Note that the metal film may be a one-layer or two-layer structure, or may be a laminate structure of four or more layers, and may be formed so that the film thickness of the entire laminate film is 500 nm to 2 μm (preferably 800 nm to 1 μm). The electrode 530 formed here becomes the source electrode of the driving TFT, and the electrode 529 becomes the drain electrode of the driving TFT. Thereafter, the sixth resist mask is removed.

In this electrode formation process, a sixth resist mask may be formed using a negative resist. In the negative resist, the portion (electrode pattern) irradiated with light, electrons, or ion energy rays hardens, and the portion not irradiated is dissolved and removed after development. That is, the exposed portion remains as a resist pattern (electrode pattern). Therefore, even if there is a foreign matter or the like in an unintended place (for example, a pixel electrode formation region), defects such as the metal film not being etched and remaining due to the foreign matter or the like can be reduced. In addition, the present invention is not limited to this, and a sixth resist mask may be formed using a positive resist.

Through the above steps, a driving TFT 537 and a switching TFT 538 arranged in the pixel section, and an n-channel TFT 539 and a p-channel TFT 540 arranged in the driving circuit section are fabricated on the same substrate. In this embodiment, the multi-gate structure TFT of the present invention is applied to the driving TFT 537.

In this embodiment, the driving TFT 537 formed in the pixel portion is a p-channel TFT having two gate electrodes and two channel formation regions connected in series, but is not limited to this and may be an n-channel TFT. As described above, the driving TFT 537 is characterized in that the first channel formation region 527 is larger than the second channel formation region 526.

Furthermore, in this embodiment, the driving TFT 537 is a TFT having an LDD region overlapping with the gate electrode, but the present invention is not limited to this, and may be a TFT having no LDD region.

In this embodiment, the switching TFT 538 disposed in the pixel portion is an n-channel TFT having two gate electrodes and two channel forming regions connected in series, but it is not limited to this and may be a single-gate TFT or a multi-gate TFT having three or more gate electrodes. Also, it is not limited to the n-channel type and may be a p-channel type.

Furthermore, in this embodiment, the switching TFT 538 is a TFT having an LDD region that does not overlap with the gate electrode, but the present invention is not limited to this, and a TFT having no LDD region may be used.

The n-channel TFT 539 disposed in the driving circuit section 552 is an n-channel TFT having an LDD region overlapping with the gate electrode, and the p-channel TFT 540 is a p-channel TFT having an LDD region overlapping with the gate electrode. Both are TFTs with a single gate structure. In the driving circuit section 552, the n-channel TFT 539 and the p-channel TFT 540 are complementarily connected to configure a CMOS circuit, which can realize various types of circuits. If necessary, a multi-gate structure TFT can also be used.

Next, a first electrode 541 (anode or cathode of the organic light-emitting element) is formed. At the same time, an electrode 561, which will later become a terminal electrode, is also formed. The first electrode 541 and the electrode 561 are made of a material having a large work function, such as an element selected from nickel (Ni), tungsten (W), chromium (Cr), platinum (Pt), zinc (Zn), tin (Sn), indium (In) or molybdenum (Mo), or an alloy material containing the above element as a main component, such as titanium nitride (TiN) or titanium silicon nitride (TiSi_XN_Y), Tungsten silicide (WSi_X), Tungsten nitride (WN_X), Tungsten Silicide Nitride (WSi_XN_Y) or niobium nitride (NbN), a single layer film or a laminated film thereof may be used with a total thickness in the range of 100 nm to 800 nm.

Specifically, a transparent conductive layer made of a conductive material having a light-transmitting property may be used as the first electrode 541 and the electrode 561, and indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like may be used. Of course, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like may also be used.

The composition ratio of each conductive material having translucency is described below. The composition ratio of indium oxide containing tungsten oxide may be 1.0 wt% tungsten oxide and 99.0 wt% indium oxide. The composition ratio of indium zinc oxide containing tungsten oxide may be 1.0 wt% tungsten oxide, 0.5 wt% zinc oxide, and 98.5 wt% indium oxide. The composition ratio of indium oxide containing titanium oxide may be 1.0 wt% to 5.0 wt% titanium oxide and 99.0 wt% to 95.0 wt% indium oxide. The composition ratio of indium tin oxide (ITO) may be 10.0 wt% tin oxide and 90.0 wt% indium oxide. The composition ratio of indium zinc oxide (IZO) may be 10.7 wt% zinc oxide and 89.3 wt% indium oxide. The composition ratio of indium tin oxide containing titanium oxide may be 5.0 wt% titanium oxide, 10.0 wt% tin oxide, and 85.0 wt% indium oxide. The above composition ratio is an example, and the composition ratio may be set appropriately.

Next, an insulating film (for example, an organic resin film) is formed by a coating method, and the obtained insulating film is patterned to form an insulator 542 (called a bank, partition, barrier, embankment, etc.) that covers the end of the first electrode 541.

Next, a layer 543 containing an organic compound is formed by evaporation, coating, or the like.

The layer 543 containing an organic compound has a laminated structure, and a buffer layer may be used as one layer of the layer 543 containing an organic compound. The buffer layer is a composite material layer containing an organic compound and an inorganic compound, and the inorganic compound exhibits electron accepting properties with respect to the organic compound. The buffer layer is a composite material layer containing an organic compound and an inorganic compound, and the inorganic compound is one or more selected from the group consisting of titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, and rhenium oxide. The buffer layer is a composite material layer containing an organic compound having hole transport properties and an inorganic compound.

For example, it is preferable to provide a stacked layer containing an organic compound (a stacked layer of a buffer layer and an organic compound layer) between the first electrode 541 and the second electrode. The buffer layer is a composite layer containing a metal oxide (molybdenum oxide, tungsten oxide, rhenium oxide, or the like) and an organic compound (a material having a hole transport property (e.g., 4,4'-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl (abbreviation: TPD), 4,4'-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (abbreviation: α-NPD), 4,4'-bis{N-[4-(N,N-di-m-tolylamino)phenyl]-N-phenylamino}biphenyl (abbreviation: DNTPD), or the like)). The layer 543 containing an organic compound is, for example, tris(8-quinolinolato)aluminum (abbreviation: Alq₃) and tris(4-methyl-8-quinolinolato)aluminum (abbreviation: Almq₃), α-NPD, or the like can be used. The layer 543 containing an organic compound may contain a dopant material, for example, N,N'-dimethylquinacridone (abbreviation: DMQd), coumarin 6, rubrene, or the like can be used. The layer 543 containing an organic compound provided between the first electrode and the second electrode may be formed by a deposition method such as a resistance heating method.

By adjusting the thickness of the buffer layer, the distance between the first electrode 541 and the layer containing an organic compound 543 can be controlled, and light-emitting efficiency can be improved. By adjusting the thickness of the buffer layer, an excellent image in which the light-emitting color of each light-emitting element is clearly displayed can be displayed, and a light-emitting device with low power consumption can be realized.

Next, a second electrode 544 (cathode or anode of the organic light emitting element) is formed. As the second electrode 544, an alloy such as MgAg, MgIn, or AlLi, or a transparent conductive layer (ITO, etc.) is used.

Next, a protective layer 545 is formed by evaporation or sputtering using a mask. The protective layer 545 protects the second electrode 544. When light emitted from the light-emitting element is extracted through the protective layer 545, it is preferable to use a transparent material. Note that the protective layer 545 does not have to be provided if it is not necessary.

Next, the sealing substrate 548 is attached with a sealant 546 to seal the light-emitting element. That is, the periphery of the display region of the light-emitting display device is surrounded by the sealant 546, and the light-emitting display device is sealed by the substrate 500 and the sealing substrate 548. In this embodiment mode, the sealant 546 is provided on the terminal portion, but a part of the sealant 546 may be provided over the driver circuit portion, and it is sufficient to provide the sealant 546 so as to surround at least the periphery of the display region.

The region surrounded by the sealant 546 is filled with a filler 547. Alternatively, the region surrounded by the sealant 546 is filled with a dry inert gas.

Finally, FPC 550 is attached to the terminal electrode of terminal portion 553 by a known method using anisotropic conductive layer 549 (FIG. 7). Note that it is preferable to use electrode 561 obtained in the same process as first electrode 541 as the uppermost layer of the terminal electrode, and the terminal electrode is formed on electrode 560 formed at the same time as the source electrode or drain electrode.

8 shows a top view of the pixel section, and the cross section taken along the chain line EF in FIG. 8 corresponds to the cross-sectional structure of the driving TFT 537 of the pixel section 551 in FIG. 7. The cross section taken along the chain line ML in FIG. 8 corresponds to the cross-sectional structure of the switching TFT 538 of the pixel section in FIG. 7. The solid line indicated by 680 in FIG. 8 indicates the periphery of the insulator 542. However, in FIG. 8, only the second conductive layer is shown, and the first conductive layer is not shown. Note that FIGS. 7 and 8 are diagrams showing an example of the light-emitting device of the present invention, and wiring and the like may be changed as appropriate depending on the layout.

Through the above steps, a pixel portion 551, a driver circuit portion 552, and a terminal portion 553 can be formed over the same substrate.

In this embodiment, the driving TFT 537 and the switching TFT 538 in the pixel portion have a multi-gate structure.

In addition, the light-emitting device may have one or both light-emitting display surfaces. When the first electrode 541 and the second electrode 544 are formed of transparent conductive layers, light from the light-emitting element passes through the substrate 500 and the sealing substrate 548 and is extracted to both sides. In this case, it is preferable to use transparent materials for the sealing substrate 548 and the filler 547.

When the second electrode 544 is formed of a metal film and the first electrode 541 is formed of a transparent conductive layer, the structure is such that light from the light-emitting element passes only through the substrate 500 and is extracted to one side, that is, a bottom emission type. In this case, the sealing substrate 548 and the filling material 547 do not need to be made of transparent materials.

When the first electrode 541 is formed of a metal film and the second electrode 544 is formed of a transparent conductive layer, the light of the light-emitting element passes only through the sealing substrate 548 and is extracted to one side, that is, the structure is a top emission type. In this case, the substrate 500 does not need to be made of a transparent material.

In addition, the materials of the first electrode 541 and the second electrode 544 must be selected in consideration of the work function. However, the first electrode 541 and the second electrode 544 can both be an anode or a cathode depending on the pixel configuration. When the polarity of the driving TFT 537 is a p-channel type, it is preferable that the first electrode 541 is an anode and the second electrode 544 is a cathode. When the polarity of the driving TFT 537 is an n-channel type, it is preferable that the first electrode 541 is a cathode and the second electrode 544 is an anode.

FIG. 9 shows an equivalent circuit diagram of the pixel section of this embodiment for full color display. The TFT 938 in FIG. 9 corresponds to the switching TFT 538 in FIG. 7, and the TFT 937 corresponds to the driving TFT 537. The TFT 938 is disposed near the intersection of the gate wiring 901 and the source wiring 902. In the pixel displaying red, a light emitting element 903R that emits red light is connected to the drain region of the TFT 937, and an anode side power line (R) 904R is provided in the source region. The light emitting element 903R is provided with a cathode side power line 900. In the pixel displaying green, a light emitting element 903G that emits green light is connected to the drain region of the TFT 937, and an anode side power line (G) 904G is provided in the source region. In the pixel displaying blue, a light emitting element 903B that emits blue light is connected to the drain region of the driving TFT 937, and an anode side power line (B) 904B is provided in the source region. Different voltages are applied to the different color pixels depending on the EL material.

In addition, in the light-emitting device, the driving method of the screen display is not particularly limited, and for example, a point sequential driving method, a line sequential driving method, a surface sequential driving method, etc. may be used. Typically, the line sequential driving method is used, and a time division gray scale driving method or an area gray scale driving method may be used as appropriate. In addition, the video signal input to the source line of the light-emitting device may be an analog signal or a digital signal, and a driving circuit, etc. may be designed appropriately according to the video signal.

Furthermore, in light-emitting devices with digital video signals, the video signals input to the pixels can be either constant voltage (CV) or constant current (CC). The constant voltage (CV) video signal can be one in which the voltage of the signal applied to the light-emitting element is constant (CVCV) or one in which the current of the signal applied to the light-emitting element is constant (CVCC). The constant current (CC) video signal can be one in which the voltage of the signal applied to the light-emitting element is constant (CCCV) or one in which the current of the signal applied to the light-emitting element is constant (CCCC).

In addition, a protection circuit (such as a protection diode) for preventing electrostatic breakdown may be provided in the light emitting device.

As described above, by applying a p-channel TFT with a multi-gate structure to the TFT 537 for driving the light-emitting device, it is possible to prevent the characteristic failure of the driving TFT 537 (specifically, the characteristic failure in the form of a bump occurring in the rising region of the Id-Vg curve). As a result, it is possible to prevent the "black floating phenomenon" of the light-emitting device. The "black floating phenomenon" refers to a phenomenon in which a current flows through a part that is displayed in black (a part that does not pass current) and emits light. When the "black floating phenomenon" occurs in the light-emitting device, black is not displayed correctly in the display part, which greatly affects the color contrast, gradation expression, and color reproducibility in general, making it difficult to reproduce an accurate image. By using the TFT with a multi-gate structure disclosed in this specification, it is possible to obtain a light-emitting device with improved color contrast, gradation expression, and color reproducibility.

(Embodiment Mode 5) In this embodiment mode, an example of another light-emitting device and a manufacturing method thereof will be described with reference to FIGS.

Since the structure and manufacturing method are the same as those shown in FIG. 6C in the fourth embodiment, the description thereof will be omitted.

In FIG. 10, electrodes 529 to 536 functioning as source electrodes or drain electrodes and an electrode 560 serving as a terminal electrode are formed and are electrically connected to the semiconductor layers 502 to 505 via interlayer insulating films 528a to 528c.

Next, a fourth interlayer insulating film 700 is formed on the third interlayer insulating film 528c and the electrodes 529 to 536 and 560. As the fourth interlayer insulating film 700, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used, and these insulating films may be formed as a single layer or as two or more layers. In addition, as a method for forming the inorganic insulating film, a sputtering method, an LPCVD method, a plasma CVD method, or the like may be used.

In this embodiment, the fourth interlayer insulating film 700 made of an inorganic insulating film is formed to a thickness of 100 nm to 150 nm by using a plasma CVD method. The thickness of the fourth interlayer insulating film 700 may be formed to a range of 50 nm to 500 nm (preferably 100 nm to 300 nm). By providing the fourth interlayer insulating film 700 made of a thin inorganic insulating film as shown in Fig. 10, steps due to wiring and residues generated during wiring formation are covered, and short circuits are prevented, thereby improving the reliability of the light emitting device.

Next, a resist mask is formed on the fourth interlayer insulating film 700 and selectively etched to form contact holes reaching the drain electrode 529 of the driving TFT and the electrode 560. Then, the resist mask is removed.

Next, a first electrode 541 and an electrode 561 which serves as a terminal electrode are formed. The following structure and manufacturing method of the light-emitting device are similar to those in Embodiment 4.

In this embodiment mode, the sealant 746 is provided so that a part of it covers the driver circuit portion. The area surrounded by the sealant 746 may be filled with a filler or may be filled with a dry inert gas. The sealant 746 may be provided so as to surround the periphery of the display area, and may be provided only on the terminal portion.

By forming the fourth interlayer insulating film 700 as in this embodiment, the TFTs, wiring, and the like of the driving circuit section can be prevented from being exposed and can be protected.

(Embodiment Mode 6) In this embodiment mode, an example of another light-emitting device and a manufacturing method thereof will be described with reference to FIG.

Note that the structure and manufacturing method of the second interlayer insulating film are the same as those in the fifth embodiment, and therefore the description thereof will be omitted. Note that in this embodiment, only the pixel portion will be described.

In FIG. 11, electrodes 529 to 532 are formed which are electrically connected to the semiconductor layers 502 and 503 via interlayer insulating films 528a to 528c and function as source electrodes or drain electrodes.

Next, a fourth interlayer insulating film and a fifth interlayer insulating film are formed on the third interlayer insulating film 528c and the electrodes 529 to 532. As the fourth interlayer insulating film 800, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used, and these insulating films may be formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. The fourth interlayer insulating film 800 may be a multi-layer inorganic insulating film.

Next, as the fifth interlayer insulating film 801, a film containing siloxane or a low dielectric constant organic resin film (photosensitive or non-photosensitive organic resin film) can be used, and these films may be formed by a coating method. Siloxane is a material whose skeletal structure is formed by the bond between silicon (Si) and oxygen (O). An organic group (e.g., an alkyl group, an aromatic hydrocarbon) is used as a substituent. A fluoro group may also be used as a substituent. Or, an organic group and a fluoro group may also be used as a substituent.

Further, the fifth interlayer insulating film 801 is provided only in the pixel portion. That is, in the driver circuit portion and the terminal portion, only the fourth interlayer insulating film 800 is provided. Therefore, the structure of the driver circuit portion and the terminal portion is the same as that of FIG. 10 (Embodiment 4).

In this embodiment, the fourth interlayer insulating film 800 is formed by plasma CVD using a silicon oxynitride film with a thickness of 100 nm to 150 nm. The fifth interlayer insulating film 801 is formed by coating using a film containing siloxane with a thickness of 800 nm. The fourth interlayer insulating film 800 may be formed to a thickness of 50 nm to 500 nm (preferably 100 nm to 300 nm). The fifth interlayer insulating film 801 may be formed to a thickness of 500 nm to 1 μm (preferably 700 nm to 900 nm).

Next, a resist mask is formed on the fifth interlayer insulating film 801, and selective etching is performed to form a contact hole reaching the drain electrode 529 of the driving TFT. Then, the resist mask is removed.

Next, a first electrode 541 is formed. The following structure and manufacturing method of the light-emitting device are similar to those in Embodiments 4 and 5.

As in this embodiment, by forming the fifth interlayer insulating film 801 made of a film containing siloxane or an organic resin film, the steps due to the TFT can be flattened. Since the layer containing an organic compound 543 formed later is very thin, the presence of the steps may cause light emission defects. Therefore, it is very effective to flatten the surface before forming the first electrode 541 so that the layer containing an organic compound 543 can be formed on as flat a surface as possible.

Seventh Embodiment Here, an example in which an FPC and a driving IC for driving are mounted on a light-emitting display panel will be described with reference to FIG.

The diagram shown in Fig. 12(a) shows an example of a top view of a light-emitting device in which an FPC 1009 is attached to four terminal portions 1008. A pixel portion 1002 including a light-emitting element and a TFT, a gate side driver circuit 1003 including a TFT, and a first driver circuit 1001 including a TFT are formed on a substrate 1010. The active layer of the TFT is made of a semiconductor film having a crystalline structure, and these circuits are formed on the same substrate. Therefore, an EL display panel that realizes a system-on-panel configuration can be manufactured.

The substrate 1010 is covered with a protective film except for the contact portion, and a base layer containing a substance having a photocatalytic function is provided on the protective film.

The connection regions 1007 are provided in two places on either side of the pixel section to bring the second electrode (cathode) of the light-emitting element into contact with the wiring in the lower layer. The first electrode (anode) of the light-emitting element is electrically connected to the TFT provided in the pixel section.

The sealing substrate 1004 is fixed to the substrate 1010 by a sealant 1005 that surrounds the pixel portion and the driver circuit, and a filler material that is surrounded by the sealant 1005. A filler material that contains a transparent desiccant may be used. The desiccant may be placed in a region that does not overlap with the pixel portion.

In this embodiment, the sealant 1005 is provided so as to overlap a part of the gate driver circuit 1003 including the TFT, but it may be provided so as to surround the periphery of the display area. In other words, it may be provided so as not to overlap the gate driver circuit 1003.

In addition, the structure shown in FIG. 12(a) is a suitable example for a light-emitting device of a relatively large size (e.g., 4.3 inches diagonal), while FIG. 12(b) is an example that employs a COG method suitable for a small size light-emitting device with a narrow frame (e.g., 1.5 inches diagonal).

In FIG. 12(b), a driving IC 1101 is mounted on a substrate 1110, and an FPC 1109 is mounted on a terminal section 1108 disposed at the tip of the driving IC. In order to improve productivity, it is preferable to fabricate a plurality of driving ICs 1101 on a rectangular substrate with a side of 300 mm to 1000 mm or more. That is, a plurality of circuit patterns each having a driving circuit section and an input/output terminal as one unit are formed on the substrate, and then the substrate is divided to extract the driving ICs individually. The length of the long side of the driving IC may be formed into a rectangular shape with a long side of 15 to 80 mm and a short side of 1 to 6 mm, taking into consideration the length of one side of the pixel section and the pixel pitch, or may be formed to be the length of one side of the pixel region, or the length of one side of the pixel section plus one side of each driving circuit.

The advantage of the driver IC over the IC chip in terms of external dimensions is the length of the long side. If a driver IC with a long side of 15 to 80 mm is used, the number required to mount it corresponding to the pixel part is smaller than when an IC chip is used, and the manufacturing yield can be improved. In addition, if the driver IC is formed on a glass substrate, it is not limited to the shape of the substrate used as the base, so there is no loss of productivity. This is a major advantage compared to the case of extracting IC chips from a circular silicon wafer.

Alternatively, the TAB method may be used, in which case multiple tapes are attached and the driver IC is mounted on the tapes. As with the COG method, a single driver IC may be mounted on a single tape, in which case a metal piece or the like for fixing the driver IC may be attached together for strength reasons.

A connection region 1107 between the pixel section 1102 and the driving IC 1101 is provided to bring the second electrode of the light-emitting element into contact with the wiring in the lower layer. The first electrode of the light-emitting element is electrically connected to the TFT provided in the pixel section.

In addition, the sealing substrate 1104 is fixed to the substrate 1110 by a sealant 1105 surrounding the pixel portion 1102 and a filling material surrounded by the sealant.

Furthermore, when an amorphous semiconductor film is used as the active layer of the TFT in the pixel portion, it is difficult to form the driving circuit on the same substrate, so the configuration shown in FIG. 12(b) is used even for a large size.

Here, the connection region 1007 will be described with reference to Fig. 13. Since the parts other than the connection region 1007 are the same as those in the fourth, fifth or sixth embodiment, the description thereof will be omitted.

In FIG. 13, in the connection region 1007, a conductive layer 1301 is formed of the same material as the gate electrodes 512a to 512d.

Next, after interlayer insulating films 528a to 528c are formed, wiring 1302 is formed from the same material as electrodes 529 to 532 that function as source electrodes or drain electrodes.

Next, a fourth interlayer insulating film 1303 is formed over the third interlayer insulating film 528c and the wiring 1302. As the fourth interlayer insulating film 1303, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used, and these insulating films may be formed as a single layer or as two or more layers. In addition, a sputtering method, an LPCVD method, a plasma CVD method, or the like may be used as a method for forming the inorganic insulating film. Furthermore, a film containing siloxane or an organic resin film with a low dielectric constant may be formed on the inorganic insulating film by a coating method to form a laminated structure. Note that the fourth interlayer insulating film 1303 does not have to be provided if it is not necessary.

Next, a resist mask is formed on the fourth interlayer insulating film 1303 and selectively etched to form a contact hole reaching the wiring 1302. Then, the resist mask is removed.

Next, after forming a first electrode in the pixel portion, an insulating film (for example, an organic resin film) is formed by a coating method, and the obtained insulating film is patterned to form an insulator 1304 (also called a bank, partition wall, barrier, embankment, etc.) that covers the end of the first electrode 541. At this time, the insulating film is patterned so that the wiring 1302 is exposed.

Next, a layer 543 containing an organic compound is formed in the pixel portion, and then a second electrode 1305 is formed. At this time, the wiring 1302 and the second electrode 1305 are electrically connected (contacted) in the connection region 1007. The second electrode 1305 may be made of an alloy such as MgAg, MgIn, or AlLi, or a transparent conductive layer (such as ITO).

Next, a protective layer 1306 is formed over the second electrode 1305. When light emitted from the light-emitting element is extracted through the protective layer 1306, it is preferable to use a transparent material. Note that the protective layer 1306 does not have to be provided if not necessary. The structure and manufacturing method of the light-emitting device described below are the same as those in Embodiment 4, Embodiment 5, or Embodiment 6.

It should be noted that the connection area 1107 is similar to the connection area 1007 .

Although an example of an active matrix type light emitting device is shown here as the display device, it goes without saying that the present invention can also be applied to an active matrix type liquid crystal display device. In an active matrix type liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. In detail, a voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, whereby optical modulation of a liquid crystal layer arranged between a pixel electrode provided on an element substrate and a counter electrode provided on a counter substrate is performed, and this optical modulation is recognized by an observer as a display pattern. The counter substrate and the element substrate are arranged at equal intervals and filled with liquid crystal material. The liquid crystal material may be dropped under reduced pressure with a seal material as a closed pattern so as not to trap air bubbles, and then both substrates are bonded together, or a dip type (pumping type) may be used in which a seal pattern with an opening is provided, and the liquid crystal is injected using capillary action after bonding the TFT substrate.

The present invention can also be applied to a liquid crystal display device using a field sequential driving method in which an optical shutter is used without using a color filter and backlight light sources of three colors, RGB, are blinked on and off at high speed.

As described above, various electronic devices can be completed by using any one of the manufacturing methods or structures described in Embodiments 1 to 4.

(Embodiment 8) Examples of the semiconductor device and electronic device of the present invention include cameras such as video cameras and digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, audio components, etc.), notebook personal computers, game devices, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), image playback devices equipped with recording media (specifically, devices equipped with a display capable of playing recording media such as Digital Versatile Discs (DVDs) and displaying the images), etc. Specific examples of such electronic devices are shown in Figs. 14 and 15.

Fig. 14(a) shows a digital camera, which includes a main body 2101, a display unit 2102, an imaging unit, operation keys 2104, an antenna 2105, and a shutter 2106. Note that Fig. 14(a) is a view from the display unit 2102 side, and does not show the imaging unit.

Furthermore, the digital camera of the present invention may cause the display unit 2102 to function as a display medium such as a television receiver by receiving signals such as video signals and audio signals via the antenna 2105. When the display unit functions as a display medium, a speaker, an operation switch, and the like may be provided as appropriate. The present invention makes it possible to realize a highly reliable digital camera having a high-definition display unit.

14(b) shows a notebook personal computer, which includes a main body 2201, a housing 2202, a display unit 2203, a keyboard 2204, an external connection port 2205, and a pointing mouse 2206. According to the present invention, a notebook personal computer having a high-definition display unit and high reliability can be realized.

Fig. 14(c) shows a portable image reproducing device (specifically, a DVD reproducing device) equipped with a recording medium, and includes a main body 2301, a housing 2302, a display unit A 2303, a display unit B 2304, a recording medium (DVD, etc.) reading unit 2305, operation keys 2306, a speaker unit 2307, etc. The display unit A 2303 mainly displays image information, and the display unit B 2304 mainly displays text information. Note that image reproducing devices equipped with a recording medium also include home game machines. According to the present invention, it is possible to realize an image reproducing device having a high-definition display unit and high reliability.

14(d) shows a display device, which includes a housing 2401, a support 2402, a display portion 2403, a speaker 2404, a video input terminal 2405, and the like. This display device is manufactured by using a thin-film TFT formed by the manufacturing method shown in the above-mentioned embodiment mode for the display portion 2403 and a driver circuit. Note that the display device includes a liquid crystal display device, a light-emitting device, and the like, and specifically includes all display devices for displaying information such as those for computers, television reception, and advertisement display. The present invention can realize a display device having a high-definition display portion and high reliability, particularly a large display device having a large screen of 22 inches to 50 inches.

15, a main body (a) 3001 equipped with operation switches 3004, a microphone 3005, etc., and a main body (b) 3002 equipped with a display panel (a) 3008, a display panel (b) 3009, a speaker 3006, etc. are connected openably and closably by a hinge 3010. The display panel (a) 3008 and the display panel (b) 3009 are housed in a housing 3003 of the main body (b) 3002 together with a circuit board 3007. The pixel portions of the display panel (a) 3008 and the display panel (b) 3009 are arranged so as to be visible from an opening window formed in the housing 3003.

The specifications of the display panel (a) 3008 and the display panel (b) 3009, such as the number of pixels, can be set appropriately according to the functions of the mobile phone 3000. For example, the display panel (a) 3008 can be used as a main screen, and the display panel (b) 3009 can be used as a sub-screen.

Moreover, by receiving signals such as video signals and audio signals via the antenna 3011, the display panel (a) 3008 may function as a display medium such as a television receiver.

According to the present invention, a portable information terminal having a high-definition display portion and high reliability can be realized.

The mobile phone according to this embodiment can be transformed into various forms depending on its functions and applications. For example, an imaging element may be incorporated in the hinge 3010 to make it a mobile phone with a camera. The above-mentioned effects can also be achieved by a configuration in which the operation switches 3004, the display panel (a) 3008, and the display panel (b) 3009 are housed in a single housing. The same effects can also be achieved by applying the configuration of this embodiment to an information display terminal equipped with multiple display units.

As described above, by implementing the present invention, that is, by using any one of the manufacturing methods or structures in Embodiment Modes 1 to 5, various electronic devices can be completed.

<p>In this embodiment, the characteristics of a TFT (hereinafter referred to as Type-A) having a multi-gate structure (having at least two or more gate electrodes and a semiconductor layer including at least two or more channel formation regions connected in series and located between a source region and a drain region) of the present invention and in which the channel length of the first channel formation region (channel formation region adjacent to the source region) is longer than the channel length of the second channel formation region (channel formation region adjacent to the drain region), a TFT (hereinafter referred to as Type-B) having a multi-gate structure and in which the channel lengths of the first channel formation region and the second channel formation region are equal, and a TFT (hereinafter referred to as Type-C) having a multi-gate structure and in which the channel length of the first channel formation region is shorter than the channel length of the second channel formation region were compared.</p><p>For the above-mentioned Type-A, Type-B, and Type-C p-channel TFTs with multi-gate structures, the parameters were set as follows, and the gate voltage dependence of the drain current was measured.</p><p>The Type-A TFT is a p-channel TFT with a multi-gate structure having two gate electrodes and two channel formation regions connected in series. The channel length L of the first channel formation region of the Type-A multi-gate structure TFT is₁is 3.2 μm, and the channel length L₂was set to 1.5 μm.</p><p>The Type-B TFT is a p-channel TFT with a multi-gate structure having two gate electrodes and two channel formation regions connected in series. The channel length L of the first channel formation region of the Type-B multi-gate structure TFT is₁is 2.4 μm, and the channel length L₂The channel length of each of the two channel formation regions was set to be equal to 2.4 μm.</p><p>The Type-C TFT is a p-channel TFT with a multi-gate structure having two gate electrodes and two channel formation regions connected in series. The channel length L of the first channel formation region of the Type-C multi-gate structure TFT is₁is 1.5 μm, and the channel length L₂was set to 3.2 μm.</p><p>The gate insulating film, channel formation region, and drain voltage were set as follows, and were used as common parameters for the above Type-A to Type-C TFTs. The gate insulating film was a silicon oxide film with a thickness of 110 nm, the first channel formation region and the second channel formation region were made of silicon films with a channel width (W) of 23.7 μm, and the drain voltage (Vd) was set to 12 V.</p><p>Figure 16 shows the results of measuring the gate voltage dependence of drain current for TFTs with multi-gate structures of Type-A, Type-B, and Type-C. Hereinafter, the obtained drain current (Id)-gate voltage (Vg) characteristics are referred to as Id-Vg curves.</p><p>16, the Type-B and Type-C TFTs had a hump-like characteristic defect in the rising region of the Id-Vg curve. On the other hand, the Type-A multi-gate structure TFT of the present invention did not have a hump-like characteristic defect in the rising region of the Id-Vg curve, compared to the Type-B and Type-C multi-gate structure TFTs.</p><p>As a result of extensive research, the present inventors have found the reason why the hump-like characteristic defect occurs in the rising region of the Id-Vg curve. Furthermore, they have found that the Type-A multi-gate structure TFT of the present invention prevents the TFT characteristic defect, specifically, the hump-like characteristic defect that occurs in the rising region of the Id-Vg curve. Hereinafter, the reason why the hump-like characteristic defect occurs will be explained using the Type-B multi-gate structure TFT.</p><p>As described above, the Type-B multi-gate structure TFT is a TFT in which the channel length of the first channel formation region is equal to the channel length of the second channel formation region. In the following description, the TFT portion having the first channel formation region of the multi-gate structure TFT is referred to as the first TFT 201, and the TFT portion having the second channel formation region is referred to as the second TFT 202. The potential of the impurity region portion that is the drain region side in the first TFT 201 and the source region side in the second TFT 202 is referred to as the intermediate potential (VM).</p><p>17(a) shows the case where a gate voltage (Vg) of +2 V is applied. In this case, no current flows through either TFT. However, an off current flows through the second TFT 202.</p><p>FIG. 17(b) shows the case where Vg=+1V is applied. In this case, current starts to flow through the first TFT due to the short channel effect. As a result, the midpoint potential (VM) changes, and the potential difference between the source region and the drain region of the second TFT 202 (absolute value of Vd-VM, hereafter represented as |Vd-VM|) increases. Also, an off-current flows through the second TFT, just like in (a).</p><p>FIG. 17(c) shows the case where Vg=+0.75V is applied. In this case, as in (b), a current flows through the first TFT 201 due to the short channel effect. Also, Vgs (=Vg-VM) of the second TFT 202 becomes large, and the voltage (|</p><p>When Vd-V M|) increases, the off-current flowing through the second TFT 202 increases.</p><p>In this case, if the relationship between the current flowing through the first TFT and the off current flowing through the second TFT 202 due to the short channel effect meets a certain condition, the drain current flows where it should not flow, resulting in a hump-shaped defect in the rising region of the Id-Vg curve.</p><p>17D shows the case where Vg=+0.5 V is applied. In this case, a current flows through the second TFT 202 due to the short channel effect, similar to the first TFT 201.</p><p>17(e) shows the case where Vg=0 V. In this case, a current flows in the linear region of the drain voltage (Vd)-drain current (Id) characteristics in the first TFT 201. Also, a current flows in the saturation region of the Vd-Id characteristics in the second TFT.</p><p>From the above, it was found that the short channel of the first TFT 201 and the second TFT 202 that constitute the multi-gate structure TFT progresses, and the short channel effect of the first TFT 201 becomes stronger, and the current that starts to flow due to the short channel effect becomes balanced with the off current flowing in the second TFT 202, causing the drain current to flow where it should not flow. As a result, it was found that a hump-shaped defect occurs in the rising region of the Id-Vg curve.</p><p>In the Type-A multi-gate structure TFT, the channel length of the first channel formation region is made longer than that of the second channel formation region, which makes it possible to suppress current flow in the source side TFT due to the short channel effect. As a result, it is possible to suppress the phenomenon seen in (b) and (c) where drain current flows in a place where it should not flow due to the relationship with the off current flowing in the second TFT 202. Therefore, it is possible to prevent defects in the rising region of the Id-Vg curve and prevent TFT characteristic defects.</p>

<p>FIG. 10 shows an example in which a fourth interlayer insulating film 700 made of a thin inorganic insulating film is provided so as to cover an end face of electrode 529, and part of the upper surface of electrode 529 is connected to first electrode 541, but this is not particularly limited, and a connection structure in which the end face and first electrode 541 are in contact with each other may also be used.</p><p>In order to confirm the electrical connection between the electrode 529 and the first electrode 541, a TEG having a substantially identical laminated structure was fabricated, the electrical connection was confirmed by electrical measurement, and a cross-sectional STEM photograph of the periphery of the connection was taken. Figure 18(A) shows a schematic diagram of the cross section, and Figure 18(B) shows the cross-sectional STEM photograph.</p><p>As shown in FIG. 18(A), an opening is formed in the first interlayer insulating film 301, and a wiring 302 is formed thereon. Although not shown in the schematic diagram, the wiring 302 is in contact with the semiconductor layer through the opening in the first interlayer insulating film 301. Note that the wiring 302 is shown as a single layer in FIG. 18(A) for simplification, but has a three-layer structure of a titanium film, an aluminum film, and a titanium film as shown in FIG. 18(B). A second interlayer insulating film 303 with a thickness of 150 nm is formed so as to cover the end face of the wiring 302, and an opening is also formed in the second interlayer insulating film 303 so as to overlap with the opening in the first interlayer insulating film 301. A first electrode 304 is formed through the opening in the second interlayer insulating film 303, and an organic resin film 305 serving as a partition is formed so as to cover the first electrode and the second interlayer insulating film. Since the thickness of the organic resin film 305 formed by the spin coating method is set to 1 μm, the organic resin film is thinner than 1 μm above the end face of the wiring. The organic resin film 305 may be an insulating film formed by a coating method such as spin coating, and may be a film containing siloxane.</p><p>FIG. 19(A) shows an example of a TEG having a different connection structure from that shown in FIG. 18(A).</p><p>FIG. 19(A) shows a schematic diagram of the cross section, and FIG. 19(B) shows a cross-sectional STEM photograph thereof. Note that the same parts as in FIG. 18(A) are described using the same reference numerals. The structure shown in FIG. 19(A) is a structure that suppresses thinning of the film thickness above the end face of the wiring. Since the second interlayer insulating film is not formed in the part where the first electrode 304 and the wiring 302 contact each other, the film thickness of the organic resin film can be made thicker than in the structure shown in FIG. 18(A). Therefore, in the structure of FIG. 19(A), there is a part where the first interlayer insulating film and the first electrode contact each other.</p><p>Moreover, Fig. 20(A) shows an example of a TEG having a different connection structure from those shown in Figs. 18(A) and 19(A). Fig. 20(A) shows a schematic cross-sectional view, and Fig. 20(B) shows a cross-sectional STEM photograph. Note that the same parts as those in Fig. 18(A) are described using the same reference numerals. The structure in Fig. 20(A) is an example in which the end face of the first electrode 304 is located inside the opening of the second interlayer insulating film.</p><p>Therefore, in the structure of Fig. 20(A), the interface between the wiring and the first electrode is exposed during etching to form the first electrode. In this structure, etching tends to proceed from the interface, i.e., the interface between the titanium film and the ITSO film, so that the end of the first electrode has an inverse tapered shape can be seen in the cross-sectional photograph of Fig. 20(B). That is, when the structure of Fig. 20(A) is fabricated, the first electrode is likely to be etched excessively, so that the first electrode overlapping with the wiring disappears, and there is a possibility that electrical connection becomes difficult. For these reasons, the connection structure of Fig. 18(A) is more preferable than the connection structure of Fig. 20(A) in terms of the manufacturing process.</p><p>However, since electrical connection was confirmed in both the structure of FIG. 19(A) and the structure of FIG. 20(A) as in the structure of FIG. 18(A), it can be said from these experimental results that either structure is acceptable.</p>

Ten substrate

11 First insulating film

12 Semiconductor Layer

13 Second insulating film

14 Gate electrode

15 Gate electrode

16 Third insulating film

17 Fourth insulating film

18 Source electrode

19 Drain electrode

twenty one Channel formation region

twenty two Channel formation region

twenty three High concentration impurity region

twenty four Source Region

twenty five Drain Region

31a Conductive layer

31b Conductive layer

32a Conductive layer

32b Conductive layer

100 substrate

101 First insulating film

102 Semiconductor Layer

103 Second insulating film

104 First Conductive Layer

105 Second Conductive Layer

106a Second resist mask

106b Second resist mask

107a first gate electrode

107b second gate electrode

108 Source Region

109 Drain Region

110 High concentration impurity region

111 First channel forming region

112 Second channel formation region

113 Third insulating film

114 Fourth insulating film

115 Source electrode

116 Drain electrode

201 First TFT

202 Second TFT

301 First interlayer insulating film

302 wiring

303 Second interlayer insulating film

304 First electrode

305 Organic Resin Film

401 First channel forming region

402 Second channel formation region

403 High concentration impurity region

404 Source Region

405 Drain Region

406a First LDD region

406b First LDD region

407a Second LDD Region

407b Second LDD region

411 First channel forming region

412 Second channel formation region

413 High concentration impurity region

414 Source Region

415 Drain Region

416a First LDD region

416b First LDD region

417a Second LDD region

417b Second LDD region

500 substrate

501a Undercoat insulating film

501b Undercoat insulating film

502, 503, 504, 505 Semiconductor layer

506 Gate insulating film

507a, 507b, 507c, 507d, 507e, 507f Second resist mask

508a, 508b, 508c, 508d, 508e, 508f First conductive layer

509a, 509b, 509c, 509d, 509e, 509f Second conductive layer

510a, 510b, 510c, 510d, 510e, 510f First conductive layer

511a, 511b, 511c, 511d, 511e, 511f second conductive layer

512a, 512b, 512c, 512d, 512e, 512f gate electrodes

513 First impurity region

514a, 514b, 514c, 514d Third resist mask

515 Second impurity region

516 Third impurity region

517 Fourth resist mask

518, 519, 520, 521, 522 Fourth impurity region

523a, 523b, 524a, 524b, 525a, 525b Fifth impurity region

526 Second channel formation region

527 First channel forming region

528a First interlayer insulating film

528b Second interlayer insulating film

528c Third interlayer insulating film

529, 530, 531, 532, 533, 534, 535, 536 electrode

537 Driving TFT

538 Switching TFT

539 n-channel TFT

540 p-channel TFT

541 First electrode

542 Insulator

543 Layer containing organic compound

544 Second electrode

545 Protective Layer

546 Sealing materials

547 Filler

548 Encapsulating Substrate

549 Anisotropic Conductive Layer

550 FPC

551 Pixel section

552 Drive Circuit Section

553 Terminal

560 electrode

561 electrode

680 Insulation edge

700 Fourth interlayer insulating film

746 Sealing materials

800 Fourth interlayer insulating film

801 Fifth interlayer insulating film

900 Cathode side power line

901 Gate wiring

902 Source wiring

903R Red light emitting element

904R Anode side power line (R)

903G Green light emitting element

904G Anode side power wire (G)

903B Blue light emitting element

904B Anode side power wire (B)

937 TFT

938 TFT

1001 First Drive Circuit

1002 Pixel section

1003 Gate side drive circuit

1004 Encapsulating Substrate

1005 Sealing materials

1007 Connection Area

1008 Terminal

1009 FPC

1010 substrate

1101 Driver IC

1102 Pixel section

1104 Encapsulating Substrate

1105 Sealing materials

1107 Connection Area

1108 Terminal

1109 FPC

1110 substrate

1301 Conductive layer

1302 wiring

1303 Fourth interlayer insulating film

1304 Insulator

1305 Second electrode

1306 Protective Layer

2101 Main unit

2102 Display

2104 Operation key

2105 antenna

2106 shutter

2201 Main unit

2202 Chassis

2203 Display

2204 keyboard

2205 External connection port

2206 Pointing Mouse

2301 Main unit

2302 Chassis

2303 Display A

2304 Display B

2305 Recording medium reading section

2306 Operation key

2307 Speaker section

2401 Chassis

2402 Support stand

2403 Display

2404 Speaker

2405 Video input terminal

3000 Mobile phone

3001 Body (a)

3002 Body (b)

3003 Chassis

3004 Operation Switches

3005 microphone

3006 Speaker

3007 Circuit Board

3008 Display panel (a)

3009 Display panel (b)

3010 hinge

3011 antenna