Liquid crystal display device

The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. In particular, one embodiment of the present invention relates to a display device and a manufacturing method thereof.

In recent years, liquid crystals have been used in a variety of devices, and liquid crystal display devices (liquid crystal displays), which are characterized by their thinness and light weight, are used as displays in a wide range of fields.

There are two methods for applying an electric field to liquid crystal molecules in a liquid crystal display device: a vertical electric field method and a horizontal electric field method. A horizontal electric field method liquid crystal display panel includes an IPS (In-Plane Switching) mode in which a pixel electrode and a common electrode are provided on the same insulating film, and an FFS (Fringe Field Switching) mode in which a pixel electrode and a common electrode overlap with each other via an insulating film.

An FFS mode liquid crystal display device has a slit-shaped opening in a pixel electrode, and controls the alignment of the liquid crystal molecules by applying an electric field generated between the pixel electrode and a common electrode at the opening to the liquid crystal molecules.

FFS mode liquid crystal display devices have the advantage of having a high aperture ratio, a wide viewing angle, and improved image contrast, and have come to be widely used in recent years (see Patent Document 1).

<p><patcit num="1"><text>JP 2000-89255 A</text></patcit></p>

<p>One embodiment of the present invention provides a display device in which wiring delay due to parasitic capacitance is reduced. Another embodiment of the present invention provides a display device with little light leakage and excellent contrast. Another embodiment of the present invention provides a display device having a high aperture ratio and a capacitor capable of increasing charge capacitance. Another embodiment of the present invention provides a display device with reduced power consumption. Another embodiment of the present invention provides a display device including a transistor with excellent electrical characteristics. Another embodiment of the present invention provides a novel display device. Another embodiment of the present invention provides a method for manufacturing a display device that has a high aperture ratio and a wide viewing angle with a small number of steps. Another embodiment of the present invention provides a method for manufacturing a novel display device.</p><p>Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc.</p>

<p>One embodiment of the present invention is a display device that includes a transistor on an insulating surface, a pixel electrode connected to the transistor, a signal line connected to the transistor, a scan line connected to the transistor and intersecting the signal line, and a common electrode provided over the pixel electrode and the signal line with an insulating film interposed therebetween, wherein the common electrode has a striped region extending in a direction intersecting the signal line.</p><p>The transistor has a gate electrode electrically connected to a scan line, a semiconductor film overlapping with the gate electrode, a gate insulating film between the gate electrode and the semiconductor film, a first conductive film electrically connected to the signal line and the semiconductor film, and a second conductive film electrically connected to the pixel electrode and the semiconductor film, and the second conductive film has a region parallel to the striped regions of the scan line and the common electrode.</p><p>One embodiment of the present invention is a display device having a signal line, a scan line, a transistor, a pixel electrode, a common electrode, and a capacitor on an insulating surface. The transistor has a gate electrode electrically connected to the scan line, a semiconductor film overlapping with the gate electrode, a gate insulating film between the gate electrode and the semiconductor film, a first conductive film electrically connected to the signal line and the semiconductor film, and a second conductive film electrically connected to the pixel electrode and the semiconductor film. The capacitor has a pixel electrode, a common electrode, and a nitride insulating film provided between the pixel electrode and the common electrode. The common electrode has a striped region extending in a direction intersecting the signal line.</p><p>The second conductive film has regions parallel to the striped regions of the scanning lines and the common electrode.</p><p>Furthermore, each of the striped regions of the common electrode may extend across a plurality of pixel electrodes arranged in parallel to the scanning lines.</p><p>Moreover, the angle at which the common electrode and the signal line intersect is preferably not less than 70° and not more than 110°.</p><p>The pixel electrodes are arranged in a matrix, the common electrode has a region that intersects with the scanning lines and is connected to the striped region, and the semiconductor film and the pixel electrodes are in contact with a gate insulating film.</p><p>The semiconductor film and the pixel electrode have In-Ga oxide, In-Zn oxide, or In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd).</p><p>Moreover, the semiconductor film and the pixel electrode have a multi-layer structure including a first film and a second film, and the first film has a different atomic ratio of metal elements from that of the second film.</p>

<p>According to one embodiment of the present invention, a display device in which wiring delay due to parasitic capacitance is reduced can be provided. According to one embodiment of the present invention, a display device in which light leakage is small and contrast is excellent can be provided. According to one embodiment of the present invention, a display device having a high aperture ratio and a capacitor capable of increasing charge capacitance can be provided. According to one embodiment of the present invention, a display device in which power consumption is reduced can be provided. According to one embodiment of the present invention, a display device having a transistor with excellent electrical characteristics can be provided. According to one embodiment of the present invention, a display device in which a high aperture ratio and a wide viewing angle can be obtained can be manufactured with a small number of steps.</p>

<figref num="1">1A and 1B are a cross-sectional view and a top view illustrating one embodiment of a display device.</figref><figref num="2">FIG. 1 is a top view illustrating one embodiment of a display device.</figref><figref num="3">1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of a display device.</figref><figref num="4">FIG. 1 is a top view illustrating one embodiment of a display device.</figref><figref num="5">FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor.</figref><figref num="6">1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor.</figref><figref num="7">1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor.</figref><figref num="8">1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor.</figref><figref num="9">1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a display device.</figref><figref num="10">FIG. 1 is a top view illustrating one embodiment of a display device.</figref><figref num="11">FIG. 1 is a top view illustrating one embodiment of a display device.</figref><figref num="12">FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor.</figref><figref num="13">1A to 1C are cross-sectional views illustrating one mode of a method for manufacturing a transistor.</figref><figref num="14">FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor.</figref><figref num="15">FIG. 2 is a diagram illustrating a display module.</figref><figref num="16">1A and 1B are diagrams illustrating external views of an electronic device according to an embodiment.</figref><figref num="17">1A and 1B are top views of Sample 1 and Sample 2 and graphs showing transmittance distributions.</figref><figref num="18">1A and 1B are top views and graphs showing transmittance distributions of Samples 3 and 4.</figref><figref num="19">FIG. 1 is a top view illustrating one embodiment of a display device.</figref><figref num="20">FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor.</figref><figref num="21">FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor.</figref><figref num="22">FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor.</figref><figref num="23">FIG. 1 is a cross-sectional view illustrating one embodiment of a transistor.</figref><figref num="24">FIG. 1 is a top view illustrating one embodiment of a display device.</figref><figref num="25">FIG. 1 is a top view illustrating one embodiment of a display device.</figref><figref num="26">FIG. 13 is a graph showing the temperature dependence of electrical conductivity.</figref>

Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments and examples shown below. In addition, in the embodiments and examples described below, the same parts or parts having similar functions are designated by the same reference numerals or the same hatch patterns in different drawings, and repeated description thereof will be omitted.

In addition, in each figure described in this specification, the size of each component, the thickness of a film, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

In addition, the terms "first," "second," "third," etc., used in this specification are used to avoid confusion of components and are not intended to limit the number. Therefore, for example, "first" can be appropriately replaced with "second" or "third" to explain.

In addition, the functions of "source" and "drain" may be interchangeable when the direction of current flow changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

Furthermore, voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point. However, generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is simply called potential or voltage, and potential and voltage are often used as synonyms. For this reason, in this specification, potential may be read as voltage, and voltage may be read as potential, unless otherwise specified.

In this specification, "electrically connected" includes a case where the connection is made via "something having some electrical action". Here, the "something having some electrical action" is not particularly limited as long as it allows the transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

Embodiment 1 In this embodiment, a display device which is one embodiment of the present invention will be described with reference to the drawings.

Fig. 1(A) is a cross-sectional view of an FFS mode liquid crystal display device, and Fig. 1(B) is a top view of one pixel 10 of a display unit included in the liquid crystal display device. Fig. 1(A) corresponds to a cross-sectional view of dashed line AB in Fig. 1(B). In Fig. 1(B), substrate 1, insulating film 3, insulating film 8, insulating film 60, substrate 61, light-shielding film 62, colored film 63, insulating film 64, insulating film 65, and liquid crystal layer 66 are omitted.

As shown in FIG. 1, the FFS mode liquid crystal display device is an active matrix type liquid crystal display device, and includes a transistor 102 and a pixel electrode 7 for each pixel 10 provided in a display portion.

As shown in FIG. 1(A), the liquid crystal display device includes a transistor 102 on a substrate 1, a pixel electrode 7 connected to the transistor 102, an insulating film 8 in contact with the transistor 102 and the pixel electrode 7, a common electrode 9 in contact with the insulating film 8, and an insulating film 60 in contact with the insulating film 8 and the common electrode 9 and functioning as an alignment film.

The liquid crystal display further includes a light-shielding film 62 and a colored film 63 in contact with the substrate 61, an insulating film 64 in contact with the substrate 61, the light-shielding film 62, and the colored film 63, and an insulating film 65 in contact with the insulating film 64 and functioning as an alignment film. The liquid crystal display further includes a liquid crystal layer 66 between the insulating film 60 and the insulating film 65. Although not shown, polarizing plates are provided on the outer sides of the substrate 1 and the substrate 61.

A staggered type, an inverted staggered type, a coplanar type, or the like can be appropriately used as the transistor 102. In addition, in the case of an inverted staggered type, a channel etch structure, a channel protection structure, or the like can be appropriately used.

The transistor 102 described in this embodiment is an inverted staggered transistor with a channel etch structure. The transistor 102 includes a conductive film 2 over a substrate 1 that functions as a gate electrode, an insulating film 3 over the substrate 1 and the conductive film 2 that functions as a gate insulating film, a semiconductor film 4 that overlaps with the conductive film 2 with the insulating film 3 therebetween, and a conductive film 5 and a conductive film 6 in contact with the semiconductor film 4. The conductive film 2 functions as a scan line together with the gate electrode. That is, the gate electrode is a part of the scan line. The conductive film 5 functions as a signal line. The conductive films 5 and 6 function as a source electrode and a drain electrode. That is, one of the source electrode and the drain electrode is a part of the signal line. For these reasons, the transistor 102 is electrically connected to the scan line and the signal line. Note that the conductive film 2 functions as a scan line together with the gate electrode here, but the gate electrode and the scan line may be formed separately. The conductive film 5 functions as one of the source electrode and the drain electrode and the signal line, but the one of the source electrode and the drain electrode and the signal line may be formed separately.

Note that in the transistor 102, a semiconductor material such as silicon, silicon germanium, or an oxide semiconductor can be used as appropriate for the semiconductor film 4. The semiconductor film 4 can have an amorphous structure, a microcrystalline structure, a polycrystalline structure, a single crystal structure, or the like as appropriate.

1B, the pixel electrode 7 has a rectangular shape in the pixel 10. Since the display device described in this embodiment is an active matrix liquid crystal display device, the pixel electrodes 7 are arranged in a matrix. The pixel electrodes 7 and the common electrode 9 are formed of a light-transmitting film.

The shape of the pixel electrode 7 is not limited to a rectangular shape, and may be an appropriate shape according to the shape of the pixel 10. It is preferable that the pixel electrode 7 is formed widely in a region surrounded by the conductive film 2 functioning as a scanning line and the conductive film 5 functioning as a signal line in the pixel 10. As a result, the aperture ratio in the pixel 10 can be increased.

The common electrode 9 has a plurality of regions (first regions) extending in a direction intersecting with the conductive film 5 functioning as a signal line. That is, it has striped regions (multiple first regions) extending in a direction intersecting with the conductive film 5 functioning as a signal line. The striped regions are connected to a region (second region) extending in a direction parallel or approximately parallel to the conductive film 5 functioning as a signal line. That is, the common electrode 9 is composed of the striped regions (multiple first regions) and a connection region (second region) connected to the striped regions.

In other words, the common electrode 9 has a plurality of regions (first regions) on the pixel electrode 7 that extend in a direction parallel or approximately parallel to the conductive film 2 that functions as a scanning line. That is, the common electrode 9 has striped regions (a plurality of first regions) that extend in a direction parallel or approximately parallel to the conductive film 2 that functions as a scanning line. The striped regions are connected to a region (second region) that extends in a direction intersecting the conductive film 2 that functions as a scanning line.

The angle at which the extending direction of the striped regions (plurality of first regions) in the common electrode 9 intersects with the extending direction of the conductive film 5 functioning as a signal line is preferably 70° or more and 110° or less. By intersecting at such an angle, it is possible to reduce light leakage. In addition, since the common electrode 9 is not formed over the entire surface of the substrate 1 and has striped regions (plurality of first regions), it is possible to reduce parasitic capacitance generated between the conductive film 2 functioning as a scanning line and the conductive film 5 functioning as a signal line and the common electrode 9.

Moreover, the striped regions (plurality of first regions) in the common electrode 9 can be linear. Alternatively, the striped regions (plurality of first regions) in the common electrode 9 can be in a shape of repeated zigzag broken lines, wavy lines, or other curved lines. When the striped regions (plurality of first regions) in the common electrode 9 are in a shape of repeated broken lines or curved lines, the alignment state of the liquid crystal molecules becomes multi-domain, and the viewing angle is improved.

Since the common electrode 9 has a striped shape, when a voltage is applied to the pixel electrode 7, a parabolic electric field is generated between the pixel electrode 7 and the common electrode 9, as shown by the dashed arrow in Fig. 1(A). As a result, the liquid crystal molecules contained in the liquid crystal layer 66 can be aligned.

In the region where the pixel electrode 7 and the common electrode 9 overlap, the pixel electrode 7, the insulating film 8, and the common electrode 9 function as a capacitance element. Since the pixel electrode 7 and the common electrode 9 are formed of a film having light-transmitting properties, the aperture ratio is increased and the charge capacity stored in the capacitance element can be increased. In addition, by forming the insulating film 8 between the pixel electrode 7 and the common electrode 9 using a material with a high relative dielectric constant, it is possible to store a large charge capacity in the capacitance element. Examples of materials with a high relative dielectric constant include silicon nitride, aluminum oxide, gallium oxide, yttrium oxide, hafnium oxide, and hafnium silicate (HfSiO_x), nitrogen-doped hafnium silicate (HfSi_xO_yN_z), nitrogen-doped hafnium aluminate (HfAl_xO_yN_z) etc.

The light-shielding film 62 functions as a black matrix. The colored film 63 functions as a color filter. Note that the colored film 63 does not necessarily have to be provided. For example, when the liquid crystal display device displays black and white, the colored film 63 may not be provided.

The colored film 63 may be any colored film that transmits light in a specific wavelength band, such as a red (R) film that transmits light in the red wavelength band, a green (G) film that transmits light in the green wavelength band, or a blue (B) film that transmits light in the blue wavelength band.

The light-shielding film 62 may be any film capable of blocking light in a specific wavelength range, and may be a metal film or an organic insulating film containing a black pigment or the like.

The insulating film 65 has a function as a planarizing layer, or a function of suppressing the diffusion of impurities that may be contained in the colored film 63 toward the liquid crystal element side.

Although not shown, a sealant is provided between the substrate 1 and the substrate 61, and the substrate 1, the substrate 61, and the sealant seal the liquid crystal layer 66. A spacer may be provided between the insulating film 60 and the insulating film 64 to maintain the thickness (also called a cell gap) of the liquid crystal layer 66.

Next, a method for driving the liquid crystal display device shown in this embodiment mode will be described with reference to FIG.

2 is a top view of a pixel included in a pixel portion of an FFS mode liquid crystal display device, showing two adjacent pixels 10a and 10b. In Fig. 2(A) and Fig. 2(B), a common electrode 9 extends in a direction parallel or approximately parallel to a conductive film 2 that functions as a scanning line. In other words, the common electrode 9 spans the pixels 10a and 10b.

2(A) and 2(B) show pixels 10a and 10b provided with a common electrode 9 having a striped region extending in a direction intersecting with the conductive films 5a and 5b functioning as signal lines, and FIGS. 2(C) and 2(D) show pixels 10a and 10b provided with a common electrode 9 having a striped region extending in a direction intersecting with the conductive film 2 functioning as a scanning line. A method of driving a display element in each pixel in which the initial state is black display and white display is achieved by applying a voltage to the pixel electrode, that is, a method of driving a display element in a normally black mode, will be described. Note that the display element here refers to the pixel electrode 7, the common electrode 9, and liquid crystal molecules contained in the liquid crystal layer. Note that in this embodiment, a normally black mode driving method will be described, but a normally white mode driving method may also be used as appropriate.

In addition, when displaying black, a voltage that turns on the transistor is applied to the scanning line, and 0V is applied to the signal line and the common electrode. As a result, 0V is applied to the pixel electrode. In other words, no electric field is generated between the pixel electrode and the common electrode, and the liquid crystal molecules do not move.

To display white, a voltage that turns on the transistor is applied to the scan line, a voltage that moves the liquid crystal molecules, for example 6 V, is applied to the signal line, and 0 V is applied to the common electrode. As a result, 6 V is applied to the pixel electrode. In other words, an electric field is generated between the pixel electrode and the common electrode, and the liquid crystal molecules move.

In addition, since a negative type liquid crystal material is used for the explanation here, in the initial state, the liquid crystal molecules are aligned in a direction perpendicular to the common electrode. In this manner, the alignment of the liquid crystal molecules in the initial state is called the initial alignment. Furthermore, by applying a voltage between the pixel electrode and the common electrode, the liquid crystal molecules are rotated in a plane parallel to the substrate. Note that, although a negative type liquid crystal material is used for the explanation in this embodiment, a positive type liquid crystal material can also be used as appropriate.

Polarizing plates are provided on the outer sides of the substrate 1 and the substrate 61 shown in FIG. 1A. The polarizer included in the polarizing plate provided on the outer side of the substrate 1 and the polarizer included in the polarizing plate provided on the outer side of the substrate 61 are arranged in a crossed Nicol configuration so as to be perpendicular to each other. Therefore, when the liquid crystal molecules are oriented in a direction parallel to the conductive film 2 functioning as the scanning line or the conductive films 5a and 5b functioning as the signal line, the light is absorbed in the polarizing plate, resulting in a black display. Note that, in this embodiment, the polarizers are described as being in a crossed Nicol configuration, but they may also be in a parallel Nicol configuration as appropriate.

2, a pixel having the conductive film 2 functioning as a scanning line, the semiconductor film 4a, the conductive film 5a functioning as a signal line, the conductive film 6a, the pixel electrode 7a, and the common electrode 9 is referred to as pixel 10a, and a pixel having the conductive film 2 functioning as a scanning line, the semiconductor film 4b, the conductive film 5b functioning as a signal line, the conductive film 6b, the pixel electrode 7b, and the common electrode 9 is referred to as pixel 10b. In addition, Figures 2(A) and 2(C) show the initial state, and Figures 2(B) and 2(D) show the state in which pixel 10b displays white.

In the pixels 10a and 10b shown in Figures 2(C) and 2(D), the common electrode 9 extends in a direction parallel or approximately parallel to the conductive films 5a and 5b functioning as signal lines, so that in the initial state (black display) shown in Figure 2(C), the liquid crystal molecules L are oriented in a direction perpendicular to the conductive films 5a and 5b functioning as signal lines.

As shown in Fig. 2(D), a case will be described where pixel 10a displays black and pixel 10b displays white. 0V is applied to the conductive film 5a, which functions as a signal line, and the common electrode 9. 6V is also applied to the conductive film 5b, which functions as a signal line. As a result, 6V is applied to the pixel electrode 7b in pixel 10b, and an electric field is generated between the pixel electrode 7b and the common electrode 9 as shown by the arrow in the figure, and the liquid crystal molecules L are aligned accordingly. Here, the state in which the liquid crystal molecules L are rotated by 45° is shown.

In the pixel 10a, the potential of the pixel electrode 7a is 0V, and the potential of the conductive film 5b functioning as a signal line provided near the pixel electrode 7a is 6V. Therefore, in the pixel 10a as well, as shown by the arrow in the figure, an electric field is generated between the pixel electrode 7a and the conductive film 5b functioning as a signal line, and the liquid crystal molecules L are aligned accordingly. As a result, in the pixel 10a that should display black, the alignment state of some of the liquid crystal molecules L changes, causing light leakage.

On the other hand, in the pixels 10a and 10b shown in Figures 2(A) and 2(B), the common electrode 9 extends in a direction perpendicular to the conductive films 5a and 5b functioning as signal lines, so that in the initial state (black display), the liquid crystal molecules L are oriented in a direction parallel or approximately parallel to the conductive films 5a and 5b functioning as signal lines.

As shown in Fig. 2(B), a case will be described where pixel 10a displays black and pixel 10b displays white. 0V is applied to the conductive film 5a functioning as a signal line and the common electrode 9. 6V is applied to the conductive film 5b functioning as a signal line. As a result, 6V is applied to the pixel electrode 7b in pixel 10b, and an electric field is generated between the pixel electrode 7b and the common electrode 9 as shown by the arrow in the figure, and the liquid crystal molecules L are aligned accordingly. Here, the state where the liquid crystal molecules L are rotated by -45° is shown.

In the pixel 10a, the potential of the pixel electrode 7a is 0 V, and the potential of the conductive film 5b functioning as a signal line provided near the pixel electrode 7a is 6 V. However, since the conductive film 5b functioning as the signal line and the common electrode 9 intersect, a first electric field F1 generated between the pixel electrode 7a and the conductive film 5b functioning as the signal line is perpendicular to the long axis of the liquid crystal molecule L.

As a result, since the liquid crystal molecules L are negative type liquid crystal, the liquid crystal molecules L do not move, and light leakage can be suppressed.

From the above, in an FFS mode liquid crystal display device, by providing a common electrode extending in a direction intersecting with the signal lines, a display device with excellent contrast can be manufactured.

Moreover, the common electrode 9 shown in this embodiment is not formed over the entire surface of the substrate. Therefore, it is possible to reduce the area overlapping with the conductive films 5a and 5b functioning as signal lines, and it is possible to reduce the parasitic capacitance generated between the signal lines and the common electrode 9. As a result, it is possible to reduce wiring delay in a display device formed using a large-area substrate.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

Embodiment 2 In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

In this embodiment, an oxide semiconductor film is used as a semiconductor film included in a transistor.

The display device shown in FIG. 3A includes a pixel portion 101, a scanning line driver circuit 104, a signal line driver circuit 106, m scanning lines 107 arranged in parallel or approximately parallel and whose potentials are controlled by the scanning line driver circuit 104, and n signal lines 109 arranged in parallel or approximately parallel and whose potentials are controlled by the signal line driver circuit 106. The pixel portion 101 includes a plurality of pixels 103 arranged in a matrix. The pixel portion 101 also includes common lines 115 arranged in parallel or approximately parallel along the signal lines 109. The scanning line driver circuit 104 and the signal line driver circuit 106 may be collectively referred to as a driver circuit portion.

Each scanning line 107 is electrically connected to n pixels 103 arranged in any row among the pixels 103 arranged in m rows and n columns in the pixel unit 101. Also, each signal line 109 is electrically connected to m pixels 103 arranged in any column among the pixels 103 arranged in m rows and n columns. Both m and n are integers equal to or greater than 1. Also, each common line 115 is electrically connected to m pixels 103 arranged in any column among the pixels 103 arranged in m rows and n columns.

FIG. 3B shows an example of a circuit configuration that can be used for the pixel 103 of the display device shown in FIG.

The pixel 103 shown in FIG. 3B includes a liquid crystal element 121, a transistor 102, and a capacitor 105.

One of a pair of electrodes of the liquid crystal element 121 is connected to the transistor 102, and a potential is set appropriately according to the specifications of the pixel 103. The other of the pair of electrodes of the liquid crystal element 121 is connected to the common line 115, and a common potential (common potential) is applied. The alignment state of the liquid crystal molecules of the liquid crystal element 121 is controlled by data written to the transistor 102.

The liquid crystal element 121 is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal molecules. The optical modulation action of the liquid crystal molecules is controlled by an electric field (including a horizontal electric field, a vertical electric field, or an oblique electric field) applied to the liquid crystal molecules. Examples of liquid crystal materials used for the liquid crystal element 121 include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, ferroelectric liquid crystal, and antiferroelectric liquid crystal.

The display device having the liquid crystal element 121 is driven in the FFS mode.

A liquid crystal element may be formed from a liquid crystal composition containing a liquid crystal material exhibiting a blue phase and a chiral agent. Liquid crystals exhibiting a blue phase have a short response speed of 1 msec or less and are optically isotropic, so no alignment treatment is required and they have little viewing angle dependency.

3B, one of a source electrode and a drain electrode of the transistor 102 is electrically connected to a signal line 109, and the other is electrically connected to one of a pair of electrodes of a liquid crystal element 121. A gate electrode of the transistor 102 is electrically connected to a scan line 107. The transistor 102 has a function of controlling writing of a data signal by being turned on or off.

In the configuration of the pixel 103 shown in FIG. 3B, one of a pair of electrodes of the capacitor 105 is connected to the transistor 102. The other of the pair of electrodes of the capacitor 105 is electrically connected to a common line 115. The potential value of the common line 115 is set as appropriate according to the specifications of the pixel 103. The capacitor 105 has a function as a storage capacitor that holds written data. Note that in this embodiment, one of the pair of electrodes of the capacitor 105 is one of the pair of electrodes of the liquid crystal element 121. The other of the pair of electrodes of the capacitor 105 is the other of the pair of electrodes of the liquid crystal element 121.

Next, a specific configuration of an element substrate included in the display device will be described below. Here, a top view of a plurality of pixels 103a, 103b, and 103c is shown in FIG.

4, the conductive film 13 functioning as the scanning line is provided extending in a direction (horizontal direction in the figure) substantially perpendicular to the signal line. The conductive film 21a functioning as the signal line is provided extending in a direction (vertical direction in the figure) substantially perpendicular to the scanning line. The conductive film 13 functioning as the scanning line is electrically connected to the scanning line driving circuit 104 (see FIG. 3), and the conductive film 21a functioning as the signal line is electrically connected to the signal line driving circuit 106 (see FIG. 3(A)).

The transistor 102 is provided in a region where a scan line and a signal line intersect. The transistor 102 includes a conductive film 13 functioning as a gate electrode, a gate insulating film (not shown in FIG. 4), and a gate insulating film 13a.

4, the gate insulating film 13 includes an oxide semiconductor film 19a having a channel region formed thereon, and conductive films 21a and 21b functioning as a source electrode and a drain electrode. The conductive film 13 also functions as a scan line, and a region overlapping with the oxide semiconductor film 19a functions as a gate electrode of the transistor 102. The conductive film 21a also functions as a signal line, and a region overlapping with the oxide semiconductor film 19a functions as a source electrode or a drain electrode of the transistor 102. In FIG. 4, the end of the scan line is located outside the end of the oxide semiconductor film 19a in the top view. Therefore, the scan line functions as a light-shielding film that blocks light from a light source such as a backlight. As a result, the oxide semiconductor film 19a included in the transistor is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed.

Moreover, the conductive film 21b is electrically connected to the pixel electrode 19b. Moreover, a common electrode 29 is provided on the pixel electrode 19b via an insulating film. An opening 40 indicated by a dashed line is provided in the insulating film provided on the pixel electrode 19b. In the opening 40, the pixel electrode 19b contacts the nitride insulating film (not shown in FIG. 4).

The common electrode 29 has striped regions (multiple first regions) extending in a direction intersecting the signal lines. The multiple first regions are connected to second regions extending in a direction parallel or approximately parallel to the signal lines. Therefore, in the common electrode 29 having striped regions (multiple first regions), each of the multiple first regions is at the same potential.

The capacitor 105 is formed in a region where the pixel electrode 19b overlaps with the common electrode 29. The pixel electrode 19b and the common electrode 29 have light-transmitting properties. That is, the capacitor 105 has light-transmitting properties.

As shown in FIG. 4, the liquid crystal display device shown in this embodiment is an FFS mode, and further includes a common electrode 29 having a striped region extending in a direction intersecting the signal line, so that a display device with excellent contrast can be manufactured.

In addition, since the capacitor 105 has a light-transmitting property, the capacitor 105 can be formed large (with a large area) in the pixel 103. Therefore, the aperture ratio can be increased, typically to 50% or more, preferably to 60% or more, and a display device with increased charge capacity can be obtained. For example, in a display device with high resolution, such as a liquid crystal display device, the area of the pixel is reduced and the area of the capacitor is also reduced. Therefore, in a display device with high resolution, the charge capacity accumulated in the capacitor is reduced. However, since the capacitor 105 described in this embodiment has a light-transmitting property, by providing the capacitor in a pixel, the aperture ratio can be increased while obtaining a sufficient charge capacity in each pixel. Typically, the capacitor can be suitably used in a high-resolution display device with a pixel density of 200 ppi or more, further 300 ppi or more, and further 500 ppi or more.

In addition, in a liquid crystal display device, the larger the capacitance value of the capacitor, the longer the period during which the alignment of the liquid crystal molecules in the liquid crystal element is kept constant when an electric field is applied. When a still image is displayed, the period can be extended, so that the number of times image data is rewritten can be reduced, and power consumption can be reduced. Furthermore, with the structure shown in this embodiment mode, the aperture ratio can be increased even in a high-resolution display device, so that light from a light source such as a backlight can be efficiently utilized, and power consumption of the display device can be reduced.

Note that the top view of one aspect of the embodiment of the present invention is not limited to this. Various configurations can be used. For example, as shown in FIG. 19, in the common electrode 29, the connection region may be formed on the conductive film that functions as each signal line.

5 shows cross-sectional views taken along dashed lines AB and CD in FIG. 4. The transistor 102 shown in FIG. 5 is a channel-etched transistor. Note that the dashed line AB is a cross-sectional view of the transistor 102 in the channel length direction and the capacitor 105, and the cross-sectional view taken along dashed line CD is a cross-sectional view of the transistor 102 in the channel width direction.

The transistor 102 shown in FIG. 5 has a single-gate structure and includes a conductive film 13 functioning as a gate electrode provided over a substrate 11. The transistor 102 also includes a nitride insulating film 15 formed over the substrate 11 and the conductive film 13 functioning as a gate electrode, an oxide insulating film 17 formed over the nitride insulating film 15, an oxide semiconductor film 19a overlapping with the conductive film 13 functioning as a gate electrode through the nitride insulating film 15 and the oxide insulating film 17, and conductive films 21a and 21b functioning as a source electrode and a drain electrode in contact with the oxide semiconductor film 19a. An oxide insulating film 23 is formed over the oxide insulating film 17, the oxide semiconductor film 19a, and the conductive films 21a and 21b functioning as a source electrode and a drain electrode, and an oxide insulating film 25 is formed over the oxide insulating film 23. A nitride insulating film 27 is formed over the oxide insulating film 23, the oxide insulating film 25, and the conductive film 21b. A pixel electrode 19b is formed over the oxide insulating film 17. The pixel electrode 19b is connected to one of the conductive films 21a and 21b functioning as a source electrode and a drain electrode, that is, the conductive film 21b here. In addition, a common electrode 29 is formed on the nitride insulating film 27 .

Moreover, the region where the pixel electrode 19 b , the nitride insulating film 27 , and the common electrode 29 overlap functions as a capacitance element 105 .

Note that the cross-sectional view of one aspect of the embodiment of the present invention is not limited to this. Various configurations can be used. For example, the pixel electrode 19b may have a slit. Or, the pixel electrode 19b may have a comb-tooth shape. An example of a cross-sectional view in this case is shown in FIG. 20. Or, as shown in FIG. 21, an insulating film 26b may be provided on the nitride insulating film 27. For example, an organic resin film may be provided as the insulating film 26b. This allows the surface of the insulating film 26b to be flattened. That is, the insulating film 26b can function as a flattening film, for example. Or, the common electrode 29 and the conductive film 21b may overlap to form the capacitor element 105b. Examples of cross-sectional views in this case are shown in FIG. 22 and FIG. 23.

The configuration of the display device will be described in detail below.

There is no significant restriction on the material of the substrate 11, but it is necessary that the substrate 11 has at least a heat resistance sufficient to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 11. Also, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SOI substrate, made of silicon or silicon carbide, or the like, may be used, and a semiconductor element may be provided on one of these substrates and used as the substrate 11. When a glass substrate is used as the substrate 11, a large-area substrate such as a sixth generation (1500 mm×1850 mm), seventh generation (1870 mm×2200 mm), eighth generation (2200 mm×2400 mm), ninth generation (2400 mm×2800 mm), or tenth generation (2950 mm×3400 mm) substrate may be used to manufacture a large display device.

Alternatively, a flexible substrate may be used as the substrate 11, and the transistor 102 may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 11 and the transistor 102. The peeling layer can be used to separate the display device from the substrate 11 after a part or whole of the display device is completed thereon, and to transfer the display device to another substrate. In this case, the transistor 102 can be transferred to a substrate having poor heat resistance or a flexible substrate.

The conductive film 13 functioning as a gate electrode can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. A metal element selected from one or more of manganese and zirconium may also be used. The conductive film 13 functioning as a gate electrode may have a single layer structure or a laminated structure of two or more layers. For example, there are a single layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is laminated on a titanium film, and a three-layer structure in which a titanium film is laminated on the titanium film and an aluminum film is further laminated on the titanium film. An alloy film or a nitride film in which one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum may also be used.

The conductive film 13 functioning as the gate electrode can be made of a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide has been added. Alternatively, the conductive film 13 can have a stacked structure of the light-transmitting conductive material and the metal element.

The nitride insulating film 15 can be a nitride insulating film with low oxygen permeability. Furthermore, it is possible to use a nitride insulating film with low oxygen, hydrogen, and water permeability. Examples of the nitride insulating film with low oxygen permeability and the nitride insulating film with low oxygen, hydrogen, and water permeability include a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, and an aluminum nitride oxide film. Instead of the nitride insulating film with low oxygen permeability and the nitride insulating film with low oxygen, hydrogen, and water permeability, an oxide insulating film such as an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, or a hafnium oxynitride film can be used.

The thickness of the nitride insulating film 15 is preferably 5 nm or more and 100 nm or less, and more preferably 20 nm or more and 80 nm or less.

The oxide insulating film 17 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, a Ga-Zn-based metal oxide, or the like, and is provided as a stacked layer or a single layer.

The oxide insulating film 17 is made of hafnium silicate (HfSiO_x), nitrogen-doped hafnium silicate (HfSi_xO_yN_z), nitrogen-doped hafnium aluminate (HfAl_xO_yN_zThe gate leakage of transistors can be reduced by using materials with high dielectric constants such as SiO2, hafnium oxide, and yttrium oxide.

The thickness of the oxide insulating film 17 is preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, and even more preferably 50 nm to 250 nm.

Representative examples of the oxide semiconductor film 19a include In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd).

When the oxide semiconductor film 19a is an In-M-Zn oxide film, the atomic ratio of In to M, where the sum of In and M is 100 atomic %, is set such that In is higher than 25 atomic % and M is lower than 75 atomic %, preferably In is higher than 34 atomic % and M is lower than 66 atomic %.

The oxide semiconductor film 19a has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor with a wide energy gap in this manner, the off-state current of the transistor 102 can be reduced.

The thickness of the oxide semiconductor film 19a is 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm.

When the oxide semiconductor film 19a is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), it is preferable that the atomic ratio of metal elements in a sputtering target used to form the In-M-Zn oxide film satisfies InM, ZnM.

The atomic ratio of the metal elements in such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, or In:M:Zn=3:1:2.

Note that the atomic ratio of the oxide semiconductor film 19a to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target as an error.

The oxide semiconductor film 19a is an oxide semiconductor film with low carrier density. For example, the oxide semiconductor film 19a has a carrier density of 1×10¹⁷Pieces/cm³Less than or equal to 1×10¹⁵Pieces/cm³Less than 1×10, more preferably¹³Pieces/cm³Less than or equal to 1×10¹¹Pieces/cm³The following oxide semiconductor film is used.

Note that the composition is not limited to these and may be appropriate depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the semiconductor characteristics of the transistor, it is preferable that the oxide semiconductor film 19a has an appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like.

Note that by using an oxide semiconductor film having a low impurity concentration and a low density of defect states as the oxide semiconductor film 19a, a transistor with better electrical characteristics can be manufactured, which is preferable. Here, an oxide semiconductor film having a low impurity concentration and a low density of defect states (a small amount of oxygen vacancies) is referred to as high-purity intrinsic or substantially high-purity intrinsic. A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has a small number of carrier generation sources, and therefore the carrier density can be reduced in some cases. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film is unlikely to have electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be reduced. In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has an extremely small off-state current and a channel width of 1×10⁶Even if the device has a channel length L of 10 μm and a width of 1 μm, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10^-13A characteristic of A or less can be obtained. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has small fluctuation in electrical characteristics and can be a highly reliable transistor. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, and the like.

Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies are formed in the lattice from which oxygen has been removed (or in the portion from which oxygen has been removed). When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. When some of the hydrogen bonds to oxygen bonded to metal atoms, electrons serving as carriers may be generated. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics.

For this reason, it is preferable that the oxide semiconductor film 19a has as little oxygen vacancy as possible and hydrogen as possible. Specifically, the hydrogen concentration in the oxide semiconductor film 19a measured by secondary ion mass spectrometry (SIMS) is 5×10¹⁹atoms/cm³Less than or equal to 1×10¹⁹atoms/cm³Less than or equal to 5×10¹⁸atoms/cm³Less than or equal to 1×10¹⁸atoms/cm³Less than or equal to 5×10¹⁷atoms/cm³Less than 1×10, more preferably¹⁶atoms/cm³The following applies.

When the oxide semiconductor film 19a contains silicon or carbon, which is one of the group 14 elements, oxygen vacancies increase in the oxide semiconductor film 19a, causing the oxide semiconductor film 19a to become n-type. For this reason, the concentration of silicon or carbon in the oxide semiconductor film 19a (concentration obtained by secondary ion mass spectrometry) is set to 2×10¹⁸atoms/cm³Less than or equal to 2×10¹⁷atoms/cm³The following applies.

In addition, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor film 19a obtained by secondary ion mass spectrometry is 1×10¹⁸atoms/cm³Less than or equal to 2×10¹⁶atoms/cm³When an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, it may generate carriers, which may increase the off-state current of a transistor. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor film 19a.

Furthermore, when the oxide semiconductor film 19a contains nitrogen, electrons serving as carriers are generated, the carrier density increases, and the oxide semiconductor film 19a is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen is likely to have normally-on characteristics. Therefore, it is preferable that the amount of nitrogen in the oxide semiconductor film is as small as possible. For example, the nitrogen concentration measured by secondary ion mass spectrometry is less than 5×10¹⁸atoms/cm³It is preferable to do the following:

The oxide semiconductor film 19a may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

The oxide semiconductor film 19a may have an amorphous structure, for example. An oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and does not contain a crystalline component.

The oxide semiconductor film 19a may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a stacked structure having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region.

The pixel electrode 19b is formed by processing an oxide semiconductor film formed simultaneously with the oxide semiconductor film 19a. Therefore, the pixel electrode 19b is a film having the same metal element as the oxide semiconductor film 19a. Also, the pixel electrode 19b is a film having the same crystal structure as the oxide semiconductor film 19a or a different crystal structure. However, by making the oxide semiconductor film formed simultaneously with the oxide semiconductor film 19a have impurities or oxygen vacancies, the film becomes conductive and functions as the pixel electrode 19b. The impurities contained in the oxide semiconductor film include hydrogen. Note that instead of hydrogen, boron, phosphorus, tin, antimony, rare gas elements, alkali metals, alkaline earth metals, and the like may be contained as impurities. Alternatively, the pixel electrode 19b is a film formed simultaneously with the oxide semiconductor film 19a, in which oxygen vacancies are formed by plasma damage or the like, and the conductivity is increased. Alternatively, the pixel electrode 19b is a film formed simultaneously with the oxide semiconductor film 19a, in which impurities are contained, and in which oxygen vacancies are formed by plasma damage or the like, and the conductivity is increased.

For this reason, both the oxide semiconductor film 19a and the pixel electrode 19b are formed over the oxide insulating film 17 but have different impurity concentrations. Specifically, the impurity concentration of the pixel electrode 19b is higher than that of the oxide semiconductor film 19a. For example, the hydrogen concentration in the oxide semiconductor film 19a is 5×10¹⁹atoms/cm³Less than or equal to 1×10¹⁹atoms/cm³Less than or equal to 5×10¹⁸atoms/cm³Less than or equal to 1×10¹⁸atoms/cm³Less than or equal to 5×10¹⁷atoms/cm³Less than 1×10, more preferably¹⁶atoms/cm³The concentration of hydrogen contained in the pixel electrode 19b is 8×10¹⁹atoms/cm³More than 1×10²⁰atoms/cm³More preferably, 5×10²⁰atoms/cm³The concentration of hydrogen contained in the pixel electrode 19b is two times, preferably ten times or more, higher than that in the oxide semiconductor film 19a.

Furthermore, by exposing an oxide semiconductor film formed simultaneously with the oxide semiconductor film 19a to plasma, the oxide semiconductor film can be damaged and oxygen vacancies can be formed. For example, when a film is formed on the oxide semiconductor film by a plasma CVD method or a sputtering method, the oxide semiconductor film is exposed to plasma and oxygen vacancies are generated. Alternatively, the oxide semiconductor film is exposed to plasma in an etching treatment for forming the oxide insulating film 23 and the oxide insulating film 25, and oxygen vacancies are generated. Alternatively, the oxide semiconductor film is exposed to plasma of a mixed gas of oxygen and hydrogen, hydrogen, a rare gas, ammonia, or the like, and oxygen vacancies are generated. As a result, the oxide semiconductor film becomes highly conductive and functions as the pixel electrode 19b.

That is, it can be said that the pixel electrode 19b is formed of a highly conductive oxide semiconductor film, or that the pixel electrode 19b is formed of a highly conductive metal oxide film.

Furthermore, when a silicon nitride film is used as the nitride insulating film 27, the silicon nitride film contains hydrogen. Therefore, when hydrogen in the nitride insulating film 27 diffuses into the oxide semiconductor film formed simultaneously with the oxide semiconductor film 19a, hydrogen bonds with oxygen in the oxide semiconductor film, generating electrons as carriers. Furthermore, when the silicon nitride film is formed by the plasma CVD method or the sputtering method, the oxide semiconductor film is exposed to plasma, generating oxygen vacancies. Hydrogen contained in the silicon nitride film enters the oxygen vacancies, generating electrons as carriers. As a result, the oxide semiconductor film becomes highly conductive, becoming the pixel electrode 19b.

When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed, hydrogen enters the oxygen vacancy sites and a donor level is formed near the conduction band. As a result, the oxide semiconductor becomes more conductive and becomes a conductor. The oxide semiconductor that has become a conductor can be called an oxide conductor. In other words, the pixel electrode 19b can be said to be formed of an oxide conductor film. In general, an oxide semiconductor has a large energy gap and is therefore transparent to visible light. On the other hand, an oxide conductor is an oxide semiconductor that has a donor level near the conduction band. Therefore, the effect of absorption due to the donor level is small, and the oxide conductor has the same level of transparency to visible light as an oxide semiconductor.

The pixel electrode 19b has a lower resistivity than the oxide semiconductor film 19a. The resistivity of the pixel electrode 19b is 1×10^-8More than 1x10 times^-1It is preferable that the ratio is less than 1×10^-3Ωcm or more 1×10⁴Ωcm, and more preferably a resistivity of 1×10^-3Ωcm or more 1×10^-1It is preferable that the resistivity is less than Ωcm.

The conductive films 21a and 21b functioning as the source electrode and the drain electrode are made of a single metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy mainly composed of such metal, in a single layer structure or a multilayer structure. For example, there are a single layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a three-layer structure in which a titanium film or a titanium nitride film is laminated on the titanium film or the titanium nitride film, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or a molybdenum nitride film is laminated on the molybdenum film or the molybdenum nitride film, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon. A transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

An oxide insulating film containing more oxygen than the stoichiometric composition is preferably used as the oxide insulating film 23 or the oxide insulating film 25. Here, an oxide insulating film that transmits oxygen is formed as the oxide insulating film 23, and an oxide insulating film containing more oxygen than the stoichiometric composition is formed as the oxide insulating film 25.

The oxide insulating film 23 is an oxygen-permeable oxide insulating film. Therefore, oxygen desorbed from the oxide insulating film 25 provided over the oxide insulating film 23 can be moved to the oxide semiconductor film 19a through the oxide insulating film 23. The oxide insulating film 23 also functions as a film for reducing damage to the oxide semiconductor film 19a when the oxide insulating film 25 is formed later.

As the oxide insulating film 23, a silicon oxide film, a silicon oxynitride film, or the like having a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm, can be used. Note that in this specification, a silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and a silicon nitride oxide film refers to a film whose composition contains more nitrogen than oxygen.

In addition, the oxide insulating film 23 preferably has a small number of defects. Typically, the spin density of the signal appearing at g=2.001 in ESR measurement is 3×10¹⁷spins/cm³or less. Note that the signal that appears at g = 2.001 is derived from silicon dangling bonds. This is because, when the oxide insulating film 23 has a high defect density, oxygen is bonded to the defects and the amount of oxygen that permeates the oxide insulating film 23 is reduced.

In addition, the number of defects at the interface between the oxide insulating film 23 and the oxide semiconductor film 19a is preferably small. Typically, the spin density of a signal at g=1.93 due to defects in the oxide semiconductor film 19a in an ESR measurement is 1×10¹⁷spins/cm³It is preferably below the lower detection limit.

Note that in the oxide insulating film 23, all of the oxygen that enters the oxide insulating film 23 from the outside might move to the outside of the oxide insulating film 23. Alternatively, part of the oxygen that entered the oxide insulating film 23 from the outside might remain in the oxide insulating film 23. In addition, oxygen might enter the oxide insulating film 23 from the outside and oxygen contained in the oxide insulating film 23 might move to the outside of the oxide insulating film 23, causing transfer of oxygen in the oxide insulating film 23.

The oxide insulating film 25 is formed in contact with the oxide insulating film 23. The oxide insulating film 25 is formed using an oxide insulating film that contains more oxygen than the stoichiometric composition. Part of the oxygen is released from the oxide insulating film that contains more oxygen than the stoichiometric composition by heating. The oxide insulating film that contains more oxygen than the stoichiometric composition has a released amount of oxygen of 1.0×10 in terms of oxygen atoms, as determined by TDS analysis.¹⁸atoms/cm³More than 3.0×10²⁰atoms/cm³The oxide insulating film is one having the above-mentioned properties. Note that the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 500° C. or less.

As the oxide insulating film 25, a silicon oxide film, a silicon oxynitride film, or the like having a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm, can be used.

In addition, the oxide insulating film 25 preferably has a small number of defects. Typically, the spin density of the signal appearing at g=2.001 in ESR measurement is 1.5×10¹⁸spins/cm³Less than or even 1×10¹⁸spins/cm³Note that the oxide insulating film 25 is located farther from the oxide semiconductor film 19a than the oxide insulating film 23; therefore, the oxide insulating film 25 may have a higher defect density than the oxide insulating film 23.

The nitride insulating film 27 can be a nitride insulating film with low oxygen permeability like the nitride insulating film 15. Furthermore, a nitride insulating film with low oxygen, hydrogen, and water permeability can be used.

The nitride insulating film 27 may be a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like, having a thickness of 50 nm or more and 300 nm or less, preferably 100 nm or more and 200 nm or less.

When the oxide insulating film 23 or the oxide insulating film 25 includes an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition, part of the oxygen contained in the oxide insulating film 23 or the oxide insulating film 25 can be moved to the oxide semiconductor film 19a, thereby reducing the amount of oxygen vacancies in the oxide semiconductor film 19a.

A transistor including an oxide semiconductor film having oxygen vacancies in the oxide semiconductor film is likely to have a negative shift in threshold voltage and a normally-on characteristic because electric charge is generated due to the oxygen vacancies in the oxide semiconductor film, resulting in low resistance.

When a transistor has normally-on characteristics, various problems occur, such as malfunction during operation, high power consumption during non-operation, etc. In addition, there is a problem that the amount of fluctuation in the electrical characteristics of the transistor, typically the threshold voltage, increases due to aging or stress testing.

However, in the transistor 102 described in this embodiment, the oxide insulating film 23 or the oxide insulating film 25 provided over the oxide semiconductor film 19a is an oxide insulating film containing more oxygen than the oxygen in the stoichiometric composition. As a result, oxygen contained in the oxide insulating film 23 or the oxide insulating film 25 moves efficiently to the oxide semiconductor film 19a, and the amount of oxygen vacancies in the oxide semiconductor film 19a can be reduced. As a result, the transistor has normally-off characteristics. Furthermore, the amount of change in the electrical characteristics of the transistor, typically, the threshold voltage, due to changes over time or a stress test can be reduced.

A light-transmitting conductive film is used for the common electrode 29. Examples of the light-transmitting conductive film include an indium oxide film containing tungsten oxide, an indium zinc oxide film containing tungsten oxide, an indium oxide film containing titanium oxide, an indium tin oxide film containing titanium oxide, an indium tin oxide (hereinafter referred to as ITO) film, an indium zinc oxide film, and an indium tin oxide film to which silicon oxide is added.

The common electrode 29 has a region extending in a stripe shape in a direction intersecting with the conductive film 21a functioning as a signal line. Therefore, it is possible to prevent unintended alignment of liquid crystal molecules in the vicinity of the pixel electrode 19b and the conductive film 21a, and to suppress light leakage. As a result, a display device with excellent contrast can be manufactured.

In addition, in the element substrate of the display device described in this embodiment, a pixel electrode is formed at the same time as the oxide semiconductor film of the transistor. The pixel electrode functions as one electrode of the capacitor. The common electrode functions as the other electrode of the capacitor. For these reasons, a step of forming a new conductive film is not required to form the capacitor, and the manufacturing process can be reduced. In addition, the capacitor has light-transmitting properties. As a result, the area occupied by the capacitor can be increased and the aperture ratio of the pixel can be increased.

Next, a manufacturing method of the transistor 102 and the capacitor 105 shown in FIG. 5 will be described with reference to FIGS.

As shown in Fig. 6(A), a conductive film 12 that will become a conductive film 13 is formed on a substrate 11. The conductive film 12 is formed by a sputtering method, a chemical vapor deposition (CVD) method (including a metalorganic chemical vapor deposition (MOCVD) method, a metal chemical vapor deposition method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), an evaporation method, a pulsed laser deposition (PLD) method, or the like. By using the metalorganic chemical vapor deposition (MOCVD) method, the metal chemical vapor deposition method, or the atomic layer deposition (ALD) method, a conductive film that is less damaged by plasma can be formed.

Here, a glass substrate is used as the substrate 11. In addition, as the conductive film 12, a tungsten film having a thickness of 100 nm is formed by sputtering.

Next, a mask is formed on the conductive film 12 by a photolithography process using a first photomask. Next, a part of the conductive film 12 is etched using the mask to form a conductive film 13 that functions as a gate electrode, as shown in Fig. 6(B). Then, the mask is removed.

The conductive film 13 functioning as the gate electrode may be formed by electrolytic plating, printing, ink-jet printing, or the like instead of the above-mentioned formation method.

Here, the tungsten film is etched by dry etching to form the conductive film 13 which functions as a gate electrode.

6(C), a nitride insulating film 15 and an oxide insulating film 16 which will later become an oxide insulating film 17 are formed over the conductive film 13 which functions as a gate electrode. Next, an oxide semiconductor film 18 which will later become an oxide semiconductor film 19a and a pixel electrode 19b are formed over the oxide insulating film 16.

The nitride insulating film 15 and the oxide insulating film 16 are formed by a sputtering method, a chemical vapor deposition (CVD) method (including a metalorganic chemical vapor deposition (MOCVD) method, a metal chemical vapor deposition method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), an evaporation method, a pulsed laser deposition (PLD) method, a coating method, a printing method, or the like. By using the metalorganic chemical vapor deposition (MOCVD) method, the metal chemical vapor deposition method, or the atomic layer deposition (ALD) method, the nitride insulating film 15 and the oxide insulating film 16 can be formed with less damage caused by plasma. Furthermore, by using the atomic layer deposition (ALD) method, the coverage of the nitride insulating film 15 and the oxide insulating film 16 can be improved.

Here, a silicon nitride film having a thickness of 300 nm is formed as the nitride insulating film 15 by using a plasma CVD method using silane, nitrogen, and ammonia as raw material gases.

When a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is formed as the oxide insulating film 16, a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas. Typical examples of deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. Examples of oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

When a gallium oxide film is formed as the oxide insulating film 16, it can be formed by using an MOCVD method.

Here, a silicon oxynitride film with a thickness of 50 nm is formed as the oxide insulating film 16 by a plasma CVD method using silane and dinitrogen monoxide as source gases.

The oxide semiconductor film 18 can be formed by a sputtering method, a chemical vapor deposition (CVD) method (including a metal-organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), a pulsed laser deposition method, a laser ablation method, a coating method, or the like. By using the metal-organic chemical vapor deposition (MOCVD) method or the atomic layer deposition (ALD) method, it is possible to form the oxide semiconductor film 18 that is less damaged by plasma, and to reduce damage to the oxide insulating film 16. In addition, by using the atomic layer deposition (ALD) method, it is possible to improve the coverage of the oxide semiconductor film 18.

When the oxide semiconductor film is formed by a sputtering method, an RF power supply, an AC power supply, a DC power supply, or the like can be used as appropriate as a power supply for generating plasma.

The sputtering gas may be a rare gas (typically argon), oxygen gas, or a mixed gas of rare gas and oxygen. In the case of a mixed gas of rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to rare gas.

Further, the target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed.

In order to obtain a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film, it is necessary not only to evacuate the chamber to a high vacuum but also to highly purify the sputtering gas. The oxygen gas or argon gas used as the sputtering gas is a gas highly purified to a dew point of 40° C. or less, preferably 80° C. or less, more preferably 100° C. or less, and more preferably 120° C. or less, so that moisture and the like can be prevented from being taken into the oxide semiconductor film as much as possible.

Here, a 35-nm-thick In-Ga-Zn oxide film is formed as the oxide semiconductor film by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1).

Next, a mask is formed on the oxide semiconductor film 18 by a photolithography process using a second photomask, and then part of the oxide semiconductor film is etched using the mask to form element-isolated oxide semiconductor films 19a and 19c as shown in Fig. 6(D). Then, the mask is removed.

Here, a mask is formed over the oxide semiconductor film 18, and part of the oxide semiconductor film 18 is selectively etched by a wet etching method, whereby the oxide semiconductor films 19a and 19c are formed.

Next, as shown in FIG. 7(A), a conductive film 20 which will later become conductive films 21a and 21b is formed.

The conductive film 20 can be formed by appropriately using a method similar to that for the conductive film 12 .

Here, a 50 nm thick tungsten film and a 300 nm thick copper film are laminated in this order by sputtering.

Next, a mask is formed by a photolithography process using a third photomask over the conductive film 20. Next, the conductive film 20 is etched using the mask to form conductive films 21a and 21b functioning as a source electrode and a drain electrode, as shown in FIG.

After this, the mask is removed.

Here, a mask is formed on the copper film by a photolithography process. Next, the tungsten film and the copper film are etched using the mask to form the conductive films 21a and 21b. The copper film is etched by a wet etching method. Next, SF₆The tungsten film is etched by a dry etching method using fluoride, which forms a fluoride on the surface of the copper film during the etching. The fluoride reduces the diffusion of copper elements from the copper film, and the copper concentration in the oxide semiconductor film 19a can be reduced.

7C, the oxide insulating film 22 which will later become the oxide insulating film 23, and the oxide insulating film 24 which will later become the oxide insulating film 25 are formed over the oxide semiconductor films 19a and 19c and the conductive films 21a and 21b. The oxide insulating film 22 and the oxide insulating film 24 can be formed as appropriate by a method similar to that for the nitride insulating film 15 and the oxide insulating film 16.

Note that after the oxide insulating film 22 is formed, the oxide insulating film 24 is preferably formed continuously without exposure to air. By forming the oxide insulating film 22 and then continuously forming the oxide insulating film 24 without exposure to air by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of a source gas, the oxide insulating film 22 can be reduced in the impurity concentration derived from air components at the interface between the oxide insulating film 22 and the oxide insulating film 24 and oxygen contained in the oxide insulating film 24 can be moved to the oxide semiconductor film 19a, so that the amount of oxygen vacancies in the oxide semiconductor film 19a can be reduced.

The oxide insulating film 22 can be formed by maintaining the substrate placed in the evacuated processing chamber of the plasma CVD apparatus at 280°C or higher and 400°C or lower, introducing a raw material gas into the processing chamber to adjust the pressure in the processing chamber to 20 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 250 Pa or lower, and supplying high-frequency power to an electrode provided in the processing chamber.

A deposition gas containing silicon and an oxidizing gas are preferably used as a source gas for the oxide insulating film 22. Typical examples of deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

Under the above conditions, an oxide insulating film that transmits oxygen can be formed as the oxide insulating film 22. Moreover, by providing the oxide insulating film 22, damage to the oxide semiconductor film 19a can be reduced in a later step of forming the oxide insulating film 25.

Under the above film formation conditions, the bonding force between silicon and oxygen is strengthened by setting the substrate temperature to the above temperature. As a result, an oxygen-permeable, dense, and hard oxide insulating film, typically a silicon oxide film or a silicon oxynitride film, whose etching rate is 10 nm/min or less, preferably 8 nm/min or less, when 0.5 wt % hydrofluoric acid is used at 25° C., can be formed as the oxide insulating film 22.

Moreover, since the oxide insulating film 22 is formed while heating, hydrogen, water, and the like contained in the oxide semiconductor film 19a can be desorbed in this process. Hydrogen contained in the oxide semiconductor film 19a combines with oxygen radicals generated in the plasma to become water. Since the substrate is heated in the process of forming the oxide insulating film 22, water generated by the combination of oxygen and hydrogen is desorbed from the oxide semiconductor film. That is, by forming the oxide insulating film 22 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 19a can be reduced.

Furthermore, since heating is performed in the step of forming the oxide insulating film 22, the heating time in the exposed state of the oxide semiconductor film 19a is short, and the amount of oxygen released from the oxide semiconductor film due to the heat treatment can be reduced, that is, the amount of oxygen vacancies in the oxide semiconductor film can be reduced.

Note that by using an oxidizing gas with a rate 100 times or more that of a deposition gas containing silicon, the amount of hydrogen contained in the oxide insulating film 22 can be reduced. As a result, the amount of hydrogen entering the oxide semiconductor film 19a can be reduced, and a negative shift in the threshold voltage of the transistor can be suppressed.

Here, a silicon oxynitride film having a thickness of 50 nm is formed as the oxide insulating film 22 by a plasma CVD method using silane at a flow rate of 30 sccm and dinitrogen monoxide at a flow rate of 4000 sccm as source gases, setting the pressure in the process chamber to 200 Pa, the substrate temperature to 220° C., and supplying a high frequency power of 150 W to parallel plate electrodes using a high frequency power source of 27.12 MHz. Under these conditions, a silicon oxynitride film through which oxygen can pass can be formed.

The oxide insulating film 24 is formed by maintaining the substrate placed in the evacuated processing chamber of the plasma CVD apparatus at 180° C. to 280° C., more preferably 200° C. to 240° C., introducing a source gas into the processing chamber to adjust the pressure in the processing chamber to 100 Pa to 250 Pa, more preferably 100 Pa to 200 Pa, and applying 0.17 W/cm to an electrode provided in the processing chamber.²More than 0.5W/cm²Less than or equal to 0.25 W/cm²More than 0.35W/cm²A silicon oxide film or a silicon oxynitride film is formed under the following conditions for supplying high frequency power.

A deposition gas containing silicon and an oxidizing gas are preferably used as a source gas for the oxide insulating film 24. Typical examples of deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

As a deposition condition of the oxide insulating film 24, by supplying high-frequency power with the above power density in a process chamber with the above pressure, the decomposition efficiency of the source gas in the plasma is increased, oxygen radicals are increased, and oxidation of the source gas progresses, so that the oxygen content in the oxide insulating film 24 becomes higher than the stoichiometric ratio. On the other hand, in a film formed at the above substrate temperature, the bonding strength between silicon and oxygen is weak, so that part of the oxygen in the film is desorbed by heat treatment in a later step. As a result, an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition and from which part of the oxygen is desorbed by heating can be formed. In addition, the oxide insulating film 22 is provided over the oxide semiconductor film 19a. Therefore, in the step of forming the oxide insulating film 24, the oxide insulating film 22 serves as a protective film for the oxide semiconductor film 19a. As a result, the oxide insulating film 24 can be formed using high-frequency power with high power density while reducing damage to the oxide semiconductor film 19a.

Here, a silicon oxynitride film having a thickness of 400 nm is formed as the oxide insulating film 24 by a plasma CVD method using silane at a flow rate of 200 sccm and dinitrogen monoxide at a flow rate of 4000 sccm as source gases, a processing chamber pressure of 200 Pa, a substrate temperature of 220°C, and a high-frequency power of 1500 W supplied to parallel plate electrodes using a high-frequency power source of 27.12 MHz. The plasma CVD apparatus used had an electrode area of 6000 cm.²The power supplied to the device is converted to power per unit area (power density) of 0.25 W/cm²It is.

Furthermore, when the conductive films 21a and 21b functioning as source and drain electrodes are formed, the oxide semiconductor film 19a is damaged by etching of the conductive film, and oxygen vacancies are generated on the back channel side of the oxide semiconductor film 19a (the surface of the oxide semiconductor film 19a opposite to the surface facing the conductive film 13 functioning as a gate electrode). However, by using an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition as the oxide insulating film 24, the oxygen vacancies generated on the back channel side can be repaired by heat treatment. As a result, defects in the oxide semiconductor film 19a can be reduced, and the reliability of the transistor 102 can be improved.

Next, a mask is formed on the oxide insulating film 24 by a photolithography process using a fourth photomask. Next, the oxide insulating film 22 and the oxide insulating film 24 are partly etched using the mask to form the oxide insulating film 23 and the oxide insulating film 25 having the openings 40, as shown in Fig. 7(D). Then, the mask is removed.

In this step, the oxide insulating film 22 and the oxide insulating film 24 are preferably etched by a dry etching method. As a result, the oxide semiconductor film 19c is exposed to plasma in the etching treatment, which can increase the amount of oxygen vacancies in the oxide semiconductor film 19c.

Next, a heat treatment is performed at a temperature of typically 150° C. to 400° C., preferably 300° C. to 400° C., more preferably 320° C. to 370° C.

The heat treatment can be performed using an electric furnace, an RTA device, etc. By using an RTA device, the heat treatment can be performed at a temperature equal to or higher than the distortion point of the substrate for a short period of time, and therefore the heat treatment time can be shortened.

The heat treatment may be carried out under an atmosphere of nitrogen, oxygen, ultra-dry air (air containing 20 ppm or less of water, preferably 1 ppm or less, and preferably 10 ppb or less of water), or a rare gas (argon, helium, etc.). Note that it is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc.

Through this heat treatment, part of oxygen contained in the oxide insulating film 25 can be moved to the oxide semiconductor film 19a, so that the amount of oxygen vacancies in the oxide semiconductor film 19a can be reduced.

When the oxide insulating film 23 and the oxide insulating film 25 contain water, hydrogen, or the like and the nitride insulating film 26 further has a barrier property against water, hydrogen, or the like, if the nitride insulating film 26 is formed later and heat treatment is performed, the water, hydrogen, or the like contained in the oxide insulating film 23 and the oxide insulating film 25 move to the oxide semiconductor film 19a, causing defects in the oxide semiconductor film 19a. However, the heating can eliminate the water, hydrogen, or the like contained in the oxide insulating film 23 and the oxide insulating film 25, thereby reducing variation in the electrical characteristics of the transistor 102 and suppressing a change in the threshold voltage.

Note that by forming the oxide insulating film 24 over the oxide insulating film 22 while heating, oxygen can be transferred to the oxide semiconductor film 19a and the amount of oxygen vacancies in the oxide semiconductor film 19a can be reduced; therefore, the heat treatment is not necessarily performed.

The heat treatment may be performed after the formation of the oxide insulating film 22 and the oxide insulating film 24; however, the heat treatment after the formation of the oxide insulating film 23 and the oxide insulating film 25 is preferable because oxygen is not transferred to the oxide semiconductor film 19c and oxygen is released from the oxide semiconductor film 19c because the oxide semiconductor film 19c is exposed, resulting in formation of oxygen vacancies; thus, a film having higher conductivity can be formed.

Here, heat treatment is performed in a nitrogen and oxygen atmosphere at 350° C. for 1 hour.

Next, as shown in FIG. 8(A), a nitride insulating film 26 is formed.

The nitride insulating film 26 can be formed as appropriate by a method similar to that for the nitride insulating film 15 and the oxide insulating film 16. By forming the nitride insulating film 26 by a sputtering method, a CVD method, or the like, the oxide semiconductor film 19c is exposed to plasma, so that the amount of oxygen vacancies in the oxide semiconductor film 19c can be increased.

Moreover, the oxide semiconductor film 19c has improved conductivity and becomes the pixel electrode 19b. When a silicon nitride film is formed as the nitride insulating film 26 by a plasma CVD method, hydrogen contained in the silicon nitride film diffuses into the oxide semiconductor film 19c, thereby improving the conductivity of the pixel electrode 19b.

When forming a silicon nitride film as the nitride insulating film 26 by the plasma CVD method, it is preferable to maintain the substrate placed in the evacuated processing chamber of the plasma CVD apparatus at a temperature of 300°C or higher and 400°C or lower, more preferably 320°C or higher and 370°C or lower, so that a dense silicon nitride film can be formed.

When forming a silicon nitride film, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as a source gas. By using a small amount of ammonia compared to nitrogen as the source gas, ammonia dissociates in plasma and active species are generated. The active species breaks the bond between silicon and hydrogen and the triple bond of nitrogen contained in the deposition gas containing silicon. As a result, the bond between silicon and nitrogen is promoted, and a dense silicon nitride film with fewer bonds between silicon and hydrogen and fewer defects can be formed. On the other hand, if the amount of ammonia relative to nitrogen in the source gas is large, the decomposition of the deposition gas containing silicon and nitrogen does not progress, and silicon and hydrogen bonds remain, resulting in the formation of a silicon nitride film with increased defects and a rough structure. For these reasons, it is preferable to set the flow rate ratio of nitrogen to ammonia in the source gas to 5 to 50, preferably 10 to 50.

Here, a silicon nitride film having a thickness of 50 nm is formed as the nitride insulating film 26 by the plasma CVD method in which silane at a flow rate of 50 sccm, nitrogen at a flow rate of 5000 sccm, and ammonia at a flow rate of 100 sccm are used as raw material gases in the processing chamber of the plasma CVD apparatus, the processing chamber pressure is set to 100 Pa, the substrate temperature is set to 350°C, and a high frequency power of 1000 W is supplied to the parallel plate electrodes using a high frequency power source of 27.12 MHz. Note that the plasma CVD apparatus has an electrode area of 6000 cm.²The power supplied to the device is converted to power per unit area (power density) of 1.7×10^-1W/cm²It is.

Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. to 400° C., preferably 300° C. to 400° C., and more preferably 320° C. to 370° C. As a result, the negative shift of the threshold voltage can be reduced. In addition, the amount of variation in the threshold voltage can be reduced.

Next, although not shown, a mask is formed on the nitride insulating film 26 by a photolithography process using a fifth photomask, and then the nitride insulating film 26 is etched using the mask to expose the conductive film formed simultaneously with the conductive films 21a and 21b and to form the nitride insulating film 27. The conductive film is connected to the common electrode 29 to be formed later.

Next, as shown in FIG. 8B, a conductive film 28, which will later become a common electrode 29, is formed on the nitride insulating film 27.

The conductive film 28 is formed by a sputtering method, a CVD method, a vapor deposition method or the like.

Next, a mask is formed on the conductive film 28 by a photolithography process using a sixth photomask. Next, a part of the conductive film 28 is etched using the mask to form a common electrode 29 as shown in Fig. 8(C). Although not shown, the common electrode 29 is connected to a connection terminal formed simultaneously with the conductive film 13 or a connection terminal formed simultaneously with the conductive films 21a and 21b. Thereafter, the mask is removed.

Through the above steps, the transistor 102 and the capacitor 105 can be manufactured.

In the element substrate of the display device shown in this embodiment, a common electrode having a region extending in a striped shape in a direction intersecting with the signal lines is formed, so that a display device with excellent contrast can be manufactured.

In addition, since the pixel electrode is formed simultaneously with the oxide semiconductor film of the transistor in the element substrate of the display device described in this embodiment, the transistor 102 and the capacitor 105 can be manufactured using six photomasks. The pixel electrode functions as one electrode of the capacitor. The common electrode functions as the other electrode of the capacitor. For these reasons, a step of forming a new conductive film is not required to form the capacitor, and the manufacturing process can be reduced. In addition, the capacitor has light-transmitting properties. As a result, the area occupied by the capacitor can be increased and the aperture ratio of the pixel can be increased.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

&lt;Modification 1&gt; In the display device shown in the first embodiment, a structure having a common line connected to a common electrode will be described with reference to FIG.

FIG. 9A is a top view of pixels 103a, 103b, and 103c included in the display device, and FIG. 9B is a cross-sectional view taken along dashed lines AB and CD in FIG. 9A.

As shown in FIG. 9(A), a common line 21c is formed, which extends in a direction parallel or substantially parallel to the conductive film 21a functioning as a signal line. Here, in order to make the configuration of the common electrode 29 easier to understand, the shape of the common electrode 29 will be described using hatching. The common electrode 29 has a plurality of first regions indicated by hatching slanting downward to the left and a second region indicated by hatching slanting downward to the right. The plurality of first regions are striped regions. The second region extends in a direction parallel or substantially parallel to the conductive film 21a functioning as a signal line. The second region is connected to the plurality of first regions (striped regions), and therefore can also be called a connection region. The common line 21c overlaps the connection region (second region) of the common electrode 29.

The common line 21c may be provided for each pixel. Alternatively, the common line 21c may be provided for each set of pixels. For example, as shown in FIG. 9A, by providing one common line 21c for three pixels, it is possible to reduce the area occupied by the common line in the display device. As a result, it is possible to increase the area of the pixel and the aperture ratio of the pixel.

Furthermore, in the region where the pixel electrode 19b and the common electrode 29 overlap, the liquid crystal molecules are not easily driven by the electric field generated between the pixel electrode 19b and the connection region (second region) of the common electrode 29. Therefore, by reducing the region where the common electrode 29 connects and overlaps with the pixel electrode 19b, it is possible to increase the region where the liquid crystal molecules are driven, and the aperture ratio can be improved. For example, as shown in FIG. 9(A), by providing the connection region of the common electrode 29 at a position where it does not overlap with the pixel electrode 19b, it is possible to reduce the overlapping area between the connection region of the pixel electrode 19b and the common electrode 29, and it is possible to increase the aperture ratio of the pixel.

9A, one common line 21c is provided for three pixels 103a, 103b, and 103c, but one common line may be provided for two pixels, or one common line may be provided for four or more pixels.

9B, the common line 21c can be formed simultaneously with the conductive film 21a functioning as a signal line. The common electrode 29 is connected to the common line 21c through an opening 42 formed in the oxide insulating film 23, the oxide insulating film 25, and the nitride insulating film 27.

Since the material forming the conductive film 21a has a lower resistivity than the material forming the common electrode 29, it is possible to reduce the resistance of the common electrode 29 and the common line 21c.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

(Embodiment 3) In this embodiment, a display device different from that in Embodiment 2 and a manufacturing method thereof will be described with reference to the drawings. In this embodiment, a transistor included in a high-definition display device has a source electrode and a drain electrode capable of reducing light leakage, which is different from that in Embodiment 2. Note that a description of the configuration that overlaps with that in Embodiment 2 will be omitted.

10 is a top view of the display device shown in this embodiment. The conductive film 21b functioning as one of the source electrode and the drain electrode has an L-shaped top shape. That is, the conductive film 21b has a planar shape in which a region 21b_1 extending in a direction perpendicular to the conductive film 13 functioning as a scan line and a region 21b_2 extending in a direction parallel or substantially parallel to the conductive film 13 are connected, and the region 21b_2 overlaps with one or more of the conductive film 13, the pixel electrode 19b, and the common electrode 29 in the top view. Alternatively, the conductive film 21b has a region 21b_2 extending in a direction parallel or substantially parallel to the conductive film 13, and the region 21b_2 is located between the conductive film 13 and the pixel electrode 19b or the common electrode 29 in the top view.

In a high-definition display device, the area of a pixel is reduced, and therefore the distance between the conductive film 13 functioning as a scanning line and the common electrode 29 is narrowed. In a pixel that displays black, when a voltage that turns on a transistor is applied to the conductive film 13 functioning as a scanning line, an electric field is generated between the pixel electrode 19b and the conductive film 13 functioning as a scanning line. As a result, the liquid crystal molecules rotate in an unintended direction, causing light leakage.

However, in the transistor included in the display device described in this embodiment, the conductive film 21b functioning as one of the source electrode and the drain electrode has a region 21b_2 overlapping with one or more of the conductive film 13, the pixel electrode 19b, and the common electrode 29, or has a region 21b_2 located between the conductive film 13 and the pixel electrode 19b or the common electrode 29 in a top view. As a result, the region 21b_2 shields the electric field of the conductive film 13 functioning as a scan line, so that an electric field generated between the conductive film 13 and the pixel electrode 19b can be suppressed, and light leakage can be reduced.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

(Embodiment 4) In this embodiment, a display device different from those in Embodiments 2 and 3 and a manufacturing method thereof will be described with reference to the drawings. In this embodiment, a high-definition display device is different from that in Embodiment 2 in that it has a common electrode capable of reducing light leakage. Note that description of the configuration overlapping with that in Embodiment 2 will be omitted.

11 is a top view of the display device shown in this embodiment. The common electrode 29a has a striped region 29a_1 extending in a direction intersecting the conductive film 21a functioning as a signal line, and a region 29a_2 connected to the striped region and overlapping with the conductive film 13 functioning as a scan line.

In a high-definition display device, the area of a pixel is reduced, and therefore the distance between the conductive film 13 functioning as a scanning line and the pixel electrode 19b is narrowed. When a voltage is applied to the conductive film 13 functioning as a scanning line, an electric field is generated between the conductive film 13 and the pixel electrode 19b. As a result, the liquid crystal molecules move in an unintended direction, which causes light leakage.

However, the display device described in this embodiment has the common electrode 29a having the region 29a_2 intersecting with the conductive film 13 functioning as a scan line. As a result, it is possible to suppress an electric field generated between the conductive film 13 functioning as a scan line and the common electrode 29a, and it is possible to reduce light leakage.

Note that the top view of one aspect of the embodiment of the present invention is not limited to this. Various configurations can be used. For example, the common electrode 29a may have a region overlapping with a part of the conductive film 13 functioning as a scan line as in FIG. 24 and FIG. 25. A channel region formed in the oxide semiconductor film 19a of the transistor does not overlap with the common electrode 29a. As a result, the electric field of the common electrode 29a is not applied to the channel region, and therefore the leakage current of the transistor can be reduced. In addition, the common electrode 29a shown in FIG. 25 has a region overlapping with the conductive film 13 functioning as a scan line and the conductive film 21a functioning as a signal line, and therefore the electric field of the conductive film 13 and the conductive film 21a can be shielded by the common electrode 29a, and therefore the alignment disorder of the liquid crystal molecules can be reduced.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

(Embodiment 5) In this embodiment, a display device and a manufacturing method thereof, which are different from those in Embodiment 2, will be described with reference to the drawings. This embodiment is different from Embodiment 2 in that a transistor has a structure in which an oxide semiconductor film is provided between different gate electrodes, that is, a transistor has a dual-gate structure. Note that description of the configuration that overlaps with that in Embodiment 2 will be omitted.

A specific structure of an element substrate included in the display device will be described. The element substrate shown in this embodiment is different from that of Embodiment 2 in that, as shown in FIG 12, the element substrate includes a conductive film 13 functioning as a gate electrode, an oxide semiconductor film 19a, conductive films 21a and 21b, and a conductive film 29b functioning as a gate electrode which overlaps with each of a part or all of the oxide insulating film 25. The conductive film 29b functioning as a gate electrode is connected to the conductive film 13 functioning as a gate electrode in openings 41a and 41b.

12 is a channel-etched transistor. Note that AB is a cross-sectional view of the transistor 102a in the channel length direction and the capacitor 105a, and CD is a cross-sectional view of the transistor 102a in the channel width direction and at a connection portion of the conductive film 13 functioning as a gate electrode and the conductive film 29b functioning as a gate electrode.

The transistor 102a shown in FIG. 12 has a dual-gate structure and includes a conductive film 13 functioning as a gate electrode provided over a substrate 11. The transistor 102a also includes a nitride insulating film 15 formed over the substrate 11 and the conductive film 13 functioning as a gate electrode, an oxide insulating film 17 formed over the nitride insulating film 15, an oxide semiconductor film 19a overlapping with the conductive film 13 functioning as a gate electrode through the nitride insulating film 15 and the oxide insulating film 17, and conductive films 21a and 21b functioning as a source electrode and a drain electrode in contact with the oxide semiconductor film 19a. An oxide insulating film 23 is formed over the oxide insulating film 17, the oxide semiconductor film 19a, and the conductive films 21a and 21b functioning as a source electrode and a drain electrode, and an oxide insulating film 25 is formed over the oxide insulating film 23. A nitride insulating film 27 is formed over the nitride insulating film 15, the oxide insulating film 23, the oxide insulating film 25, and the conductive film 21b. A pixel electrode 19b is formed over the oxide insulating film 17. The pixel electrode 19b is connected to one of the conductive films 21a and 21b functioning as a source electrode and a drain electrode, that is, the conductive film 21b in this embodiment. In addition, a common electrode 29 and a conductive film 29b functioning as a gate electrode are formed on the nitride insulating film 27.

As shown in the cross-sectional view along CD, the conductive film 29b functioning as a gate electrode is connected to the conductive film 13 functioning as a gate electrode in openings 41a and 41b provided in the nitride insulating film 15 and the nitride insulating film 27. That is, the conductive film 13 functioning as a gate electrode and the conductive film 29b functioning as a gate electrode have the same potential.

Therefore, by applying the same potential voltage to each gate electrode of the transistor 102a, it is possible to reduce variations in initial characteristics, suppress deterioration in a -GBT stress test, and suppress fluctuations in the on-state current rise voltage at different drain voltages. In addition, the region through which carriers flow in the oxide semiconductor film 19a becomes larger in the film thickness direction, so the amount of carrier movement increases. As a result, the on-state current of the transistor 102a increases and the field-effect mobility increases, typically reaching 20 cm.²/V.s or more.

Separated oxide insulating films 23 and 25 are formed over the transistor 102a described in this embodiment. The separated oxide insulating films 23 and 25 overlap with the oxide semiconductor film 19a. In addition, in a cross-sectional view in the channel width direction, end portions of the oxide insulating film 23 and the oxide insulating film 25 are located outside the oxide semiconductor film 19a. In addition, in the channel width direction shown in FIG. 12, the conductive film 29b functioning as a gate electrode faces a side surface of the oxide semiconductor film 19a with the oxide insulating film 23 and the oxide insulating film 25 interposed therebetween.

At the end of the oxide semiconductor film processed by etching or the like, defects are formed due to damage during processing, and the oxide semiconductor film is contaminated by impurity adhesion or the like. Therefore, it is easily activated by the application of stress such as an electric field, and thus it is easily made n-type (low resistance). Therefore, the end of the oxide semiconductor film 19a overlapping with the conductive film 13 functioning as the gate electrode is easily made n-type. If the end made n-type is provided between the conductive films 21a and 21b functioning as the source electrode and the drain electrode, the n-type region becomes a carrier path, and a parasitic channel is formed. However, as shown in the cross-sectional view of CD, if the conductive film 29b functioning as the gate electrode faces the side surface of the oxide semiconductor film 19a through the oxide insulating films 23 and 25 in the channel width direction, the generation of a parasitic channel in the side surface of the oxide semiconductor film 19a or the region including the side surface and its vicinity is suppressed by the influence of the electric field of the conductive film 29b functioning as the gate electrode. As a result, a transistor with excellent electrical characteristics in which the drain current increases sharply at the threshold voltage is obtained.

The common electrode has a striped region extending in a direction intersecting with the signal line. This makes it possible to prevent unintended alignment of liquid crystal molecules near the pixel electrode 19b and the conductive film 21a, and suppress light leakage. As a result, a display device with excellent contrast can be manufactured.

In the capacitor 105a, the pixel electrode 19b is a film formed simultaneously with the oxide semiconductor film 19a, and contains impurities to enhance its conductivity. Alternatively, the pixel electrode 19b is a film formed simultaneously with the oxide semiconductor film 19a, and contains oxygen vacancies due to plasma damage or the like to enhance its conductivity. Alternatively, the pixel electrode 19b is a film formed simultaneously with the oxide semiconductor film 19a, and contains impurities, and contains oxygen vacancies due to plasma damage or the like to enhance its conductivity.

In the element substrate of the display device described in this embodiment, a pixel electrode is formed at the same time as the oxide semiconductor film of the transistor. The pixel electrode functions as one electrode of the capacitor. The common electrode functions as the other electrode of the capacitor. For these reasons, a step of forming a new conductive film is not required to form the capacitor, and the manufacturing process can be reduced. In addition, the capacitor has light-transmitting properties. As a result, the area occupied by the capacitor can be increased and the aperture ratio of the pixel can be increased.

The details of the configuration of the transistor 102a will be described below, with the same reference numerals as in the second embodiment not being described below.

The conductive film 29b functioning as the gate electrode can be formed using a material similar to that of the common electrode 29 described in Embodiment 2 as appropriate.

Next, a manufacturing method of the transistor 102a and the capacitor 105a shown in FIG. 12 will be described with reference to FIGS.

6 to 8A, a conductive film 13 functioning as a gate electrode, a nitride insulating film 15, an oxide insulating film 16, an oxide semiconductor film 19a, a pixel electrode 19b, conductive films 21a and 21b functioning as a source electrode and a drain electrode, an oxide insulating film 22, an oxide insulating film 24, and a nitride insulating film 26 are formed over a substrate 11. In these steps, photolithography steps using first to fourth photomasks are performed.

Next, a mask is formed on the nitride insulating film 26 by a photolithography process using a fifth photomask, and then a portion of the nitride insulating film 26 is etched using the mask to form the nitride insulating film 27 having openings 41a and 41b, as shown in FIG. 13(A).

Next, as shown in FIG. 13B, a conductive film 28, which will later become a common electrode 29 and a conductive film 29b which will function as a gate electrode, is formed on the conductive film 13, the conductive film 21b, and the nitride insulating film 27 which function as a gate electrode.

Next, a mask is formed over the conductive film 28 by a photolithography process using a sixth photomask. Next, the conductive film 28 is partly etched using the mask to form a conductive film 29b that functions as a common electrode 29 and a gate electrode, as shown in Fig. 13(C). Then, the mask is removed.

Through the above steps, the transistor 102a and the capacitor 105a can be manufactured.

In the transistor described in this embodiment, the common electrode 29 functioning as a gate electrode faces a side surface of the oxide semiconductor film 19a through the oxide insulating films 23 and 25 in the channel width direction, so that generation of a parasitic channel in the side surface of the oxide semiconductor film 19a or a region including the side surface and its vicinity is suppressed by the influence of an electric field of the conductive film 29b functioning as a gate electrode. As a result, the transistor has excellent electrical characteristics in which the drain current increases sharply at the threshold voltage.

In the element substrate of the display device shown in this embodiment, a common electrode having a region extending in a striped shape in a direction intersecting with the signal lines is formed, so that a display device with excellent contrast can be manufactured.

In addition, in the element substrate of the display device described in this embodiment, a pixel electrode is formed at the same time as the oxide semiconductor film of the transistor. The pixel electrode functions as one electrode of the capacitor. The common electrode functions as the other electrode of the capacitor. For these reasons, a step of forming a new conductive film is not required to form the capacitor, and the manufacturing process can be reduced. In addition, the capacitor has light-transmitting properties. As a result, the area occupied by the capacitor can be increased and the aperture ratio of the pixel can be increased.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

(Embodiment 6) For the conductive films 21a and 21b functioning as source and drain electrodes in the transistors described in any of Embodiments 2 to 5, a conductive material that easily bonds with oxygen, such as tungsten, titanium, aluminum, copper, molybdenum, chromium, or tantalum alone or an alloy thereof, can be used. As a result, oxygen contained in the oxide semiconductor film 19a is bonded to the conductive material contained in the conductive films 21a and 21b functioning as the source and drain electrodes, and an oxygen-deficient region is formed in the oxide semiconductor film 19a. In addition, some of the constituent elements of the conductive films 21a and 21b functioning as the source and drain electrodes may be mixed into the oxide semiconductor film 19a. As a result, a low-resistance region is formed in the oxide semiconductor film 19a near a region in contact with the conductive films 21a and 21b functioning as the source and drain electrodes. The low-resistance region is formed in contact with the conductive films 21a and 21b functioning as the source and drain electrodes and between the oxide insulating film 17 and the conductive films 21a and 21b functioning as the source and drain electrodes. Since the low-resistance region has high conductivity, it is possible to reduce the contact resistance between the oxide semiconductor film 19a and the conductive films 21a and 21b functioning as a source electrode and a drain electrode, and therefore it is possible to increase the on-state current of the transistor.

The conductive films 21a and 21b functioning as the source and drain electrodes may have a stacked structure of the above-mentioned conductive material that easily bonds with oxygen and a conductive material that does not easily bond with oxygen, such as titanium nitride, tantalum nitride, or ruthenium. Such a stacked structure can prevent oxidation of the conductive films 21a and 21b functioning as the source and drain electrodes at the interface between the conductive films 21a and 21b functioning as the source and drain electrodes and the oxide insulating film 23, and can suppress an increase in resistance of the conductive films 21a and 21b functioning as the source and drain electrodes.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

(Embodiment 7) In this embodiment, a display device including a transistor in which the amount of defects in an oxide semiconductor film can be further reduced as compared with Embodiments 2 to 5 will be described with reference to the drawings. The transistor described in this embodiment is different from those in Embodiments 2 to 5 in that it includes a multilayer film including a plurality of oxide semiconductor films. Here, the transistor will be described in detail with reference to Embodiment 2.

14 shows a cross-sectional view of an element substrate of a display device, which corresponds to a cross-sectional view taken along dashed lines AB and CD in FIG.

The transistor 102b shown in Figure 14(A) has a multilayer film 37a that overlaps with the conductive film 13 functioning as a gate electrode with the nitride insulating film 15 and the oxide insulating film 17 interposed therebetween, and conductive films 21a and 21b functioning as a source electrode and a drain electrode in contact with the multilayer film 37a.

In addition, the oxide insulating film 23, the oxide insulating film 25, and the nitride insulating film 27 are formed over the nitride insulating film 15, the oxide insulating film 17, the multilayer film 37a, and the conductive films 21a and 21b functioning as the source electrode and the drain electrode.

14A includes a multilayer film 37b formed on an oxide insulating film 17, a nitride insulating film 27 in contact with the multilayer film 37b, and a common electrode 29 in contact with the nitride insulating film 27. The multilayer film 37b includes an oxide semiconductor film 19f and an oxide semiconductor film 39b. That is, the multilayer film 37b has a two-layer structure. The multilayer film 37b functions as a pixel electrode.

In the transistor 102b described in this embodiment, the multilayer film 37a includes an oxide semiconductor film 19a and an oxide semiconductor film 39a. That is, the multilayer film 37a has a two-layer structure. Part of the oxide semiconductor film 19a functions as a channel region. The oxide insulating film 23 is formed in contact with the oxide semiconductor film 39a, and the oxide insulating film 25 is formed in contact with the oxide insulating film 23. That is, the oxide semiconductor film 39a is provided between the oxide semiconductor film 19a and the oxide insulating film 23.

The oxide semiconductor film 39a is an oxide film composed of one or more elements constituting the oxide semiconductor film 19a. Therefore, interfacial scattering is unlikely to occur at the interface between the oxide semiconductor film 19a and the oxide semiconductor film 39a. Therefore, the movement of carriers is not hindered at the interface, and the field-effect mobility of the transistor is increased.

The oxide semiconductor film 39a is typically an In-Ga oxide film, an In-Zn oxide film, or an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), and has a conduction band lower end energy closer to the vacuum level than the oxide semiconductor film 19a. Typically, the difference between the conduction band lower end energy of the oxide semiconductor film 39a and the conduction band lower end energy of the oxide semiconductor film 19a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the oxide semiconductor film 39a and the electron affinity of the oxide semiconductor film 19a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

The oxide semiconductor film 39a preferably contains In because it has high carrier mobility (electron mobility).

The oxide semiconductor film 39a containing Al, Ga, Y, Zr, La, Ce, or Nd at a higher atomic ratio than In may have the following effects: (1) The energy gap of the oxide semiconductor film 39a is increased. (2) The electron affinity of the oxide semiconductor film 39a is decreased. (3) The diffusion of impurities from the outside is reduced. (4) The insulating property is increased compared to the oxide semiconductor film 19a. (5) Since Al, Ga, Y, Zr, La, Ce, or Nd is a metal element that has a strong bond with oxygen, oxygen vacancies are less likely to occur.

When the oxide semiconductor film 39a is an In-M-Zn oxide film, when the sum of In and M is 100 atomic %, the atomic ratio of In to M is preferably such that In is less than 50 atomic % and M is 50 atomic % or more, and more preferably In is less than 25 atomic % and M is 75 atomic % or more.

Furthermore, when the oxide semiconductor film 19a and the oxide semiconductor film 39a are In-M-Zn oxide films (M is Al, Ga, Y, Zr, La, Ce, or Nd), the atomic ratio of M (Al, Ga, Y, Zr, La, Ce, or Nd) contained in the oxide semiconductor film 39a is larger than that of the oxide semiconductor film 19a, and is typically 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher than that of the above atoms contained in the oxide semiconductor film 19a.

In addition, when the oxide semiconductor film 19a and the oxide semiconductor film 39a are In-M-Zn oxide films (M is Al, Ga, Y, Zr, La, Ce, or Nd), the oxide semiconductor film 39a is formed of In:M:Zn=x₁:y₁:z₁[Atomic ratio], the oxide semiconductor film 19a is In:M:Zn=x₂:y₂:z₂[Atomic ratio], y₁/x₁y₂/x₂preferably greater than y₁/x₁y₂/x₂More preferably, y₁/x₁y₂/x₂More preferably, y₁/x₁y₂/x₂More than three times larger than

When the oxide semiconductor film 19a is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), the atomic ratio of metal elements in a target used for depositing the oxide semiconductor film 19a is In:M:Zn=x₁:y₁:z₁So,_、x₁/y₁is 1/3 or more and 6 or less, and further 1 or more and 6 or less, and z₁/y₁is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less.₁/y₁A CAAC-OS film is likely to be formed as the oxide semiconductor film 19a when the atomic ratio is greater than or equal to 1 and less than or equal to 6. Typical examples of the atomic ratio of metal elements in the target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, and the like.

When the oxide semiconductor film 39a is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), the atomic ratio of metal elements in a target used for depositing the oxide semiconductor film 39a is In:M:Zn=x₂:y₂:z₂So,_、x₂/y₂&lt;x₁/y₁Where z₂/y₂is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less.₂/y₂A CAAC-OS film is likely to be formed as the oxide semiconductor film 39a when the atomic ratio is greater than or equal to 1 and less than or equal to 6. Typical examples of the atomic ratio of metal elements in the target include In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:6:8, and the like.

Note that the atomic ratios of the oxide semiconductor film 19a and the oxide semiconductor film 39a each include a variation of ±40% of the above atomic ratio as an error.

The oxide semiconductor film 39a also functions as a film for reducing damage to the oxide semiconductor film 19a when the oxide insulating film 25 is formed later.

The thickness of the oxide semiconductor film 39a is greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm.

The oxide semiconductor film 39a may have, for example, a non-single crystal structure, similar to the oxide semiconductor film 19a. The non-single crystal structure includes, for example, a C-Axis Aligned-Crystalline Oxide Semiconductor (CAAC-OS), which will be described later, a polycrystalline structure, a microcrystalline structure, which will be described later, or an amorphous structure.

The oxide semiconductor film 39a may have an amorphous structure, for example. An oxide semiconductor film with an amorphous structure has, for example, disordered atomic arrangement and does not contain crystalline components.

Note that each of the oxide semiconductor film 19a and the oxide semiconductor film 39a may be a mixed film having two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure having two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a stacked structure in which two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region are stacked.

Here, the oxide semiconductor film 39a is provided between the oxide semiconductor film 19a and the oxide insulating film 23. Therefore, even if a carrier trap is formed between the oxide semiconductor film 39a and the oxide insulating film 23 due to impurities and defects, there is a gap between the carrier trap and the oxide semiconductor film 19a. As a result, electrons flowing through the oxide semiconductor film 19a are less likely to be captured by the carrier trap, which makes it possible to increase the on-state current of the transistor and to improve the field-effect mobility. When electrons are captured by the carrier trap, the electrons become negative fixed charges. As a result, the threshold voltage of the transistor fluctuates. However, because there is a gap between the oxide semiconductor film 19a and the carrier trap, it is possible to reduce the capture of electrons by the carrier trap, and the amount of fluctuation in the threshold voltage can be reduced.

Since the oxide semiconductor film 39a can block impurities from the outside, the amount of impurities moving from the outside to the oxide semiconductor film 19a can be reduced. Furthermore, oxygen vacancies are unlikely to be formed in the oxide semiconductor film 39a. For these reasons, the impurity concentration and the amount of oxygen vacancies in the oxide semiconductor film 19a can be reduced.

Note that the oxide semiconductor film 19a and the oxide semiconductor film 39a are fabricated so as to form a continuous junction (here, a structure in which the energy of the bottom of the conduction band changes continuously between the films) rather than simply stacking the films. That is, the stacked structure is formed so that impurities that form defect levels such as trap centers or recombination centers are not present at the interfaces between the films. If impurities are present between the stacked oxide semiconductor film 19a and the oxide semiconductor film 39a, the continuity of the energy band is lost and carriers are trapped or recombined at the interfaces and disappear.

To form a continuous junction, it is necessary to use a multi-chamber film formation device (sputtering device) equipped with a load lock chamber to continuously stack each film without exposing it to the air. Each chamber in the sputtering device is evacuated to a high vacuum (5×10) using an adsorption-type vacuum exhaust pump such as a cryopump to remove water and other impurities that are harmful to the oxide semiconductor film as much as possible.^-7Pa to 1×10^-4It is preferable to set the pressure to about 100 Pa. Alternatively, it is preferable to combine a turbo molecular pump with a cold trap to prevent gas, particularly gas containing carbon or hydrogen, from flowing back into the chamber from the exhaust system.

Note that a transistor 102c illustrated in FIG. 14B may have a multilayer film 38a instead of the multilayer film 37a.

Moreover, instead of the multilayer film 37b, a multilayer film 38b may be provided as in a capacitive element 105c shown in FIG. 14(B).

The multilayer film 38a includes an oxide semiconductor film 49a, an oxide semiconductor film 19a, and an oxide semiconductor film 39a. That is, the multilayer film 38a has a three-layer structure. The oxide semiconductor film 19a functions as a channel region.

The oxide semiconductor film 49a can be formed using a material and a method similar to those of the oxide semiconductor film 39a as appropriate.

The multilayer film 38b includes an oxide semiconductor film 49b, an oxide semiconductor film 19f, and an oxide semiconductor film 39b. That is, the multilayer film 38b has a three-layer structure. The multilayer film 38b functions as a pixel electrode.

The oxide semiconductor film 19f can be formed using a material and a method similar to those of the pixel electrode 19b as appropriate. The oxide semiconductor film 49b can be formed using a material and a method similar to those of the oxide semiconductor film 39b as appropriate.

The oxide insulating film 17 and the oxide semiconductor film 49a are in contact with each other. That is, the oxide semiconductor film 49a is provided between the oxide insulating film 17 and the oxide semiconductor film 19a.

The multilayer film 38a is in contact with the oxide insulating film 23. The oxide semiconductor film 39a is in contact with the oxide insulating film 23. That is, the oxide semiconductor film 39a is provided between the oxide semiconductor film 19a and the oxide insulating film 23.

The oxide semiconductor film 49a is preferably thinner than the oxide semiconductor film 19a. When the thickness of the oxide semiconductor film 49a is 1 nm to 5 nm, preferably 1 nm to 3 nm, the amount of change in the threshold voltage of the transistor can be reduced.

In the transistor described in this embodiment, an oxide semiconductor film 39a is provided between the oxide semiconductor film 19a and the oxide insulating film 23. Therefore, even if a carrier trap is formed between the oxide semiconductor film 39a and the oxide insulating film 23 due to impurities and defects, there is a gap between the carrier trap and the oxide semiconductor film 19a. As a result, electrons flowing through the oxide semiconductor film 19a are less likely to be trapped by the carrier trap, which makes it possible to increase the on-state current of the transistor and to improve the field-effect mobility. When an electron is trapped by a carrier trap, the electron becomes a negative fixed charge.

As a result, the threshold voltage of the transistor fluctuates. However, since there is a gap between the oxide semiconductor film 19a and the carrier traps, the capture of electrons in the carrier traps can be reduced, and thus the amount of fluctuation in the threshold voltage can be reduced.

Since the oxide semiconductor film 39a can block impurities from the outside, the amount of impurities moving from the outside to the oxide semiconductor film 19a can be reduced. Furthermore, oxygen vacancies are unlikely to be formed in the oxide semiconductor film 39a. For these reasons, the impurity concentration and the amount of oxygen vacancies in the oxide semiconductor film 19a can be reduced.

Furthermore, since the oxide semiconductor film 49a is provided between the oxide insulating film 17 and the oxide semiconductor film 19a, and the oxide semiconductor film 39a is provided between the oxide semiconductor film 19a and the oxide insulating film 23, the concentrations of silicon and carbon in the vicinity of the interface between the oxide semiconductor film 49a and the oxide semiconductor film 19a, the concentrations of silicon and carbon in the oxide semiconductor film 19a, or the concentrations of silicon and carbon in the vicinity of the interface between the oxide semiconductor film 39a and the oxide semiconductor film 19a can be reduced. As a result, the absorption coefficient of the multilayer film 38a derived by a constant photocurrent measurement method is 1×10^-3/cm, preferably less than 1×10^-4/cm, and the localized levels are extremely low.

The transistor 102c having such a structure has very few defects in the multilayer film 38a, and therefore the electrical characteristics of the transistor can be improved, typically by increasing the on-state current and improving the field effect mobility. In addition, the threshold voltage fluctuates little in the BT stress test and the light BT stress test, which are examples of the stress test, and the reliability is high.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

Embodiment 8 In this embodiment, one mode that can be applied to an oxide semiconductor film in the transistor included in the display device described in the above embodiment will be described.

The oxide semiconductor film may be formed of one or more of an oxide semiconductor having a single crystal structure (hereinafter referred to as a single crystal oxide semiconductor), an oxide semiconductor having a polycrystalline structure (hereinafter referred to as a polycrystalline oxide semiconductor), an oxide semiconductor having a microcrystalline structure (hereinafter referred to as a microcrystalline oxide semiconductor), and an oxide semiconductor having an amorphous structure (hereinafter referred to as an amorphous oxide semiconductor). The oxide semiconductor film may be formed of a CAAC-OS film. The oxide semiconductor film may be formed of an amorphous oxide semiconductor and an oxide semiconductor having crystal grains. Below, CAAC-OS and a microcrystalline oxide semiconductor are described as typical examples.

&lt;CAAC-OS&gt; The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts. The crystal parts in the CAAC-OS film have a c-axis orientation. In a planar TEM image, the area of the crystal parts in the CAAC-OS film is 2500 nm²More preferably, 5 μm or more²More preferably, 1000 μm or more²Furthermore, when the crystalline portion accounts for 50% or more, preferably 80% or more, and more preferably 95% or more in a cross-sectional TEM image, the thin film has physical properties close to those of a single crystal.

When the CAAC-OS film is observed with a transmission electron microscope (TEM), it is difficult to confirm clear boundaries between crystal parts, that is, grain boundaries. Therefore, it can be said that the CAAC-OS film is unlikely to suffer from a decrease in electron mobility due to grain boundaries.

When the CAAC-OS film is observed by TEM from a direction approximately parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also called the surface on which the CAAC-OS film is formed) or the top surface of the CAAC-OS film, and is arranged parallel to the surface on which the CAAC-OS film is formed or the top surface. In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. In addition, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

On the other hand, when the CAAC-OS film is observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM observation), it can be seen that the metal atoms are arranged in triangular or hexagonal shapes in the crystalline parts, but no regularity is observed in the arrangement of the metal atoms between different crystalline parts.

When the CAAC-OS film is subjected to electron diffraction, spots (bright points) indicating orientation are observed.

Cross-sectional and planar TEM observations reveal that the crystals in the CAAC-OS film have an orientation.

When the structure of the CAAC-OS film is analyzed using an X-ray diffraction (XRD) device, a peak may appear at a diffraction angle (2θ) of about 31° in the out-of-plane analysis of the CAAC-OS film. This peak is attributed to the (00x) plane (x is an integer) of the In-Ga-Zn oxide crystal, which confirms that the crystal of the CAAC-OS film has a c-axis orientation and the c-axis is oriented in a direction approximately perpendicular to the surface on which it is formed or the top surface.

On the other hand, in an analysis of a CAAC-OS film by an in-plane method in which X-rays are incident from a direction approximately perpendicular to the c-axis, a peak may appear when 2θ is around 56°. This peak is attributed to the (110) plane of the crystal of In-Ga-Zn oxide. In the case of a single crystal oxide semiconductor film of In-Ga-Zn oxide, when 2θ is fixed at around 56° and analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface, six peaks attributed to a crystal plane equivalent to the (110) plane are observed. In contrast, in the case of a CAAC-OS film, no clear peak appears even when 2θ is fixed at around 56° and φ scan is performed.

From the above, it is found that in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the film has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the film is formed or the top surface. Therefore, each layer of metal atoms arranged in layers confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

The crystals are formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystals is oriented in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or the top surface. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystals may not be parallel to the normal vector of the surface on which the CAAC-OS film is formed or the top surface.

The degree of crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region near the top surface may have a higher degree of crystallinity than the region near the surface on which the film is formed. When an impurity is added to the CAAC-OS film, the degree of crystallinity of the region to which the impurity is added may change, and a region with a different degree of crystallinity may be formed.

In addition, in the analysis of the CAAC-OS film by the out-of-plane method, in addition to the peak at 2θ of about 31°, a peak may also appear at 2θ of about 36°. The peak at 2θ of about 36° indicates that the CAAC-OS film contains a crystal part that does not have c-axis orientation. It is preferable that the CAAC-OS film shows a peak at 2θ of about 31° and does not show a peak at 2θ of about 36°.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon that bond more strongly with oxygen than metal elements constituting the oxide semiconductor film remove oxygen from the oxide semiconductor film, thereby disturbing the atomic arrangement of the oxide semiconductor film and causing a decrease in crystallinity. Heavy metals such as iron and nickel, argon, and carbon dioxide have a large atomic radius (or molecular radius), and therefore, when contained inside the oxide semiconductor film, they disturb the atomic arrangement of the oxide semiconductor film and cause a decrease in crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can become carrier traps or can capture hydrogen and become a carrier generation source.

A semiconductor film having a low impurity concentration and a low density of defect states (a small amount of oxygen vacancies) is called high-purity intrinsic or substantially high-purity intrinsic. A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a small number of carrier generation sources, and therefore the carrier density can be reduced. Thus, a transistor using the oxide semiconductor film is unlikely to have electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). Furthermore, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a small number of carrier traps. Thus, a transistor using the oxide semiconductor film has small fluctuations in its electrical characteristics and is highly reliable. Note that charges trapped in carrier traps in the oxide semiconductor film take a long time to be released and may behave as if they are fixed charges. Thus, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, the change in electrical characteristics of a transistor using a CAAC-OS film due to irradiation with visible light or ultraviolet light is small.

&lt;Microcrystalline oxide semiconductor&gt; In a microcrystalline oxide semiconductor film, it may be difficult to clearly identify crystal parts in an image observed by TEM. The crystal parts contained in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals with a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in an image observed by TEM, it may be difficult to clearly identify crystal grain boundaries in an nc-OS film, for example.

The nc-OS film has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not show regularity in the crystal orientation between different crystal parts. Therefore, no orientation is observed throughout the film.

Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when the structure of the nc-OS film is analyzed by an XRD apparatus using an X-ray with a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected by the out-of-plane analysis. When the nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter (e.g., 50 nm or more) larger than that of the crystal part, a diffraction pattern such as a halo pattern is observed. On the other hand, when the nc-OS film is subjected to electron diffraction (also called nanobeam electron diffraction) using an electron beam with a probe diameter (e.g., 1 nm or more and 30 nm or less) close to the size of the crystal part or smaller than that of the crystal part, a spot is observed. When the nc-OS film is subjected to nanobeam electron diffraction, a region with high brightness that draws a circle (ring shape) may be observed. When the nc-OS film is subjected to nanobeam electron diffraction, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film does not have regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

&lt;Oxide semiconductor film and oxide conductor film&gt; Next, the temperature dependence of conductivity in a film formed of an oxide semiconductor (hereinafter referred to as an oxide semiconductor film (OS)) and a film formed of an oxide conductor that can be used as the pixel electrode 19b (hereinafter referred to as an oxide conductor film (OC)) will be described with reference to FIG. 26. In FIG. 26, the horizontal axis represents the measurement temperature (the lower horizontal axis is 1/T, and the upper horizontal axis is T), and the vertical axis represents the conductivity (1/ρ). The measurement results of the oxide semiconductor film (OS) are indicated by triangles, and the measurement results of the oxide conductor film (OC) are indicated by circles.

Note that a sample including an oxide semiconductor film (OS) was fabricated by forming an In-Ga-Zn oxide film with a thickness of 35 nm on a glass substrate by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2, forming an In-Ga-Zn oxide film with a thickness of 20 nm by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:4:5, and subjecting the resulting film to heat treatment in a nitrogen atmosphere at 450°C, followed by heat treatment in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Furthermore, a silicon oxynitride film was formed by a plasma CVD method.

In addition, a sample containing an oxide conductor film (OC) was prepared by forming a 100 nm thick In-Ga-Zn oxide film on a glass substrate by sputtering using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1, heat-treating the film in a nitrogen atmosphere at 450°C, and then heat-treating the film in a mixed gas atmosphere of nitrogen and oxygen at 450°C, and forming a silicon nitride film by plasma CVD.

26, the temperature dependence of the electrical conductivity in the oxide conductor film (OC) is smaller than that in the oxide semiconductor film (OS). Typically, the rate of change in electrical conductivity of the oxide conductor film (OC) from 80 K to 290 K is less than ±20%. Alternatively, the rate of change in electrical conductivity from 150 K to 250 K is less than ±10%.

In other words, it is presumed that the oxide conductor is a degenerate semiconductor, and the bottom of the conduction band and the Fermi level are equal or almost equal. Therefore, the oxide conductor film (OC) can be used for resistance elements, wiring, electrodes, pixel electrodes, common electrodes, etc.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

(Embodiment 9) In the method for manufacturing a transistor described in the above embodiment, after the conductive films 21a and 21b functioning as a source electrode and a drain electrode are formed, the oxide semiconductor film 19a is exposed to plasma generated in an oxidizing atmosphere, so that oxygen can be supplied to the oxide semiconductor film 19a. Examples of the oxidizing atmosphere include oxygen, ozone, nitrous oxide, and nitrogen dioxide. In the plasma treatment, it is preferable to expose the oxide semiconductor film 19a to plasma generated without applying a bias to the substrate 11 side. As a result, oxygen can be supplied without damaging the oxide semiconductor film 19a, and the amount of oxygen vacancies in the oxide semiconductor film 19a can be reduced. In addition, impurities remaining on the surface of the oxide semiconductor film 19a, such as halogens such as fluorine and chlorine, can be removed by the etching treatment. In addition, it is preferable to perform the plasma treatment while heating at 300° C. or higher. Oxygen in the plasma and hydrogen contained in the oxide semiconductor film 19a are combined to form water. Since the substrate is heated, the water is released from the oxide semiconductor film 19a. As a result, the amount of hydrogen and water contained in the oxide semiconductor film 19a can be reduced.

Note that the structures and methods described in this embodiment mode can be used in appropriate combination with the structures and methods described in other embodiments.

(Embodiment 10) In this embodiment, a structural example of an electronic device to which the display device of one embodiment of the present invention is applied will be described. In addition, in this embodiment, a display module to which the display device of one embodiment of the present invention is applied will be described with reference to FIG.

15 has, between an upper cover 8001 and a lower cover 8002, a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight unit 8007, a frame 8009, a printed circuit board 8010, and a battery 8011. Note that the backlight unit 8007, the battery 8011, the touch panel 8004, etc. may not be provided.

The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate to match the sizes of the touch panel 8004 and the display panel 8006.

The touch panel 8004 can be a resistive or capacitive touch panel superimposed on the display panel 8006. It is also possible to provide a touch panel function to an opposing substrate (sealing substrate) of the display panel 8006. Alternatively, it is also possible to provide an optical sensor in each pixel of the display panel 8006 to make it an optical touch panel.

Alternatively, it is also possible to provide a touch sensor electrode in each pixel of the display panel 8006 to make it a capacitive touch panel.

The backlight unit 8007 has a light source 8008. The light source 8008 may be provided at an end of the backlight unit 8007, and a light diffusion plate may be used.

The frame 8009 has a function of protecting the display panel 8006, as well as a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. The frame 8009 may also function as a heat sink.

The printed circuit board 8010 has a power supply circuit, and a signal processing circuit for outputting a video signal and a clock signal. A power supply for supplying power to the power supply circuit may be an external commercial power supply, or may be a power supply from a separately provided battery 8011. When a commercial power supply is used, the battery 8011 can be omitted.

Furthermore, the display module 8000 may be provided with additional components such as a polarizing plate, a retardation plate, and a prism sheet.

FIG. 16 is an external view of an electronic device including a display device of one embodiment of the present invention.

Examples of electronic devices include television sets (also called televisions or television receivers), computer monitors, cameras such as digital cameras and digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, personal digital assistants, audio playback devices, and large game machines such as pachinko machines.

16A shows a portable information terminal, which includes a main body 1001, a housing 1002, and display units 1003a and 1003b. The display unit 1003b is a touch panel, and a keyboard button 1004 displayed on the display unit 1003b can be touched to operate the screen or input characters. Of course, the display unit 1003a may be configured as a touch panel. A liquid crystal panel or an organic light-emitting panel is manufactured using the transistor described in the above embodiment as a switching element and is applied to the display units 1003a and 1003b, thereby providing a highly reliable portable information terminal.

16(A) can have a function of displaying various information (still images, videos, text images, etc.), a function of displaying a calendar, date, time, etc. on the display unit, a function of operating or editing the information displayed on the display unit, a function of controlling processing by various software (programs), etc. Also, the back or side of the housing may be provided with an external connection terminal (earphone terminal, USB terminal, etc.), a recording medium insertion portion, etc.

The portable information terminal shown in Fig. 16(A) may be configured to transmit and receive information wirelessly. It is also possible to configure the terminal to purchase and download desired book data from an electronic book server wirelessly.

16B shows a portable music player, which includes a main body 1021 provided with a display portion 1023, a fixing portion 1022 for wearing on an ear, a speaker, operation buttons 1024, an external memory slot 1025, and the like. By manufacturing a liquid crystal panel or an organic light-emitting panel using the transistor described in the above embodiment as a switching element and applying it to the display portion 1023, a more reliable portable music player can be provided.

Furthermore, if the portable music player shown in FIG. 16(B) is equipped with an antenna, microphone function, and wireless function and is linked to a mobile phone, it will be possible to have wireless hands-free conversations while driving a passenger car.

16C shows a mobile phone which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone 1034, a pointing device 1036, a camera 1037, an external connection terminal 1038, and the like. The housing 1030 also includes a solar cell 1040 for charging the mobile phone, an external memory slot 1041, and the like. An antenna is built inside the housing 1031. By applying the transistor described in the above embodiment to the display panel 1032, the mobile phone can be made highly reliable.

The display panel 1032 is equipped with a touch panel, and a plurality of operation keys 1035 on which images are displayed are indicated by dotted lines in Fig. 16(C). Note that a boost circuit for boosting the voltage output from the solar cell 1040 to a voltage required for each circuit is also mounted.

The display direction of the display panel 1032 changes appropriately depending on the usage mode. A camera 1037 is provided on the same surface as the display panel 1032, so that videophone is possible. The speaker 1033 and the microphone 1034 are capable of videophone, recording, playback, and the like, in addition to voice calls. Furthermore, the housing 1030 and the housing 1031 can be slid from an unfolded state as shown in FIG. 16(C) to an overlapped state, so that the device can be made compact and suitable for portability.

The external connection terminal 1038 can be connected to various cables such as an AC adapter and a USB cable, and allows charging and data communication with a personal computer, etc. Also, a recording medium can be inserted into the external memory slot 1041 to accommodate the storage and movement of larger amounts of data.

In addition to the above functions, the device may also be equipped with an infrared communication function, a television receiving function, and the like.

16D illustrates an example of a television set. In a television set 1050, a display portion 1053 is incorporated in a housing 1051. Images can be displayed by the display portion 1053. A CPU is incorporated in a stand 1055 that supports the housing 1051. By using the transistor described in the above embodiment for the display portion 1053 and the CPU, the television set 1050 can be made highly reliable.

The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote controller. The remote controller may be provided with a display unit that displays information output from the remote controller.

The television device 1050 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

The television device 1050 also includes an external connection terminal 1054, a storage medium playback/recording unit 1052, and an external memory slot. The external connection terminal 1054 can be connected to various cables such as a USB cable, and data communication with a personal computer or the like is possible. The storage medium playback/recording unit 1052 allows a disk-shaped recording medium to be inserted, and allows data stored in the recording medium to be read and written to the recording medium. It is also possible to display on the display unit 1053 images and videos stored as data in an external memory 1056 inserted in the external memory slot.

Furthermore, when the off-leakage current of the transistor described in the above embodiment is extremely small, the transistor can be used in the external memory 1056 or a CPU, thereby providing a highly reliable television set 1050 with sufficiently reduced power consumption.

This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

<p>In this example, the distribution of transmittance in a pixel of a liquid crystal display device according to one embodiment of the present invention was evaluated by calculation.</p><p>First, the samples used in this example will be described.</p><p>17A shows a top view of Sample 1, which is a comparative example. The pixel shown in Sample 1 is a region inside a scanning line 201 and a common line 203 extending in the horizontal direction, and a signal line 205 extending in the vertical direction (a direction perpendicular to the scanning line and the common line). The size of one pixel is 84 μm in length and 28 μm in width.</p><p>Sample 1 has a common electrode 207 disposed inside a region surrounded by the above-mentioned wiring and the signal lines of horizontally adjacent pixels and electrically connected to the common line 203, and a comb-shaped pixel electrode 209 disposed on the common electrode 207. Note that the teeth of the pixel electrode 209 extend in a direction intersecting with the signal line 205. In addition, in Sample 1, a transistor is provided in a pixel, the transistor having a gate electrode electrically connected to the scanning line 201, a semiconductor film 211 overlapping the gate electrode via a gate insulating film and formed through the same process as the common electrode 207, a source electrode electrically connected to the semiconductor film 211, electrically connected to the signal line 205, and a drain electrode 213 electrically connected to the pixel electrode 209.</p><p>17B shows a top view of Sample 2 which is one embodiment of the present invention. The pixel shown in Sample 2 is a region inside a scan line 221 extending in the horizontal direction and a signal line 225 extending in the vertical direction. The size of one pixel is 84 μm in length and 28 μm in width.</p><p>Sample 2 has a pixel electrode 229 arranged inside a region surrounded by the above-mentioned wiring, the signal lines of horizontally adjacent pixels, and the scan lines of vertically adjacent pixels, and a common electrode 227 arranged on the pixel electrode 229. The common electrode 227 extends in a striped shape in a direction intersecting with the signal line 225. In Sample 2, a transistor is provided in a pixel, the transistor including a gate electrode electrically connected to the scan line 221, a semiconductor film 231 overlapping the gate electrode via a gate insulating film and formed through the same process as the pixel electrode 229, a source electrode electrically connected to the semiconductor film 231 and electrically connected to the signal line 225, and a drain electrode 233 electrically connected to the pixel electrode 229. Note that the cross-sectional shape of the transistor can be referred to the transistor 102 shown in Embodiment 2 and FIG. 5.</p><p>In this manner, samples 1 and 2 were prepared. In the pixels shown in samples 1 and 2, the transmittance of the liquid crystal can be controlled by a lateral electric field applied between the pixel electrode and the common electrode.</p><p>Next, the transmittance of Sample 1 and Sample 2 was calculated. The calculation was performed in FEM-Static mode using LCD Master 3-D manufactured by Shintech. In the calculation, the size was 84 μm in length, 28 μm in width, and 4 μm in depth (height), and the boundary condition was periodic. The thickness of the gate electrode was 200 nm, the thickness of the gate insulating film was 400 nm, the thickness of the signal line was 300 nm, and the thickness of the interlayer insulating film was 500 nm. In addition, in Sample 1, the thickness of the common electrode was 0 nm, the thickness of the nitride insulating film between the common electrode and the pixel electrode was 100 nm, and the thickness of the pixel electrode was 100 nm. In addition, in Sample 2, the thickness of the pixel electrode was 0 nm, the thickness of the nitride insulating film between the pixel electrode and the common electrode was 100 nm, and the thickness of the common electrode was 100 nm. In addition, the rubbing direction of the liquid crystal was 85°, the twist angle was 0°, and the pretilt angle was 3°. In order to reduce the calculation load, the thickness of the common electrode of Sample 1 and the pixel electrode of Sample 2 was set to 0 nm. Under these conditions, the transmittance distribution was evaluated when applying -9 V to the scan line, 0 V to the common line, and 6 V to the signal line and pixel electrode.</p><p>The transmittance distribution is expressed in gray scale, with whiter indicating higher transmittance. The transmittance distribution of sample 1 is shown in Figure 17(C), and the transmittance distribution of sample 2 is shown in Figure 17(D).</p><p>It was found that a region with high transmittance was formed in Sample 1 and Sample 2. In particular, it was found that a region with high transmittance was formed over a wide range within a pixel in Sample 2.</p><p>This is because the common electrode formed in sample 2 does not have a region extending in a direction parallel to the signal line, and the region in which an electric field is generated between the pixel electrode and the common electrode in sample 2 is larger than that in sample 1.</p><p>Therefore, it is clear that Sample 2 has an effective structure for fabricating a liquid crystal display device with low power consumption.</p>

<p>In this example, light leakage in a black display region when white and black are displayed in adjacent pixels of a liquid crystal display device according to one embodiment of the present invention was evaluated by calculation.</p><p>First, the samples used in this example will be described.</p><p>18A shows a top view of sample 3. The pixel shown in sample 3 is a region inside a scanning line 241 extending in the horizontal direction and a signal line 243 extending in the vertical direction. The combined size of two horizontally adjacent pixels is 49.5 μm vertically and 30 μm horizontally.</p><p>Sample 3 has a pixel electrode 249 disposed inside a region surrounded by the above-mentioned wiring, the signal lines of horizontally adjacent pixels, and the scan lines of vertically adjacent pixels, and a common electrode 247 disposed on the pixel electrode 249. Note that the common electrode 247 extends in a striped shape in a direction intersecting with the signal line 243. In Sample 3, a transistor is provided in a pixel, the transistor including a gate electrode electrically connected to the scan line 241, a semiconductor film 251 overlapping the gate electrode via a gate insulating film and formed through the same process as the pixel electrode 249, a source electrode electrically connected to the semiconductor film 251 and electrically connected to the signal line 243, and a drain electrode 253 electrically connected to the pixel electrode. Note that the cross-sectional shape of the transistor can be referred to the transistor 102 shown in Embodiment 2 and FIG. 5.</p><p>18B shows a top view of Sample 4. Sample 4 has a similar structure to Sample 3, but the shapes of the drain electrode and the common electrode are different. Specifically, in Sample 4, the drain electrode 263 is L-shaped and has a region overlapping with an end of the pixel electrode 249, thereby suppressing the influence of the electric field between the scan line 241 and the pixel electrode 249. Similarly, the common electrode 267 is shaped to straddle the scan line 241 and connect to adjacent pixels in the vertical direction, thereby suppressing the influence of the electric field between the scan line 241 and the pixel electrode 249.</p><p>In this manner, samples 3 and 4 were prepared. In the pixels shown in samples 3 and 4, the transmittance of the liquid crystal element can be controlled by a lateral electric field applied between the pixel electrode and the common electrode.</p><p>Next, the transmittance of Sample 3 and Sample 4 was calculated. The calculation was performed in FEM-Static mode using LCD Master 3-D manufactured by Shintech. In the calculation, the size was set to 49.5 μm in length, 30 μm in width, and 4 μm in depth (height), and the boundary condition was set to periodic. In addition, the thickness of the gate electrode was set to 200 nm, the thickness of the gate insulating film was set to 400 nm, the thickness of the pixel electrode was set to 0 nm, the thickness of the signal line was set to 300 nm, the thickness of the interlayer insulating film was set to 500 nm, and the thickness of the common electrode was set to 100 nm. In addition, the rubbing direction of the liquid crystal was set to 90°, the twist angle was set to 0°, and the pretilt angle was set to 3°. In order to reduce the load of the calculation, the thickness of the pixel electrode was set to 0 nm. Under these conditions, with -9V applied to the scan line and 0V applied to the common line, 6V was applied to the signal line and pixel electrode of the left pixel, and 0V was applied to the signal line and pixel electrode of the right pixel, and the transmittance distribution was evaluated.</p><p>The transmittance distribution is expressed in gray scale, with whiter indicating higher transmittance. The transmittance distribution of sample 3 is shown in Figure 18(C), and the transmittance distribution of sample 4 is shown in Figure 18(D).</p><p>In Samples 3 and 4, white display was observed in the left pixel and black display was observed in the right pixel.</p><p>Furthermore, some areas of high transmittance (light leakage) were observed in the black display of Sample 3. On the other hand, no areas of high transmittance were observed throughout the entire pixel in the black display of Sample 4. In Sample 4, the drain electrode 263 is L-shaped and has an area overlapping with the end of the pixel electrode 249, which makes it difficult for an electric field to be generated between the scanning line and the pixel electrode compared to Sample 3, and reduces light leakage in the black display.</p><p>Therefore, it is clear that sample 4 has an effective structure for producing a liquid crystal display device with high contrast.</p>