Display device
10 claims: 8 independent, 2 dependent
- 1第1のトランジスタと、第2のトランジスタと、容量素子と、を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置されている、表示装置。
- 2第1のトランジスタと、第2のトランジスタと、容量素子と、を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第1のチャネル形成領域を有する半導体膜は、平面視において曲がった形状の第1の領域を有し、前記複数の第1のチャネル形成領域の一は、前記第1の領域を介して、前記複数の第1のチャネル形成領域の他の一と電気的に接続され、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置されている、表示装置。
- 3第1のトランジスタと、第2のトランジスタと、容量素子と、 発光素子と、 を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置され、前記複数の第1のチャネル形成領域を有する半導体膜は、前記第1の配線と同じ材料を有する導電膜を介して前記発光素子と電気的に接続され、平面視において、前記第1の配線は、前記導電膜と前記第2の配線との間に位置する領域を有する、表示装置。
- 4第1のトランジスタと、第2のトランジスタと、容量素子と、 発光素子と、 を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第1のチャネル形成領域を有する半導体膜は、平面視において曲がった形状の第1の領域を有し、前記複数の第1のチャネル形成領域の一は、前記第1の領域を介して、前記複数の第1のチャネル形成領域の他の一と電気的に接続され、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置され、前記半導体膜は、前記第1の配線と同じ材料を有する導電膜を介して前記発光素子と電気的に接続され、平面視において、前記第1の配線は、前記導電膜と前記第2の配線との間に位置する領域を有する、表示装置。
- 5第1のトランジスタと、第2のトランジスタと、容量素子と、を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置され、前記容量素子の一方の電極は、前記第1のトランジスタ及び前記第2のトランジスタと電気的に接続され、前記容量素子の一方の電極は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有する、表示装置。
- 6第1のトランジスタと、第2のトランジスタと、容量素子と、を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第1のチャネル形成領域を有する半導体膜は、平面視において曲がった形状の第1の領域を有し、前記複数の第1のチャネル形成領域の一は、前記第1の領域を介して、前記複数の第1のチャネル形成領域の他の一と電気的に接続され、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置され、前記容量素子の一方の電極は、前記第1のトランジスタ及び前記第2のトランジスタと電気的に接続され、前記容量素子の一方の電極は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有する、表示装置。
- 7第1のトランジスタと、第2のトランジスタと、容量素子と、 発光素子と、 を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置され、前記容量素子の一方の電極は、前記第1のトランジスタ及び前記第2のトランジスタと電気的に接続され、前記容量素子の一方の電極は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第1のチャネル形成領域を有する半導体膜は、前記第1の配線と同じ材料を有する導電膜を介して前記発光素子と電気的に接続され、平面視において、前記第1の配線は、前記導電膜と前記第2の配線との間に位置する領域を有する、表示装置。
- 8第1のトランジスタと、第2のトランジスタと、容量素子と、 発光素子と、 を画素に有する表示装置であって、平面視において、第1の方向に延伸した領域を有する第1の配線と、平面視において、前記第1の方向に延伸した領域を有する第2の配線と、を有し、 前記第1の配線は、電源供給線としての機能を有し、 前記第2の配線は、ソース信号線としての機能を有し、 前記第1の配線の配線幅は、前記第2の配線の配線幅よりも大きく、前記第1のトランジスタは、複数の第1のチャネル形成領域を有し、前記第2のトランジスタは、複数の第2のチャネル形成領域を有し、前記複数の第1のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第2のチャネル形成領域は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記複数の第1のチャネル形成領域を有する半導体膜は、平面視において曲がった形状の第1の領域を有し、前記複数の第1のチャネル形成領域の一は、前記第1の領域を介して、前記複数の第1のチャネル形成領域の他の一と電気的に接続され、前記第1のトランジスタと前記第2のトランジスタとは、前記複数の第1のチャネル形成領域の少なくとも一のチャネル長方向が、前記複数の第2のチャネル形成領域のチャネル長方向と交差するように配置され、前記容量素子の一方の電極は、前記第1のトランジスタ及び前記第2のトランジスタと電気的に接続され、前記容量素子の一方の電極は、前記第1の配線の下方に設けられ、且つ、前記第1の配線と重なりを有し、前記半導体膜は、前記第1の配線と同じ材料を有する導電膜を介して前記発光素子と電気的に接続され、平面視において、前記第1の配線は、前記導電膜と前記第2の配線との間に位置する領域を有する、表示装置。
- 9請求項1又は5において、前記複数の第1のチャネル形成領域を有する半導体膜は、平面視において曲がった形状を有する、表示装置。
- 10請求項2、3、4、6、7、8、又は9において、前記半導体膜は、多結晶珪素を有する、表示装置。
Independent claims10
311 paragraphs, as filed
The present invention relates to an active matrix display device and a semiconductor device in which elements are arranged in a matrix.
2. Description of the Related Art Conventionally, liquid crystal display devices, electroluminescence (hereinafter referred to as "EL") display devices, and the like are known as image display devices. Types of these display devices include a passive matrix type and an active matrix type. An active matrix display device is characterized by being able to operate at high speed even when the number of pixels is increased.
In the active matrix display device, TFTs, capacitive elements, wiring, pixel electrodes, etc. are formed on the same substrate, so the aperture ratio tends to decrease. Therefore, attempts have been made to increase the aperture ratio by devising designs such as the materials, shapes, numbers, and arrangements of these elements. For example, Patent Document 1 discloses a method of reducing the area of a capacitor by using tantalum oxide, which has a high dielectric constant, as the dielectric of the capacitor.
<p><patcit num="1"><text>JP-A-11-312808</text></patcit></p>
<p>On the other hand, the method of using a material with a high relative dielectric constant for the capacitive element in order to increase the aperture ratio has the problem of increasing the number of steps.</p><p>Here, in order to increase the aperture ratio without increasing the number of steps, the area of the aperture should be increased. However, if an attempt is made to provide an opening between wirings in order to increase the area of the opening, the shape of the opening becomes complicated. In addition, in the EL display device, if the shape of the opening is complicated, the length of the edge (edge) of the opening becomes long, which causes a problem that the shrinkage of the EL light-emitting portion is accelerated. end up</p><p>Here, the shrinkage of the EL light-emitting portion does not mean that the EL layer physically shrinks, but that the effective area of the EL element (the area where the EL element emits light) gradually shrinks from the edge. It means the state of going.</p><p>Also in semiconductor devices (for example, DRAMs) other than display devices, it is desirable to increase the area of elements connected to transistors.</p><p>Accordingly, an object of the present invention is to provide a display device (or a semiconductor device having a large element area) with a high aperture ratio.</p>
<p>In this specification, a TFT channel formation region refers to a semiconductor region arranged below a gate electrode with a gate insulating film interposed therebetween. Further, the channel length refers to the length in the direction in which carriers flow in the channel formation region. The channel width means the length of the channel formation region in the direction perpendicular to the channel length direction.</p><p>In the case of a TFT with a multi-gate structure, the channel length and channel width refer to the dimensions of each channel formation region.</p><p>A multi-gate structure is a structure in which a plurality of channel formation regions are provided in one TFT. On the other hand, the single gate structure is a structure in which one TFT is provided with one channel formation region.</p><p>Further, the display device of the present invention has a wiring provided between adjacent pixel electrodes and a thin film transistor, and a channel forming region of the thin film transistor is provided below the wiring. The region is provided at a position overlapping with the wiring, and the direction of the channel width of the channel forming region is parallel to the direction of current flow in the wiring.</p><p>A display device of the present invention includes a wiring provided between adjacent pixel electrodes and a thin film transistor having a plurality of channel formation regions, and the plurality of channel formation regions are provided below the wiring. The plurality of channel formation regions are provided at positions overlapping with the wiring, and the direction of the channel width of the plurality of channel formation regions is parallel to the direction of current flow in the wiring. do.</p><p>The display device of the present invention includes a wiring provided between adjacent pixel electrodes and a thin film transistor, a channel forming region of the thin film transistor is provided below the wiring, and the channel forming region is The channel forming region is provided at a position overlapping with the wiring, and the direction of the channel width of the channel forming region is parallel to the longitudinal direction of the wiring.</p><p>A display device of the present invention includes a wiring provided between adjacent pixel electrodes and a thin film transistor having a plurality of channel formation regions, and the plurality of channel formation regions are provided below the wiring. and the plurality of channel forming regions are provided at positions overlapping with the wiring, and the direction of the channel width of the plurality of channel forming regions is parallel to the longitudinal direction of the wiring. and</p><p>The display device of the present invention includes a wiring provided between adjacent pixel electrodes and a thin film transistor, a channel forming region of the thin film transistor is provided below the wiring, and the channel forming region is The channel forming region is provided at a position overlapping with the wiring, and the direction of the channel width of the channel forming region is parallel to the longitudinal direction of the shape of the pixel electrode.</p><p>A display device of the present invention includes a wiring provided between adjacent pixel electrodes and a thin film transistor having a plurality of channel formation regions, and the plurality of channel formation regions are provided below the wiring. The plurality of channel formation regions are provided at positions overlapping with the wiring, and the channel width direction of the plurality of channel formation regions is parallel to the longitudinal direction of the shape of the pixel electrode. Characterized by</p><p>In the display device of the invention, the thin film transistor operates in a linear region.</p><p>Let Vgs be the voltage between the gate and source of the transistor, Vds be the voltage between the source and drain of the transistor, and Vth be the threshold voltage of the transistor. In this case, the linear region refers to a range in which the relational expression |Vgs-Vth|>|Vds| holds.</p><p>That is, the thin film transistor is characterized in that the voltage between the gate and the source (Vgs) is higher than the voltage between the source and the drain (Vds) by at least the threshold voltage (Vth).</p><p>In the display device of the present invention, the channel width of the channel forming region is larger than the channel length of the channel forming region.</p><p>In the display device of the present invention, the longitudinal direction of the shape of the impurity regions connecting the channel forming regions is parallel to the direction of the channel width.</p><p>In the display device of the present invention, the channel formation region is characterized by being an amorphous semiconductor or a polycrystalline semiconductor.</p><p>In the display device of the present invention, the channel formation region is made of single crystal.</p><p>In the display device of the present invention, the thin film transistor includes an island-shaped semiconductor layer, a gate insulating film, and a gate electrode, and the island-shaped semiconductor layer includes the plurality of channel formation regions and the plurality of impurity regions. , and a gate electrode is formed on the plurality of channel forming regions with a gate insulating film interposed therebetween.</p><p>In the display device of the present invention, the wiring is formed on the gate electrode with an interlayer insulating film interposed therebetween.</p><p>In the display device of the present invention, a first capacitor including the island-shaped semiconductor layer, the gate insulating film on the island-shaped semiconductor layer, and the gate electrode on the gate insulating film; and a second capacitor comprising an interlayer insulating film on the gate electrode and the wiring on the interlayer insulating film.</p><p>In the display device of the present invention, the longitudinal direction of the shape of the gate electrode is the direction of the channel width.</p><p>In the display device of the present invention, the wiring is formed below a partition wall (insulator) formed to cover the end of the pixel electrode.</p><p>In the display device of the present invention, one of the source terminal (region) and the drain terminal (region) of the thin film transistor is connected to one of the adjacent pixel electrodes.</p><p>In the display device of the present invention, the other of the source terminal (region) and the drain terminal (region) of the thin film transistor is connected to the wiring.</p><p>A semiconductor device of the present invention includes a wiring provided between adjacent electrodes and a thin film transistor, a channel forming region of the thin film transistor is provided below the wiring, and the channel forming region is provided below the wiring. The channel forming region is provided at a position overlapping with the wiring, and the direction of the channel width of the channel forming region is parallel to the direction of current flow in the wiring (or the longitudinal direction in the shape of the wiring). .</p><p>A semiconductor device of the present invention includes a wiring provided between adjacent electrodes and a thin film transistor, a channel forming region of the thin film transistor is provided below the wiring, and the channel forming region is provided below the wiring. It is characterized in that the channel width direction of the channel forming region is parallel to the longitudinal direction of the shape of the electrode.</p><p>A semiconductor device of the present invention includes a wiring provided between adjacent elements and a thin film transistor, a channel forming region of the thin film transistor is provided below the wiring, and the channel forming region is provided below the wiring. The channel forming region is provided at a position overlapping with the wiring, and the direction of the channel width of the channel forming region is parallel to the direction of current flow in the wiring (or the longitudinal direction in the shape of the wiring). .</p><p>A semiconductor device of the present invention includes a wiring provided between adjacent elements and a thin film transistor, a channel forming region of the thin film transistor is provided below the wiring, and the channel forming region is provided below the wiring. It is characterized in that the channel width direction of the channel forming region is provided in a position overlapping with the wiring, and the direction of the channel width is parallel to the longitudinal direction of the shape of the element.</p><p>In the semiconductor device of the present invention, the channel width of the channel formation region is longer than the channel length of the channel formation region.</p>
<p>According to the present invention, a display device with a high aperture ratio (or a semiconductor device with a large element area) can be realized.</p><p>Further, it is not necessary to complicate the shape of the pixel electrode (or the electrode of the element) in order to increase the aperture ratio.</p><p>Furthermore, by increasing the aperture ratio, the current density to the element is lowered, so that the life of the element can be extended.</p>
<figref num="1">Double gate structure layout 1</figref><figref num="2">Double gate structure layout 2</figref><figref num="3">pixel circuit diagram</figref><figref num="4">TFT fabrication flow (top view)</figref><figref num="5">Pixel electrode and wiring diagram (wiring shape: straight line)</figref><figref num="6">Diagram of pixel electrodes and wiring (wiring shape: zigzag)</figref><figref num="7">Diagram of pixel electrode and wiring (wiring shape: meander)</figref><figref num="8">Single-gate structure layout 1</figref><figref num="9">Single-gate structure layout 2</figref><figref num="10">Layout 1 with triple gate structure</figref><figref num="11">Layout 2 with triple gate structure</figref><figref num="12">Cross-sectional view of inorganic EL element 1</figref><figref num="13">Cross-sectional view of inorganic EL element 2</figref><figref num="14">Top view and cross-sectional view of display device</figref><figref num="15">DRAM circuit diagram</figref><figref num="16">DRAM layout</figref><figref num="17">Examples of electronic devices</figref>
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. Those skilled in the art will readily appreciate, however, that the present invention may be embodied in many different forms and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. be done. Therefore, it should not be construed as being limited to the contents described in this embodiment.
It should be noted that Embodiments 1 to 11 below can be combined as appropriate.
(Embodiment 1) In this embodiment, the pixel configuration and layout of the display device of the present invention will be described. Note that a pixel composed of two TFTs will be described here.
First, the pixel configuration of the display device of the present invention will be described with reference to FIG. The pixel has a TFT (driving TFT 301) connected to the pixel electrode, a capacitive element 300, a switching TFT 302, a display element 303, a scanning line 305, a signal line 304, and a power supply line 306. there is The driving TFT 301 and the switching TFT 302 have a double gate structure having two channel forming regions.
The driving TFT 301 may have a single-gate structure, or may have a multi-gate structure having three or more channel formation regions.
One of the source terminal and the drain terminal of the switching TFT 302 is connected to the signal line 304 .
A gate terminal of the switching TFT 302 is connected to the scanning line 305 .
The other of the source terminal and the drain terminal of the switching TFT 302 is electrically connected to one of the gate terminal of the driving TFT 301 and the electrode of the capacitive element.
One of the source terminal and the drain terminal of the driving TFT 301 is connected to the power supply line 306 .
The other of the source terminal and drain terminal of the driving TFT 301 is connected to the display element 303 .
A gate terminal of the driving TFT 301 is connected to one electrode of the capacitive element and the other of a source terminal or a drain terminal of the switching TFT 302 .
The other terminal of capacitive element 300 is electrically connected to power supply line 306 .
One terminal of the capacitive element 300 is electrically connected to the other of the gate terminal of the driving TFT and the source terminal or drain terminal of the switching TFT 302 .
Next, the layout of the pixel portion will be described with reference to FIGS. 1 and 2. FIG. FIG. 2 is a top view corresponding to FIG. 1, showing a stage where the first semiconductor layer 101, the second semiconductor layer 102, the gate wiring 105, and the gate electrode 100 are formed.
The correspondence relationship between FIGS. 1 and 2 and FIG. 3 will be described.
A portion surrounded by a dashed line portion 6001 corresponds to the TFT 301 for driving.
A portion surrounded by a dashed line portion 6011 corresponds to the switching TFT 302 .
A portion surrounded by a dashed line portion 6012 corresponds to the capacitive element 300. FIG.
A pixel electrode 107 corresponds to the pixel electrode of the display element 303 .
Signal line 104 corresponds to signal line 304 .
Power supply line 106 corresponds to power supply line 306 .
In FIG. 1, a first semiconductor layer 101 is an island semiconductor layer of a switching TFT.
A region overlapping with the gate wiring 105 is a channel forming region, a region connected to the signal line 104 is a source terminal (or drain terminal), and a region connected to the connection electrode 103 through a contact hole is a drain terminal (or source terminal). Note that the switching TFT has a double gate structure having two channel forming regions.
Note that the switching TFT may have a single-gate structure, or may have a multi-gate structure having three or more channel formation regions.
Also, the second semiconductor layer 102 is an island-shaped semiconductor layer of the driving TFT 301 that drives the display element. A region overlapping with the gate electrode 100 is a channel forming region. A gate electrode of the driving TFT 301 is connected to the connection electrode 103 through a contact hole. Furthermore, the source terminal (or drain terminal) of the driving TFT 301 and the power supply line 106 are connected via a contact hole. A drain terminal (or a source terminal) of the driving TFT 301 and the connection electrode 108 are connected through a contact hole. A pixel electrode 107 is formed in contact with the connection electrode 108 .
Also, in the second semiconductor layer 102, a power supply line 106 is arranged above the channel forming region overlapping the gate electrode 100 with the gate insulating film interposed therebetween. A capacitance formed between the gate electrode 100 and the power supply line 106 can be used as a storage capacitance of the display element.
An interlayer insulating film is sandwiched between the gate electrode 100 and the power supply line 106 .
In addition, the gate electrode 100 becomes one electrode of the capacitor, and the portion of the power supply line that overlaps with the gate electrode becomes the other electrode of the capacitor.
In addition, in order to prevent the electrodes of the display element from short-circuiting, the area other than the light emitting area is covered with a partition wall (insulator). The width of the partition provided between the adjacent left and right pixels is, for example, about 20 μm to 25 μm. In this embodiment, the signal line 104 and the power supply line 106 are arranged under the 20 μm-wide partition (that is, between adjacent pixel electrodes).
In this embodiment, the power supply line 106 is arranged so that the longitudinal direction of the pixel electrode (the longitudinal direction of the pixel electrode) is parallel to the longitudinal direction of the pixel electrode. Furthermore, a driving TFT is arranged under the power supply line 106 so as to overlap. Then, the direction of the channel width is arranged parallel to the longitudinal direction.
However, according to the present invention, it is not always necessary to arrange the power supply line 106 in parallel with the longitudinal direction of the shape of the pixel electrode and arrange the driving TFT 301 below the power supply line 106 .
Therefore, when the signal line 104 is arranged parallel to the longitudinal direction of the shape of the pixel electrode, the driving TFT 301 may be arranged so as to overlap the signal line 104 below.
In addition, the shape of the pixel electrode is square or substantially square (for example, a square with cutouts at the corners, or a square with rounded corners (all the corners need not be rounded). Only some corners may be rounded.), etc.), and if there is no longer direction such as a circle, it does not matter which of the power supply line 106 or the signal line 104 the driving TFT 301 is arranged. no.
The shape of the pixel electrode may be a rectangle or a substantially rectangular shape (for example, a rectangular shape with cutouts at the corners, or a rectangular shape with rounded corners (all corners are rounded). Only some corners may be rounded.)), elliptical, polygonal, nearly polygonal (for example, a shape with notches in the corners of a polygon, or a shape with polygonal corners Various shapes such as a rounded shape (all corners do not need to be rounded; only some corners may be rounded) are conceivable. Note that the shape of the pixel electrode is not limited to these illustrated shapes. It should be noted that when the shape of the pixel electrode is rectangular or substantially rectangular, wiring lines can be easily arranged in a grid pattern, which facilitates layout design, which is preferable.
Also, the size of the pixel electrode may be different for each pixel. Furthermore, the shape of the pixel electrode may be different for each pixel.
Further, when the length of the required channel width is shorter than the length in the short direction of the shape of the pixel electrode, the driving TFT 301 may be arranged so as to overlap under the wiring arranged in parallel with the short direction. good.
Also, a part of the power supply line 106 may be arranged above or below the pixel electrode. In such an arrangement, the gate electrode of the driving TFT 301 is arranged so as to partially overlap the power supply line 106 .
Note that the direction of the channel width of the driving TFT 301 is parallel to the longitudinal direction of the shape of the wiring (the longitudinal direction of the wiring). This is because it is possible to increase the length of the channel width. In addition, since the wiring is arranged between the adjacent pixel electrodes, the long direction of the wiring (the long direction of the wiring) is parallel to the long direction or the short direction of the pixel electrodes, thereby increasing the aperture ratio. can be raised.
Note that the direction of the channel width can be said to be parallel to the direction in which current flows in the wiring arranged above the channel forming region, since the current normally flows in the longitudinal direction of the wiring.
Further, in this embodiment, the operation is performed in a linear region. Assuming that the channel length is L and the channel width is W, the driving TFT has a double gate structure where L<W. Here, the driving TFT has a double gate structure with L=7 μm and W=20 μm. Then, when laying out the pixels, by arranging the wiring under the 20 μm-wide partition wall and arranging the driving TFT under the wiring, the aperture ratio can be increased even if the size of the driving TFT is increased. can be done.
In the present embodiment, the semiconductor layer is patterned so as to be bent in a U shape with respect to the gate electrode 100 (broken line portion 6001 in FIGS. 1 and 2). As a result, the direction of the channel width can be arranged parallel to the longitudinal direction of the shape of the pixel electrode (arrow 7001 in FIGS. 1 and 2).
Note that it is preferable that the longitudinal direction of the shape of the impurity regions connecting the channel formation regions is parallel to the direction of the channel width. This is because a TFT of as large a size as possible can be arranged in a narrow space between pixel electrodes (a space between adjacent pixel electrodes), so that an increase in aperture ratio can be expected. Furthermore, since current flows in the impurity region in the longitudinal direction of the shape of the impurity region, the resistance value of the impurity region can be increased. Therefore, off current can be reduced.
However, according to the present invention, if the direction of the channel width is perpendicular to the longitudinal direction of the pixel electrode, the channel width can be increased by the length of the longitudinal direction. Therefore, the shape of the island-shaped semiconductor layer of the TFT is not limited to the U-shape as in the present embodiment.
Note that the capacitive element 300 includes the second semiconductor layer 102, the gate electrode 100, a gate insulating film (first storage capacitor) formed between the second semiconductor layer 102 and the gate electrode 100, and the gate electrode 100. 100 , a power supply line 106 , and an interlayer insulating film (second storage capacitor) formed between the gate electrode 100 and the power supply line 106 .
In this case, in the dashed line portion 6012, the storage capacitor is formed by the gate electrode 100, the second semiconductor layer 102, and the gate insulating film formed between the semiconductor layer 102 of the gate electrode 2. Become. Therefore, by increasing the area of the gate electrode in the dashed line portion 6012, the size of the storage capacitor can also be increased.
With the above configuration, a TFT of as large a size as possible (especially a TFT of a size having a large channel width) can be arranged in a narrow space between pixel electrodes (a space between adjacent pixel electrodes). Therefore, it is possible to increase the aperture ratio.
Since the size of the TFT is very small, there is a problem that the electrical characteristics are likely to vary due to variations in the film thickness or quality of the gate insulating film, variations in the implantation dose during ion doping, and the like.
In particular, when amorphous silicon, microcrystalline silicon, or polycrystalline silicon is used as a TFT semiconductor, characteristics of the TFT (for example, on-current, off-current, threshold voltage, mobility, etc.) due to the crystallinity of the semiconductor variation occurs. In particular, when the characteristics of the TFTs connected to the pixels vary, the current (or voltage) supplied to the pixels varies, resulting in a problem of poor visibility of the display device.
Therefore, in order to solve the above problem, there is a method of adopting a multi-gate structure, but a TFT with a multi-gate structure has a larger area than a TFT with a single gate structure. Therefore, if a TFT with a multi-gate structure is adopted in order to reduce variations in the electrical characteristics of the TFT, the aperture ratio will decrease. However, by applying the configuration of the present invention, it is possible to achieve both a reduction in variation in TFT characteristics and an increase in aperture ratio.
Here, in the present embodiment, an example of the so-called constant-voltage driving method that operates the driving TFT in the linear region has been described. Therefore, the constant voltage driving method will be described below.
A TFT may be operated in a saturation region or in a linear region. Let Vgs be the voltage between the gate and source of the transistor, Vds be the voltage between the source and drain of the transistor, and Vth be the threshold voltage of the transistor. In this case, the saturation region refers to a range in which the relational expression |VgsVth|<|Vds| holds true. On the other hand, the linear region is a range in which the relational expression |Vgs-Vth|>|Vds| holds.
A constant current driving method is a method in which a TFT connected to a pixel electrode of an EL element (hereinafter referred to as a "driving TFT") is operated in a saturation region to cause a constant current to flow through the display element.
The constant-current driving method can keep a constant current flowing through the EL element, so that variations due to deterioration of the display element can be reduced. However, in the constant current driving method, when the driving TFT deteriorates, the current flowing through the driving TFT also decreases. Therefore, variations in TFT tend to affect variations in luminance of display elements.
On the other hand, a method of applying a constant voltage to the EL element by operating the driving TFT in the linear region is called a constant voltage driving method.
Since the constant voltage drive system operates in the linear region, the voltage between the source and the drain can be made lower than the voltage between both electrodes of the display element. Therefore, it is possible to reduce the influence of variations in driving TFTs on the current flowing through the EL element. Therefore, variations in deterioration of TFTs are less likely to affect variations in luminance of display elements.
However, even if the driving TFT is operated in the linear region, if amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc. are used as the semiconductor layer of the TFT, the effect of crystallinity variation within the substrate plane can be ignored. Can not do it.
Therefore, in order to suppress variations in driving TFTs, it is preferable to increase the area of the channel formation region of the driving TFTs. That is, it is preferable to increase the channel length and channel width.
Also, the longer the channel width, the lower the voltage between the source and the drain. Furthermore, the shorter the channel length, the lower the voltage between the source and the drain. Therefore, the channel width is preferably longer than the channel length.
Therefore, when the TFT is operated in the linear region, it is preferable to increase the channel width in order to increase the area of the channel forming region of the driving TFT.
Here, in general, increasing the area of the channel forming region tends to decrease the aperture ratio of the display device. In other words, when attempts are made to reduce variations in TFT characteristics, the aperture ratio decreases. That is, in general, it is very difficult to simultaneously achieve both a reduction in variation in TFT characteristics and an increase in aperture ratio. This is particularly noticeable when the area of the channel formation region of the multi-gate structure TFT is increased as in the present embodiment.
However, by applying the configuration of this embodiment, it is possible to simultaneously achieve both a reduction in variation in TFT characteristics and an increase in aperture ratio.
Also, increasing the aperture ratio reduces power consumption and improves the reliability of the display element. That is, when a certain brightness is required, the required brightness can be obtained with a small current (or voltage) if the aperture ratio is large. This is because if the current (or voltage) supplied to the display element is small, the degradation rate of the display element is reduced.
In addition, the deterioration rate of display elements also varies from display element to display element. Therefore, when the deterioration rate of the display element is reduced by increasing the aperture ratio, the variation in luminance deterioration of the display element can also be reduced. Therefore, the visibility of the display device can be improved by the synergistic effect of the reduction in variation in TFT characteristics and the reduction in variation due to an increase in aperture ratio.
Note that a TFT with a multi-gate structure can reduce the off current of the TFT. Therefore, it is preferable to employ a multi-gate structure TFT regardless of whether the semiconductor of the TFT is non-single-crystal or single-crystal.
Further, as in the present embodiment, both the driving transistor and the switching transistor connected to the driving transistor are arranged below the wiring (signal line or power supply line), and the direction of the channel length of the switching transistor and the The aperture ratio can be increased by arranging the channel length direction of the drive transistor in the vertical direction and setting the channel width direction of the drive transistor to the direction of current flow in the wiring.
(Embodiment 2) In the present embodiment, the significance of "longitudinal direction in the shape of wiring (longitudinal direction of wiring)" will be specifically described with reference to FIGS.
The longitudinal direction in the shape of the wiring (channel width direction) is the direction parallel to the direction in which the current flows in the wiring arranged above the (described above) channel forming region. In the case of zigzag-shaped or meander-shaped wiring, which will be described later, current does not necessarily flow in a straight line in the wiring. In this case, the ``long direction of the wiring shape'' (the ``channel width direction'') is defined as ``the direction substantially parallel to the direction in which current flows in the wiring region disposed above the channel forming region''.
Here, the shape of the wiring does not necessarily have to be straight as shown in FIG. For example, as shown in FIG. 6, the first wirings 501 and 502 may have a zigzag shape. Also, as shown in FIG. 7, the first wirings 501 and 502 may have a meandering shape.
5, 6, and 7 are schematic diagrams showing the arrangement of wirings and pixel electrodes. Therefore, the TFT is not shown. 501 to 504 are first wirings, 601 and 602 are second wirings, and 701 to 707 are pixel electrodes. One of the first wiring and the second wiring is a source signal line, and the other is a power supply line.
A zigzag shape is a shape in which a straight line is bent left and right many times. In addition, meander has the meaning of "winding and flowing".
And the meandering shape means such a shape.
Then, as shown in FIG. 5, when the first wirings 501 to 504 and the second wiring 601 have a linear shape, the "longitudinal direction of the wiring shape (first arrow 8001 in FIG. 5)" is a direction parallel to the direction in which current flows in the first wiring arranged above the channel forming region (the first arrow 8001 in FIG. 5).
If the wiring has a zigzag shape as shown in FIG. 6, the TFT is arranged under the first wiring region 5001 in FIG. 6, for example. In this case, the longitudinal direction in the shape of the wiring (second arrow 8002 in FIG. 6) is the direction in which current flows in the wiring arranged above the channel forming region (second arrow 8002 in FIG. 6). in the direction parallel to
On the other hand, for example, when a TFT is arranged under the second wiring region 5002 in FIG. It is a direction parallel to the direction in which the current flows in the connected wiring (the third arrow 8003 in FIG. 6).
Also, even if the wiring has a meandering shape as shown in FIG. 7, the current flows along the shape of the wiring. Therefore, there is a portion where the current flows in a direction that is not parallel to the longitudinal direction of the wiring. However, electrons eventually flow in a direction parallel to the longitudinal direction of the wiring (fourth arrow 8004 in FIG. 7). Therefore, when the wiring has such a shape, the direction of the channel width is defined as "the direction substantially parallel to the direction in which the current flows in the wiring region arranged above the channel forming region" or "the longitudinal direction of the wiring shape." parallel direction.
With the above configuration, wiring can be arranged in a narrow space between pixel electrodes (a space between adjacent pixel electrodes). In addition, a TFT of as large a size as possible (in particular, a TFT with a large channel width) can be arranged under the wiring. Therefore, it is possible to increase the aperture ratio.
(Embodiment 3) In this embodiment, another variation of the layout of the driving transistor of the present invention is illustrated. Note that the present invention is not limited to the layouts exemplified in this embodiment.
FIG. 8 is a layout of a single gate structure. The first semiconductor layer 101 is an island semiconductor layer of a switching TFT. A region overlapping with the gate wiring 105 is a channel formation region, a region connected to the signal line 104 through a contact hole is a source terminal (or drain terminal), and a region connected to the connection electrode 103 is a drain terminal (or source terminal).
Also, the second semiconductor layer 102 is an island-shaped semiconductor layer of the driving TFT 301 that drives the display element. A region overlapping with the gate electrode 100 is a channel forming region. A gate electrode of the driving TFT 301 is connected to the connection electrode 103 through a contact hole. Further, the source terminal (or drain terminal) of the driving TFT 301 and the power supply line 106 are connected. A drain terminal (or a source terminal) of the driving TFT 301 and the connection electrode 108 are connected through a contact hole. A pixel electrode 107 is formed in contact with the connection electrode 108 .
Note that the correspondence relationship between FIG. 8 and FIG. 3 is as follows.
A portion surrounded by a dashed line portion 6002 corresponds to the TFT 301 for driving.
A portion surrounded by a dashed line portion 6021 corresponds to the switching TFT 302 .
A portion surrounded by a dashed line portion 6022 corresponds to the capacitive element 300. FIG.
A pixel electrode 107 corresponds to the pixel electrode of the display element 303 .
Signal line 104 corresponds to signal line 304 .
Power supply line 106 corresponds to power supply line 306 .
FIG. 9 is a top view corresponding to FIG. 8, showing a stage where the first semiconductor layer 101, the second semiconductor layer 102, the gate wiring 105, and the gate electrode 100 are formed.
Then, patterning is performed so that the impurity region of the semiconductor layer is parallel to the longitudinal direction of the pixel electrode (or the direction in which current flows in the wiring, or the longitudinal direction in the shape of the wiring). 6002). As a result, the direction of the channel width can be arranged parallel to the longitudinal direction of the shape of the pixel electrode (arrow 7002 in FIGS. 8 and 9).
FIG. 10 is a layout of a triple gate structure. The first semiconductor layer 101 is an island semiconductor layer of a switching TFT. A region overlapping with the gate wiring 105 is a channel formation region, a region connected to the signal line 104 is a source terminal (or drain terminal), and a region connected to the connection electrode 103 through a contact hole is a drain terminal (or source terminal).
Also, the second semiconductor layer 102 is an island-shaped semiconductor layer of the driving TFT 301 that drives the display element. A region overlapping with the gate electrode 100 is a channel formation region. A gate electrode of the driving TFT 301 is connected to the connection electrode 103 . Furthermore, the source terminal (or drain terminal) of the driving TFT 301 and the power supply line 106 are connected via a contact hole. A drain terminal (or a source terminal) of the driving TFT 301 and the connection electrode 108 are connected through a contact hole. A pixel electrode 107 is formed in contact with the connection electrode 108 .
Note that the correspondence relationship between FIG. 10 and FIG. 3 is as follows.
A portion surrounded by a dashed line portion 6003 corresponds to the TFT 301 for driving.
A portion surrounded by a dashed line portion 6031 corresponds to the switching TFT 302 .
A portion surrounded by a dashed line portion 6032 corresponds to the capacitive element 300. FIG.
A pixel electrode 107 corresponds to the pixel electrode of the display element 303 .
Signal line 104 corresponds to signal line 304 .
Power supply line 106 corresponds to power supply line 306 .
Also, FIG. 11 is a top view corresponding to FIG. 10, and shows a stage in which the first semiconductor layer 101, the second semiconductor layer 102, the gate wiring 105, and the gate electrode 100 are formed.
Then, patterning is performed so that the impurity region of the semiconductor layer is parallel to the longitudinal direction of the pixel electrode (or the direction in which the current flows in the wiring, or the longitudinal direction of the wiring shape) (for example, an S shape). (FIGS. 10 and 11 dashed line portion 6003). As a result, the direction of the channel width can be arranged parallel to the longitudinal direction of the shape of the pixel electrode (arrow 7003 in FIGS. 10 and 11).
In this embodiment, the layout of a TFT having one or three channel forming regions has been described. Further, in Embodiment 1, the layout of the TFT having two channel forming regions has been described. However, the configuration of the present invention is not limited to the configurations of these embodiments, and can also be applied to TFTs having four or more channel forming regions.
(Embodiment 4) The present invention is not limited to pixels composed of two TFTs. In the case of a pixel configuration having a driving TFT with a double gate structure where L<W, it can be used as appropriate to improve the aperture ratio, simplify the shape of the aperture, and increase the length of the channel width. can.
(Embodiment 5) In this embodiment, a manufacturing process of a display device will be described. Note that only the pixel portion will be described in the description, but the manufacturing process of the driver circuit portion is not limited to this, and the description is omitted here.
As shown in FIG. 4A, a base film made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a substrate made of glass such as barium borosilicate glass or aluminoborosilicate glass. After that, a semiconductor film having an amorphous structure is crystallized using a laser crystallization method or a known thermal crystallization method, and the crystalline semiconductor film is patterned into a desired shape to obtain island-shaped semiconductor layers 4101 and 4102 . Note that the base film and the semiconductor film can be formed by a known film formation method (eg, CVD method, PVD method, etc.).
Here, a polycrystalline silicon film was used by crystallizing the semiconductor film. However, the present invention may use amorphous silicon or microcrystalline silicon. Alternatively, single crystal silicon may be used.
When using single-crystal silicon, an SOI substrate (Silicon On Insulator substrate) or the like having a thin single-crystal silicon layer disposed on the substrate may be used.
Here, by adding an impurity to the first region of the island-shaped semiconductor layer 4101, which will be the first capacitor portion, the first region can function as the first electrode of the first capacitor. Here, boron, which imparts p-type conductivity, is implanted by an ion doping method. Impurities that impart n-type conductivity may be implanted. Phosphorus, arsenic, and the like are examples of impurities that impart n-type conductivity. Note that a known method (eg, ion doping method, ion shower method, etc.) can be used for adding impurities.
Next, a gate insulating film covering the island-shaped semiconductor layers 4101 and 4102 is formed. After that, an element selected from Ta, W, Ti, Mo, Al, Cu, etc., or an alloy material or compound material containing the element as a main component is used to form a conductive film for forming a gate electrode. After that, patterning is performed in a desired shape to obtain gate electrodes 4103 and 4104 (4104 also serves as a scanning line) (FIG. 4(B)).
Next, by adding impurities to the impurity regions of the island-shaped semiconductor layers 4101 and 4102, source regions, drain regions, and channel regions are formed. Here, boron, which imparts p-type conductivity, is implanted by an ion doping method in order to form a p-channel transistor.
When forming an n-channel transistor, an impurity imparting n-type conductivity may be implanted. Phosphorus, arsenic, and the like are examples of impurities that impart n-type conductivity. Note that a known method (eg, ion doping method, ion shower method, etc.) can be used for adding impurities. Also, an LDD region may be formed in a portion in contact with the channel forming region.
Next, annealing is performed to activate the added impurities. As the annealing method, known techniques such as furnace annealing and laser annealing may be used. In order to protect the gate insulating film before annealing, a passivation film (for example, silicon oxide or the like) may be formed by a known method (for example, CVD method, PVD method, or the like).
Next, an interlayer insulating film is formed. The interlayer insulating film may be an organic insulating film or an inorganic insulating film. Organic insulating films include acryl, polyimide, siloxane, and the like. As a method for forming the organic insulating film, a known method (spin coating method, dipping method, etc.) can be used. In addition, examples of the inorganic insulating film include silicon oxide and silicon nitride. It may be formed by a known method (for example, CVD method, PVD method, etc.). Note that the use of a material with a high dielectric constant such as silicon nitride can increase the capacity. On the other hand, planarization is possible when an organic insulating film is used.
Note that the interlayer insulating film may be planarized by a known technique (for example, CMP method).
Next, as shown in FIG. 4C, contact holes 4105 reaching the island-shaped semiconductor layers 4101 and 4102 and gate electrodes 4103 and 4104 are formed, and wirings 4106, 4107 and 4108 (4106 is the source signal line, 4107 is the A power supply line) and an electrode 4110 are formed.
Next, as shown in FIG. 4(D), a pixel electrode 4109 is formed. Indium tin oxide (commonly called ITO) and the like are typical materials for pixel electrodes. The pixel electrode 4109 also obtains a desired shape by patterning after forming a film made of the above material. Here, the electrode 4110 and the pixel electrode 4109 are in contact with each other through the contact hole 4105 .
Next, a partition is formed between adjacent pixels, and a portion to be a light emitting area is opened by patterning. After that, an EL layer is formed in the opening.
In this embodiment, a method for manufacturing a top-gate TFT has been described. However, the present invention is also applicable to bottom-gate TFTs.
(Embodiment 6) In this embodiment, an example of the appearance of a light-emitting display panel will be described with reference to FIG. FIG. 14(A) is a top view of a panel in which the space between the first substrate and the second substrate is sealed with a first sealant 1205 and a second sealant 1206, and FIG. ) correspond to cross-sectional views taken along lines AA and BB of FIG. 14(A).
FIG. 14A shows a pixel portion 1202, a monitor element portion 1230, and a scanning line driver circuit 1203 (gate line driver circuit) indicated by dotted lines. In this embodiment mode, the pixel portion 1202 and the scanning line driver circuit 1203 are in a region sealed with the first sealant and the second sealant. A signal line (source line) driving circuit 1201 is provided on the first substrate 1200 . As the first sealing material, it is preferable to use a highly viscous epoxy resin containing a filler. In addition, it is preferable to use a low-viscosity epoxy-based resin as the second sealing material. In addition, it is desirable that the first sealant 1205 and the second sealant 1206 be made of a material that does not transmit moisture and oxygen as much as possible.
A desiccant may be provided between the pixel portion 1202 and the first sealant 1205 . Furthermore, a desiccant may be provided over the scanning line or the signal line in the pixel portion. As a desiccant, water (H<sub>2</sub>It is preferable to use a substance that adsorbs O). However, it is not limited to this, and a substance that adsorbs water by physical adsorption such as zeolite or silica gel may be used.
Also, an interlayer insulating film made of a highly moisture-permeable resin containing desiccant granular substances can be used, and the interlayer insulating film and the second substrate 1204 can be fixed with a sealing material. In addition, inorganic materials such as PSG (phosphorus glass) and BPSG (phosphorus boron glass) may be used instead of the highly moisture-permeable resin.
Further, a desiccant may be provided in a region overlapping with the scanning lines. Furthermore, an interlayer insulating film made of a highly moisture-permeable resin containing desiccant granules may be used, and the interlayer insulating film and the second substrate 1204 may be fixed with a sealing material. By providing these desiccants, it is possible to suppress penetration of moisture into the display element and deterioration resulting therefrom without lowering the aperture ratio. Therefore, it is possible to suppress variations in deterioration of display elements between the peripheral portion and the central portion of the pixel portion 1202 .
The connection wiring 1210 is a connection wiring for transmitting signals input to the signal line driving circuit 1201 and the scanning line driving circuit 1203, and the connection wiring 1208 is connected from the FPC 1209 (flexible printed circuit) serving as an external input terminal. receive video and clock signals via
Next, the cross-sectional structure will be described with reference to FIG. 14(B). A driver circuit and a pixel portion are formed on the first substrate 1200, and a plurality of semiconductor elements represented by TFTs are provided. A signal line driver circuit 1201 and a pixel portion 1202 are shown as driver circuits. Note that the signal line driving circuit 1201 is formed by a CMOS circuit in which an n-channel TFT 1221 and a p-channel TFT 1222 are combined.
In this embodiment mode, the scanning line driver circuit and the TFT of the pixel portion are formed on the same substrate. Therefore, the volume of the light-emitting display device can be reduced.
In addition, the pixel portion 1202 includes a plurality of pixels including a switching TFT 1211 and a first pixel electrode 1213 (anode) made of a reflective conductive film electrically connected to the driving TFT 1212 and the other of its source and drain. formed by
Insulators 1214 (called banks, partitions, barriers, embankments, etc.) are formed on both ends of the first pixel electrode 1213 (anode). In order to improve the coverage of the film formed on the insulator 1214, the upper or lower end of the insulator 1214 is formed with a curved surface having a radius of curvature. Alternatively, the surface of the insulator 1214 may be covered with a protective film made of an aluminum nitride film, an aluminum nitride oxide film, a thin film containing carbon as its main component, or a silicon nitride film. Furthermore, by using an organic material obtained by dissolving or dispersing a material that absorbs visible light, such as a black pigment or a dye, as the insulator 1214, stray light from a display element formed later can be absorbed. As a result, the contrast of each pixel is improved. In the present invention, scanning lines, signal lines, and TFTs are arranged below the insulator. Also, the TFT is arranged below the scanning line or the signal line. When the TFTs are arranged below the scanning lines, the longitudinal direction of the scanning lines (or the direction of current flow) and the channel width direction of the TFTs are arranged in parallel. When the TFT is arranged below the signal line, the longitudinal direction of the signal line (or the direction of current flow) and the channel width direction of the TFT are arranged in parallel.
Also, an organic compound material is vapor-deposited on the first pixel electrode 1213 (anode) to selectively form an electroluminescent layer 1215 . Furthermore, a second pixel electrode 1216 (cathode) is formed on the electroluminescent layer 1215 .
Thus, a display element 1217 consisting of the first pixel electrode 1213 (anode), the electroluminescent layer 1215, and the second pixel electrode 1216 (cathode) is formed. The display element 1217 emits light toward the second substrate 1204 side.
Also, a protective laminate 1218 is formed to seal the display element 1217 . The protective laminate 1218 is composed of a laminate of a first inorganic insulating film, a stress relaxation film, and a second inorganic insulating film.
Next, the protective laminate 1218 and the second substrate 1204 are adhered with the first sealant 1205 and the second sealant 1206 . Note that it is preferable to drop the second sealant using a device for dropping a sealant. After the sealing material is dropped or discharged from a dispenser to form the sealing material on the active matrix substrate, the second substrate and the active matrix substrate are bonded together in a vacuum, and ultraviolet curing is performed for sealing. can.
An antireflection film 1226 is provided on the surface of the second substrate 1204 to prevent external light from being reflected on the substrate surface. Either or both of a polarizing plate and a retardation plate may be provided between the second substrate and the antireflection film. By providing the retardation plate and the polarizing plate, it is possible to prevent external light from being reflected by the pixel electrode. Note that the first pixel electrode 1213 and the second pixel electrode 1216 are formed using a light-transmitting conductive film or a semi-light-transmitting conductive film, and the interlayer insulating film is made of a material that absorbs visible light or a material that absorbs visible light. If an organic material obtained by dissolving or dispersing a material that absorbs light is used, external light is not reflected by each pixel electrode, and thus a retardation plate and a polarizing plate need not be used.
The connection wiring 1208 and the FPC 1209 are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1227. FIG. Furthermore, it is preferable to seal the connecting portion between each wiring layer and the connection terminal with a sealing resin. With this structure, it is possible to prevent moisture from entering the display element from the cross section and deteriorating the display element.
The space between the second substrate 1204 and the protective laminate 1218 may be filled with an inert gas such as nitrogen gas instead of the second sealant 1206 to prevent deterioration.
Also, a colored layer can be provided between the second substrate and the polarizing plate. In this case, a display element capable of emitting white light is provided in the pixel portion, and a colored layer showing RGB is separately provided, whereby full-color display can be performed. In addition, full-color display can be achieved by providing a display element capable of emitting blue light in the pixel portion and separately providing a color conversion layer or the like. Furthermore, it is also possible to form display elements that emit light of red, green, and blue in each pixel portion and use a colored layer. Such a display module has high color purity of each RBG, and is capable of high-definition display.
Also, a light-emitting display module may be formed using a substrate such as a film or resin as one or both of the first substrate 1200 and the second substrate 1204 . By using a substrate such as a film or a resin in this way, it is possible to reduce the weight, size, and thickness of the display device.
Further, IC chips such as a controller, memory, and pixel driving circuit may be provided on the surface or end of FPC 1209 (flexible printed circuit) serving as external input terminals to form a light emitting display module.
(Embodiment 7) A light-emitting device refers to a device (OLED device) having a structure in which an organic compound layer that emits light when an electric field is generated is sandwiched between an anode and a cathode. However, it is not limited to this.
In addition, the light-emitting device includes both those that use light emission (fluorescence) when a singlet exciton transitions to the ground state and those that use light emission (phosphorescence) when a triplet exciton transitions to the ground state. is intended to indicate
Examples of organic compound layers include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like. A light-emitting device is basically shown as a structure in which an anode, a light-emitting layer, and a cathode are sequentially stacked, but in addition, a structure in which an anode, a hole-injection layer, a light-emitting layer, an electron-injection layer, and a cathode are sequentially stacked. Alternatively, there is a structure in which an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode are sequentially stacked.
Note that the organic compound layer is not limited to having a layered structure in which a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and the like are clearly distinguished. In other words, the organic compound layer may have a structure in which the materials constituting the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the like are mixed.
Moreover, an inorganic substance may be mixed.
In addition, the organic compound layer of the OLED device may be made of any of low-molecular-weight materials, high-molecular-weight materials, and medium-molecular-weight materials.
In the present specification, a middle-molecular-weight material refers to a material having chained molecules with a length of 10 μm or less and having no sublimability.
(Embodiment 8) Another configuration that can be applied to the display element of the present invention will be described with reference to FIGS. 12 and 13. FIG.
Light-emitting devices (display devices) that use electroluminescence are distinguished by whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL device, and the latter is called an inorganic EL device. ing.
Inorganic EL devices are classified into dispersion-type inorganic EL devices and thin-film inorganic EL devices according to the device structure. The former has an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, while the latter has an electroluminescent layer made of a thin film of a luminescent material. They are common in that they require electrons. Mechanisms of light emission to be obtained include donor-acceptor recombination type light emission using a donor level and an acceptor level and localized type light emission using core electron transition of metal ions. In general, donor-acceptor recombination type luminescence is often used in distributed inorganic EL devices, and localized type luminescence is often used in thin-film inorganic EL devices.
A light-emitting material that can be used in the present invention is composed of a host material and an impurity element serving as a light-emitting center. Light emission of various colors can be obtained by changing the impurity element to be contained. Various methods such as a solid-phase method and a liquid-phase method (coprecipitation method) can be used as a method for producing the luminescent material. In addition, a spray pyrolysis method, a metathesis method, a method by a thermal decomposition reaction of a precursor, a reverse micelle method, a method combining these methods with high-temperature calcination, and a liquid phase method such as a freeze-drying method can also be used.
The solid-phase method is a method in which a base material and an impurity element or a compound containing an impurity element are weighed, mixed in a mortar, heated in an electric furnace, and fired to cause a reaction to cause the base material to contain the impurity element. The firing temperature is preferably 700-1500°C. This is because if the temperature is too low, the solid-phase reaction will not proceed, and if the temperature is too high, the base material will decompose. It should be noted that the firing may be performed in the powder state, but it is preferable to perform the firing in the pellet state. It requires firing at a relatively high temperature, but since it is a simple method, it is highly productive and suitable for mass production.
The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing the base material and an impurity element or a compound containing an impurity element are reacted in a solution, dried, and then calcined. The particles of the luminescent material are uniformly distributed, and the reaction can proceed even at a low firing temperature due to the small particle size.
Sulfides, oxides, and nitrides can be used as base materials for the light-emitting material.
Examples of sulfides include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y<sub>2</sub>S.<sub>3</sub>), gallium sulfide (Ga<sub>2</sub>S.<sub>3</sub>), strontium sulfide (SrS), barium sulfide (BaS), and the like can be used. In addition, as oxides, for example, zinc oxide (ZnO), yttrium oxide (Y<sub>2</sub>O<sub>3</sub>) etc. can be used. Further, as the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), etc. can also be used, and calcium-gallium sulfide (CaGa<sub>2</sub>S.<sub>4</sub>), strontium-gallium sulfide (SrGa<sub>2</sub>S.<sub>4</sub>), barium-gallium sulfide (BaGa<sub>2</sub>S.<sub>4</sub>), etc., may be a ternary mixed crystal.
Manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium as luminescent centers for localized luminescence (Pr) and the like can be used. A halogen element such as fluorine (F) or chlorine (Cl) may be added for charge compensation.
On the other hand, a light-emitting material containing a first impurity element forming a donor level and a second impurity element forming an acceptor level can be used as the emission center of donor-acceptor recombination type emission. For example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used as the first impurity element. For example, copper (Cu), silver (Ag), or the like can be used as the second impurity element.
When synthesizing a donor-acceptor recombination type light-emitting material using a solid-phase method, a host material, a first impurity element or a compound containing the first impurity element, a second impurity element or a second Compounds containing impurity elements are weighed, mixed in a mortar, and then heated and fired in an electric furnace. As the base material, the base material described above can be used, and as the first impurity element, for example, fluorine (F), chlorine (Cl), or the like can be used. is, for example, aluminum sulfide (Al<sub>2</sub>S.<sub>3</sub>) can be used, and as the second impurity element, for example, copper (Cu), silver (Ag), etc. can be used, and as the compound containing the second impurity element, for example, copper sulfide ( Cu<sub>2</sub>S), silver sulfide (Ag<sub>2</sub>S) etc. can be used. The firing temperature is preferably 700-1500°C. This is because if the temperature is too low, the solid-phase reaction will not proceed, and if the temperature is too high, the base material will decompose. It should be noted that the firing may be performed in the powder state, but it is preferable to perform the firing in the pellet state.
Further, as impurity elements when using a solid-phase reaction, a compound composed of a first impurity element and a second impurity element may be used in combination. In this case, the impurity element is easily diffused and the solid-phase reaction proceeds easily, so that a uniform light-emitting material can be obtained. Furthermore, since an extra impurity element is not included, a highly pure light-emitting material can be obtained. As the compound composed of the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), or the like can be used.
The concentration of these impurity elements may be 0.01 to 10 atom %, preferably 0.05 to 5 atom %, relative to the base material.
In the case of thin-film inorganic EL, the electroluminescent layer is a layer containing the above-mentioned light-emitting material, and is applied by vacuum deposition methods such as resistance heating deposition method and electron beam deposition (EB deposition) method, physical vapor deposition methods such as sputtering method ( PVD), a chemical vapor deposition method (CVD) such as an organometallic CVD method, a hydride transport low pressure CVD method, an atomic layer epitaxy method (ALE), or the like.
12(A) to (C) show an example of a thin-film inorganic EL element that can be used as a display element. 12A to 12C, the display element includes a first electrode layer 50, an electroluminescent layer 52, and a second electrode layer 53. In FIGS.
The display elements shown in FIGS. 12B and 12C have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the display element shown in FIG. 12A. The display element shown in FIG. 12(B) has an insulating layer 54 between the first electrode layer 50 and the electroluminescent layer 52, and the display element shown in FIG. and the electroluminescent layer 52, an insulating layer 54a is provided between the second electrode layer 53 and the electroluminescent layer 52, and an insulating layer 54b. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Further, the insulating layer may be a single layer or a laminate of multiple layers.
In addition, although the insulating layer 54 is provided so as to be in contact with the first electrode layer 50 in FIG. An insulating layer 54 may be provided on the .
In the case of a dispersed inorganic EL device, a particulate luminescent material is dispersed in a binder to form a film-like electroluminescent layer. If particles of a desired size cannot be obtained by the method for producing the luminescent material, the material may be processed into particles by pulverization with a mortar or the like. The binder is a substance for fixing the granular luminescent material in a dispersed state and maintaining the shape of the electroluminescent layer. The luminescent material is uniformly dispersed and fixed in the electroluminescent layer by the binder.
In the case of a dispersion-type inorganic EL element, the electroluminescent layer can be formed by a droplet ejection method that can selectively form an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a spin coating method, a dipping method, or a dispenser method. Law etc. can also be used. Although the film thickness is not particularly limited, it is preferably in the range of 10 to 1000 nm. In addition, in the electroluminescent layer containing a luminescent material and a binder, the ratio of the luminescent material is preferably 50 wt % or more and 80 wt % or less.
13(A) to (C) show an example of a dispersed inorganic EL device that can be used as a display device. The display element in FIG. 13A has a laminated structure of a first electrode layer 60, an electroluminescent layer 62, and a second electrode layer 63, and a luminescent material 61 held by a binder in the electroluminescent layer 62. include.
An organic material or an inorganic material can be used for the binder that can be used in this embodiment mode, and a mixed material of an organic material and an inorganic material may be used. As the organic material, polymers having a relatively high dielectric constant such as cyanoethyl cellulose resins, and resins such as polyethylene, polypropylene, polystyrene resins, silicone resins, epoxy resins and vinylidene fluoride can be used. Heat-resistant polymers such as aromatic polyamides and polybenzimidazoles, or siloxane resins may also be used. Note that the siloxane resin corresponds to a resin containing a SiOSi bond. Siloxane has a skeletal structure composed of bonds of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (eg, alkyl group, aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as substituents. Resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, phenol resins, novolak resins, acrylic resins, melamine resins, urethane resins, and oxazole resins (polybenzoxazole) may also be used.
Barium titanate (BaTiO<sub>3</sub>) and strontium titanate (SrTiO<sub>3</sub>) can be appropriately mixed to adjust the dielectric constant.
Inorganic materials contained in the binder include silicon oxide (SiO<sub>x</sub>), silicon nitride (SiN<sub>x</sub>), silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen or aluminum oxide (Al<sub>2</sub>O<sub>3</sub>), titanium oxide (TiO<sub>2</sub>), BaTiO<sub>3</sub>, SrTiO<sub>3</sub>, lead titanate (PbTiO<sub>3</sub>), potassium niobate (KNbO<sub>3</sub>), lead niobate (PbNbO<sub>3</sub>), tantalum oxide (Ta<sub>2</sub>O<sub>5</sub>), barium tantalate (BaTa<sub>2</sub>O<sub>6</sub>), lithium tantalate (LiTaO<sub>3</sub>), yttrium oxide (Y<sub>2</sub>O<sub>3</sub>), zirconium oxide (ZrO<sub>2</sub>), ZnS and other inorganic materials. By including (by addition, etc.) an inorganic material with a high dielectric constant in an organic material, the dielectric constant of the electroluminescent layer composed of the luminescent material and the binder can be more controlled, and the dielectric constant can be increased. .
In the manufacturing process, the luminescent material is dispersed in a solution containing a binder. As a solvent for the solution containing a binder that can be used in the present embodiment, a method (various types) of dissolving the binder material to form an electroluminescent layer is Wet process) and a solvent that can prepare a solution having a viscosity suitable for a desired film thickness may be appropriately selected. An organic solvent or the like can be used. For example, when a siloxane resin is used as a binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also referred to as PGMEA), 3-methoxy-3-methyl-1-butanol (also referred to as MMB) etc. can be used.
The display elements shown in FIGS. 13B and 13C have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the display element shown in FIG. 13A. The display element shown in FIG. 13(B) has an insulating layer 64 between the first electrode layer 60 and the electroluminescent layer 62, and the display element shown in FIG. and the electroluminescent layer 62, an insulating layer 64a is provided between the second electrode layer 63 and the electroluminescent layer 62, and an insulating layer 64b is provided between the second electrode layer 63 and the electroluminescent layer 62. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Further, the insulating layer may be a single layer or a laminate of multiple layers.
In addition, although the insulating layer 64 is provided so as to contact the first electrode layer 60 in FIG. An insulating layer 64 may be provided on the .
Insulating layers such as the insulating layer 54 in FIG. 12 and the insulating layer 64 in FIG. is preferred. For example, silicon oxide (SiO<sub>2</sub>), yttrium oxide (Y<sub>2</sub>O<sub>3</sub>), titanium oxide (TiO<sub>2</sub>), aluminum oxide (Al<sub>2</sub>O<sub>3</sub>), hafnium oxide (HfO<sub>2</sub>), tantalum oxide (Ta<sub>2</sub>O<sub>5</sub>), barium titanate (BaTiO<sub>3</sub>), strontium titanate (SrTiO<sub>3</sub>), lead titanate (PbTiO<sub>3</sub>), silicon nitride (Si<sub>3</sub>N.<sub>4</sub>), zirconium oxide (ZrO<sub>2</sub>), etc., a mixed film thereof, or a laminated film of two or more kinds thereof can be used. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. Also, the insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. Although the film thickness is not particularly limited, it is preferably in the range of 10 to 1000 nm.
The display element described in this embodiment mode can emit light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, and can operate in either DC driving or AC driving.
(Embodiment 9) In Embodiments 1 to 8, the display device mainly using electroluminescence was explained as an example. However, the present invention is applicable to various active matrix display devices. Other display devices include, for example, a liquid crystal display device and an FED (Field Emission Display).
(Embodiment 10) The present invention can also be applied to various semiconductor devices other than display devices (the semiconductor device is a concept including display devices).
For example, there is a memory element (storage element) such as a DRAM (Dynamic Random Access Memory). FIG. 15A shows a circuit diagram of a DRAM. A unit in which one terminal of the transistor 401 and a cell plate 402 (capacitor element) are connected is defined as one cell. The cells are connected to each other by wiring. Also, the other terminal of the transistor 401 is connected to the bit line 403 . Also, the gate of transistor 401 is connected to word line 404 .
The operating principle of DRAM is described. When the transistor 401 is an N-type transistor, a positive voltage is applied to the bit line 403 and the word line 404 to accumulate charges in the cell plate 402 during the data write period. Also, during the data read period, the charge accumulated in the cell plate 402 flows to the bit line 403 by applying a positive voltage to the word line. If the transistor 401 is a P-type transistor, voltages with opposite polarities may be applied in each period.
Furthermore, the larger the area of the cell plate 402, the larger the capacity. By increasing the capacity, it is possible to suppress the occurrence of soft errors (errors in which information recorded in memory cells is lost (rewritten) due to factors such as cosmic ray collisions). Therefore, in order to increase the capacitance of the capacitive element, it is required to increase the surface area of the capacitive element.
Therefore, a wiring is provided between adjacent electrodes, a thin film transistor connected to a capacitor is arranged under the wiring, and the direction of the channel width of the channel formation region of the thin film transistor is parallel to the direction of current flow in the wiring, or By arranging the electrodes in a direction parallel to the longitudinal direction of the shape of the electrodes, the capacitance of the capacitor can be increased.
In this embodiment, as shown in FIG. 16, the direction of the channel width of the transistor 401 is arranged parallel to the longitudinal direction of the shape of the cell plate 402 (or the electrode of the capacitor element) (arrow 7004 in FIG. 16). The transistor 401 may have a single-gate structure or a multi-gate structure.
The structure of the DRAM may be either stack type or trench type. The stack type is formed by forming an insulating film and then etching the insulating film to form a step on a substrate, and burying a capacitive element in the step. On the other hand, the trench type is formed by forming a step by etching a substrate and embedding a capacitive element in the step.
Note that, as a method for manufacturing a stack type DRAM, a transistor is formed on SOI (Silicon on Insulator) by a known method, or a TFT is manufactured by the method described in the third embodiment. After that, an insulating film (for example, acrylic, polyimide, siloxane, silicon oxide, silicon nitride, or the like can be used) is formed. Next, after patterning the insulating film, a step is formed by etching.
Thereafter, a bottom electrode (eg, metal such as aluminum can be used) is formed in contact with the source or drain region of the transistor. Next, a dielectric film (for example, titanium oxide, tantalum oxide, silicon nitride, silicon oxide, etc. can be used) is formed. Next, a capacitive element is formed in the step by forming an upper electrode (for example, tungsten silicide, polysilicon, etc. can be used).
Also, in the method of manufacturing a trench type DRAM, the substrate is first patterned and then etched to form a step in the substrate. After that, a transistor is formed on SOI (Silicon on Insulator) by a known method, or a TFT is manufactured by the method described in the third embodiment.
Thereafter, a bottom electrode (eg, metal such as aluminum can be used) is formed in contact with the source or drain region of the transistor. Next, a dielectric film (for example, titanium oxide, tantalum oxide, silicon nitride, silicon oxide, etc. can be used) is formed. Next, a capacitive element is formed in the step by forming an upper electrode (for example, tungsten silicide, polysilicon, etc. can be used).
Also, the present invention can be applied to devices other than DRAMs in order to increase the area of the device. FIG. 15(B) shows a circuit diagram of an element to which the present invention can be applied. A unit in which one terminal of the transistor 411 and the element 412 are connected is defined as one cell. The cells are connected to each other by wiring. Further, the other terminal of the transistor 411 is connected to the first wiring 413 . A gate of the transistor 411 is connected to a second wiring 414. FIG.
Therefore, a wiring is provided between adjacent elements, a thin film transistor connected to the element is arranged under the wiring, and the direction of the channel width of the channel formation region of the thin film transistor is parallel to the direction of current flow in the wiring, or By arranging the elements in a direction parallel to the longitudinal direction of the shape of the element, it is possible to increase the area of the element or increase the number of elements.
As the element 412, for example, an organic memory, a photodiode, a piezoelectric element, or the like can be used.
When an organic memory is used as the element 412, a memory element can be formed. In addition, as a method of the organic memory, a method of electrically storing data by selecting the first wiring 413 and the second wiring 414, an organic memory element using an organic material, that is, a conjugated polymer material doped with a photoacid generator. There is a method of optically memorizing by irradiating a laser beam to the memory. When forming an organic memory element, a certain amount of area is required. Also, in order to increase the memory capacity, it is effective to increase the number of memory elements. Therefore, by adopting the configuration of the present invention, it is possible to increase the number of memory elements, which is effective.
Also, when a photodiode is used as the element 412, an optical sensor can be formed. As types of photodiodes, PN photodiodes, PIN photodiodes, avalanche photodiodes, Schottky photodiodes, and the like can be used. Since the photoelectric conversion efficiency increases as the area of the photodiode increases, it is effective to adopt the configuration of the present invention.
Also, by using a piezoelectric element as the element 412, a pressure sensor can be formed. Furthermore, a touch panel can be formed by forming a piezoelectric element and a display element on the same substrate. Piezoelectric elements include a pressure sensor equipped with a parallel plate capacitor, a strain gauge type pressure sensor that uses a compensated high resistance intrinsic semiconductor region as a strain gauge by doping n-type impurities into a p-type silicon crystal by thermal diffusion. There is When forming a piezoelectric element, a certain amount of area is required. Also, the larger the area, the higher the sensitivity as a sensor. Therefore, it is effective to employ the configuration of the present invention.
As described above, the present invention can be applied to various semiconductor devices.
(Embodiment 11) The display device of the present invention can be used for display portions of various electronic devices. In particular, it is desirable to use the display device of the present invention for mobile devices that are required to be thin and light. Moreover, the semiconductor device of the present invention can be used for various electronic devices. In particular, it is desirable to use the semiconductor device of the present invention for mobile devices that are required to be thin and light.
Examples of electronic equipment in which the display device or semiconductor device of the present invention is incorporated in a housing include a television device (also simply referred to as a TV, a television, or a television receiver), a camera (video camera, digital camera, etc.), and a goggle-type display. , navigation systems, audio playback devices (car audio, audio components, etc.), computers, game machines, personal digital assistants (mobile computers, mobile phones, portable game machines, electronic books, etc.), image playback devices equipped with recording media (Specifically, a device equipped with a display capable of reproducing recording media such as DVD (digital versatile disc), HDDVD (High Definition DVD), Blu-ray disc (Blu-ray (registered trademark) Disk) and displaying the image), and other displays electric appliances having parts, and the like. A specific example of an electronic device is shown in FIG.
FIG. 17A shows a portable information terminal including a main body 9201, a display portion 9202, and the like.
FIG. 17B shows a digital video camera including a main body 9702, a display portion 9701, and the like.
FIG. 17C shows a portable terminal including a main body 9101, a display portion 9102, and the like.
FIG. 17D shows a portable television device including a main body 9301, a display portion 9302, and the like. Such a television device can be widely applied from a small size to be mounted on a mobile terminal such as a mobile phone, to a medium size that can be carried around, and a large size (for example, 40 inches or more). .
FIG. 17E shows a portable computer including a main body 9401, a display portion 9402, and the like.
FIG. 17F shows a television device including a main body 9501, a display portion 9502, and the like.
As described above, the scope of application of the present invention is extremely wide and can be applied to methods for manufacturing electronic devices in all fields.
51 electroluminescent layer
52 electroluminescent layer
62 electroluminescent layer
100 gate electrode
101 first semiconductor layer
102 Second semiconductor layer
103 connection electrode
104 Signal line
105 gate wiring
106 power supply line
107 pixel electrode
108 connection electrode
300 capacitive element
301 Driving TFT
302 TFT for switching
303 display element
304 Signal line
305 scanning line
306 power supply line
401 transistor
402 cell plate
403 bit line
404 word line
411 transistor
412 element
413 1st wiring
414 second wiring
501 1st wiring
502 1st wiring
503 1st wiring
601 second wiring
602 second wiring
701 pixel electrode
702 pixel electrode
703 pixel electrode
704 pixel electrode
705 pixel electrode
706 pixel electrode
707 pixel electrode
1200 1st substrate
1201 Signal line drive circuit
1202 Pixel part
1202 Pixel part
1203 scanning line drive circuit
1204 second substrate
1205 First sealing material
1206 Second sealing material
1208 connection wiring
1209 FPCs
1210 connection wiring
1211 TFT for switching
1212 Driving TFT
1213 first pixel electrode
1214 Insulator
1215 electroluminescent layer
1216 Second pixel electrode
1217 display element
1218 protective lamination
1221 n-channel TFT
1222 p-channel TFT
1226 Anti-reflective coating
1227 Anisotropic conductive resin
1230 monitor element
4101 Island-like semiconductor layer
4102 Island-like semiconductor layer
4103 gate electrode
4104 gate electrode
4105 contact hole
4106 wiring
4107 wiring
4108 wiring
4109 pixel electrode
4110 Luminescent area
5001 First wiring area
5002 Second routing area
6001 dashed line
6002 dashed line
6003 dashed line
6011 dashed line
6012 dashed line
6021 dashed line
6022 dashed line
6031 dashed line
6032 dashed line
7001 arrow
7002 arrow
7003 arrow
7004 arrow
8001 first arrow
8002 second arrow
8003 third arrow
8004 fourth arrow
9101 body
9102 display
9201 body
9202 display
9301 body
9302 display
9401 body
9402 display
9501 body
9502 display
9701 display
9702 body
17 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17
Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| JP2003295793A | Cites | Japan |
| JP2004006243A | Cites | Japan |
| JP2005157265A | Cites | Japan |
| JP10123567A | Cites | Japan |
101 members in 5 offices
Priority claims4
| Document | Office | Kind | Date |
|---|---|---|---|
| 2006199292 | Japan | – | |
| 2006199292 | Japan | A | |
| 2020063005 | Japan | A | |
| 2022005921 | Japan | A |
Members101
| Document | Office | Kind | |
|---|---|---|---|
| CN101110422A | China | A | |
| KR20080008989A | Republic of Korea | A | |
| US2008017866A1 | United States of America | A1 | |
| JP2008046619A | Japan | A | |
| TW200822371A | Taiwan Province of China | A | |
| US7863612B2 | United States of America | B2 | |
| US2011095297A1 | United States of America | A1 | |
| CN101110422B | China | B | |
| CN102522373A | China | A | |
| JP2012185502A | Japan | A | |
| JP5147320B2 | Japan | B2 | |
| JP5148000B2 | Japan | B2 | |
| US8426860B2 | United States of America | B2 | |
| JP2013083990A | Japan | A | |
| US2013214280A1 | United States of America | A1 | |
| JP2013214750A | Japan | A | |
| TW201347200A | Taiwan Province of China | A | |
| KR20140010915A | Republic of Korea | A | |
| KR20140012922A | Republic of Korea | A | |
| KR20140012923A | Republic of Korea | A | |
| TWI431780B | Taiwan Province of China | B | |
| JP5507731B2 | Japan | B2 | |
| JP2014098904A | Japan | A | |
| JP5568173B2 | Japan | B2 | |
| US2014246678A1 | United States of America | A1 | |
| TW201436244A | Taiwan Province of China | A | |
| KR20140133802A | Republic of Korea | A | |
| TWI463671B | Taiwan Province of China | B | |
| KR101472774B1 | Republic of Korea | B1 | |
| CN102522373B | China | B | |
| KR101482920B1 | Republic of Korea | B1 | |
| KR101482921B1 | Republic of Korea | B1 | |
| JP2015028640A | Japan | A | |
| KR101496749B1 | Republic of Korea | B1 | |
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| TWI538223B | Taiwan Province of China | B | |
| TW201624735A | Taiwan Province of China | A | |
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| JP2019040207A | Japan | A | |
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| JP2022062072A | Japan | A | |
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| US11605696B2 | United States of America | B2 | |
| JP2023086746A | Japan | A | |
| JP7300548B2This record | Japan | B2 | |
| US2023209940A1 | United States of America | A1 | |
| JP7390410B2 | Japan | B2 | |
| JP7440700B1 | Japan | B1 | |
| JP2024032703A | Japan | A | |
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| JP7486633B2 | Japan | B2 | |
| TWI843951B | Taiwan Province of China | B | |
| JP2024088677A | Japan | A | |
| US2024224673A1 | United States of America | A1 | |
| TW202443921A | Taiwan Province of China | A | |
| JP2025137573A | Japan | A | |
| US12426364B2 | United States of America | B2 |
11 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| First payment of annual fees (during grant procedure)JAPANESE INTERMEDIATE CODE: A61A61 | A61 | |
| Certificate of patent or registration of utility modelJAPANESE INTERMEDIATE CODE: R150R150 | R150 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Decision of grant or rejection writtenTRDD | TRDD | |
| Request for written amendment filedJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Written request for extension of timeJAPANESE INTERMEDIATE CODE: A601A601 | A601 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Request for written amendment filedJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Written request for application examinationJAPANESE INTERMEDIATE CODE: A621A621 | A621 | |
| Explanation of circumstances concerning accelerated examinationJAPANESE INTERMEDIATE CODE: A871A871 | A871 |
Numbers
- Publication
- 7300548
- Application
- 183116
Titles2
- Japanese
- 表示装置
- English
- Display device
Classification
- CPC, 19
- H10D86/441
- H10D86/40
- G02F1/1362
- H10B12/30
- H10K59/131
- H10D86/60
- H10D30/6757
- H10D30/67
- H10K59/12
- H10K59/124
- H10K59/1213
- H10K59/1216
- H10H29/142
- H10D30/6744
- H10D30/6745
- H10D30/6746
- H10D86/421
- H10D86/471
- H10D86/481
- IPC, 14
- H01L29 786
- G09F9 30
- H10K50 115
- H10K50 10
- H10K59 121
- H10K59 131
- H05B33 14
- H05B33 02
- H10D62 10
- H10D30 01
- H10D30 67
- H10D62 40
- H10D62 815
- H10K99 00
