Semiconductor package and method of fabricating the same
18 claims: 7 independent, 11 dependent
- 1絶縁性保護層及び前記絶縁性保護層のオープニングによって露出された複数のチップパッドを含む半導体チップと、再配線層と、を備え、前記再配線層は、有機フィルムを各々含む複数の絶縁層と、複数の再配線パターンと、を含み、前記複数の再配線パターンの各々は、前記複数の絶縁層の中の対応する絶縁層の一面に形成された配線部分を含み、前記複数の絶縁層の各々は、2つの絶縁層から成り、前記2つの絶縁層の中の1つである第1有機フィルムは、フィラー(filler)を含み、前記フィラーは、無機物で形成された複数のイオントラップ粒子を含み、前記無機物は、Cl - 、K + 、Na + 、OH - 、及びH + の中の少なくとも1つのイオンと化学的に反応する物質であることを特徴とする半導体パッケージ。
- 2前記第1有機フィルムは、前記イオントラップ粒子を含む前記フィラーが内部に分散された感光性ポリマーフィルムであることを特徴とする請求項1に記載の半導体パッケージ。
- 3前記フィラーに含まれる前記イオントラップ粒子は、塩素イオンと化学的に結合する物質であることを特徴とする請求項2に記載の半導体パッケージ。
- 4前記無機物は、マグネシウム(Mg)化合物、アラバミン(Ab)化合物、又はビスマス(Bi)化合物の中の少なくとも1つを含むことを特徴とする請求項1に記載の半導体パッケージ。
- 5前記第1有機フィルムは、第1ポリマー物質で形成されて前記イオントラップ粒子を含む前記フィラーが内部に分散されたポリマーフィルムであり、前記イオントラップ粒子は、前記第1ポリマー物質よりも高い熱伝導率を有することを特徴とする請求項1に記載の半導体パッケージ。
- 6前記第1有機フィルムは、第1ポリマー物質で形成されて前記イオントラップ粒子を含む前記フィラーが内部に分散されたポリマーフィルムであり、前記イオントラップ粒子は、前記第1ポリマー物質よりも低い熱膨張係数を有することを特徴とする請求項1に記載の半導体パッケージ。
- 7前記複数の再配線パターンは、前記半導体チップのチップパッドの中の第1チップパッドに接続された第1再配線パターンを含むことを特徴とする請求項1に記載の半導体パッケージ。
- 8前記第1有機フィルムは、前記第1チップパッドに接触することを特徴とする請求項7に記載の半導体パッケージ。
- 9前記第1チップパッドは、前記絶縁性保護層の第1オープニングによって露出された一面を有し、前記露出された第1チップパッドの一面は、前記第1オープニング内に形成された前記第1再配線パターンによって完全に覆われていることを特徴とする請求項8に記載の半導体パッケージ。
- 10前記第1再配線パターンは、ビア部分及び前記ビア部分と一体に形成された配線部分を含み、前記ビア部分は、前記絶縁性保護層の第1オープニング内に形成されて前記第1チップパッドに接続され、前記配線部分は、前記第1有機フィルムの下に形成されていることを特徴とする請求項9に記載の半導体パッケージ。
- 11前記第1有機フィルムは、前記イオントラップ粒子を含む前記フィラーが分散されたポリマー物質を含む第1上部ポリマーフィルムであり、前記複数の絶縁層の各々は、前記第1上部ポリマーフィルムの下に直接配置された第1下部有機ポリマーフィルムである第1下部ポリマーフィルムを含み、前記複数の再配線パターンは、前記半導体チップのチップパッドの中の第1チップパッドに接続されて前記第1下部ポリマーフィルムの下に直接形成された第1再配線パターンを含み、前記第1下部ポリマーフィルムは、感光性ポリマーフィルムであり、前記第1上部ポリマーフィルムは、前記第1下部ポリマーフィルムの70%以下の厚さを有することを特徴とする請求項1に記載の半導体パッケージ。
- 12絶縁性保護層及び前記絶縁性保護層のオープニングによって露出された複数のチップパッドを含む半導体チップと、再配線層と、を備え、前記再配線層は、有機フィルムを各々含む複数の絶縁層と、複数の再配線パターンと、を含み、前記複数の再配線パターンの各々は、前記複数の絶縁層の中の対応する絶縁層の一面に形成された配線部分を含み、前記複数の絶縁層の中の少なくとも1つ の 有機フィルムは、フィラー(filler)を含み、前記フィラーは、前記少なくとも1つの有機フィルム内に分散されて無機物で形成された複数のイオントラップ粒子を含み、前記イオントラップ粒子は、前記チップパッドに対して腐蝕性である反応性物質と結合する物質を含 み、 前記少なくとも1つの有機フィルムは、第1上部ポリマーフィルム及び前記第1上部ポリマーフィルムの下に直接配置された第1下部ポリマーフィルムを含み、 前記第1上部ポリマーフィルムは、前記イオントラップ粒子を含む前記フィラーが分散された第1ポリマー物質を含み、 前記複数の再配線パターンは、前記半導体チップのチップパッドの中の第1チップパッドに接続されて前記第1下部ポリマーフィルムの下に直接形成された第1再配線パターンを含 むことを特徴とする半導体パッケージ。
- 13前 記イオントラップ粒子は、前記第1ポリマー物質よりも高い熱伝導率を有することを特徴とする請求項12に記載の半導体パッケージ。
- 14前記第1再配線パターンは、ビア部分及び前記ビア部分と一体に形成された配線部分を含み、前記ビア部分は、前記第1上部ポリマーフィルム及び前記第1下部ポリマーフィルムを貫通するオープニング内に形成され、前記ビア部分は、前記第1チップパッドに接続され、前記配線部分は、前記第1下部ポリマーフィルムの下に形成されていることを特徴とする請求項 12 に記載の半導体パッケージ。
- 15前記ビア部分は、前記チップパッドにおけるビアの幅が前記配線部分におけるビアの幅よりも小さいテーパー形状を有することを特徴とする請求項 14 に記載の半導体パッケージ。
- 16前記ビア部分及び前記配線部分は、銅で形成されていることを特徴とする請求項 14 に記載の半導体パッケージ。
- 17半導体チップの第1面上に少なくとも1層の第1絶縁層を形成する段階と、前記第1絶縁層をパターニングして、前記半導体チップの前記第1面に含まれる前記半導体チップに信号及び電源を供給する複数の金属チップパッドである第1チップパッドを、前記パターニングされた第1絶縁層のオープニングを通じて露出させる段階と、前記第1絶縁層上に第1再配線パターンを形成する段階と、を有し、前記第1再配線パターンは、前記第1チップパッドに接続される第1ビア部分と、前記第1絶縁層上に水平に延長されて前記第1ビア部分に連結される第1配線部分と、を含み、前記第1絶縁層は、複数のイオントラップ粒子が内部に分散された有機フィルムを含み、前記イオントラップ粒子は、無機物を含 み、 前記半導体チップの第1面上に少なくとも1層の第1絶縁層を形成する段階は、第1上部絶縁層を前記半導体チップの第1面上に形成する段階及び前記第1上部絶縁層上に第1下部絶縁層を形成する段階を含み、 前記第1上部絶縁層は、複数のイオントラップ粒子が内部に分散された有機フィルムであり、 前記第1下部絶縁層は、感光性ポリマーフィルムを含 むことを特徴とする半導体パッケージ製造方法。
- 18前記第1上部絶縁層は、感光性ポリマーフィルムではないことを特徴とする請求項 17 に記載の半導体パッケージ製造方法。
Independent claims18
190 paragraphs, as filed
The present invention relates to a semiconductor package, and more particularly to a semiconductor package including a redistribution layer.
A semiconductor package is an implementation of an integrated circuit chip in a form suitable for use in an electronic product. Generally, a semiconductor package mounts a semiconductor chip on a printed circuit board (PCB) and electrically connects them using bonding wires or bumps. With the development of the electronics industry, various studies are being conducted to improve the reliability and durability of semiconductor packages.
<p><patcit num="1"><text>U.S. Pat. No. 5,172,212</text></patcit><patcit num="2"><text>U.S. Pat. No. 6,958,546</text></patcit><patcit num="3"><text>U.S. Pat. No. 7,033,923</text></patcit><patcit num="4"><text>U.S. Pat. No. 8,580,672</text></patcit><patcit num="5"><text>U.S. Pat. No. 8,765,531</text></patcit><patcit num="6"><text>U.S. Patent No. 9472515</text></patcit><patcit num="7"><text>U.S. Patent No. 9780069</text></patcit></p>
<p>SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package with improved reliability and durability and a method of manufacturing the same.</p>
<p>A semiconductor package according to one aspect of the present invention, which has been made to achieve the above object, comprises a semiconductor chip including an insulating protective layer and a plurality of chip pads exposed by openings in the insulating protective layer; a rewiring layer; wherein the rewiring layer includes a plurality of insulating layers each including an organic film and a plurality of rewiring patterns, each of the plurality of rewiring patterns corresponding to one of the plurality of insulating layers Each of the plurality of insulating layers includes a wiring portion formed on one surface of an insulating layer, each of the plurality of insulating layers is composed of two insulating layers, and a first organic film, which is one of the two insulating layers, is a filler. ), wherein the filler comprises a plurality of ion trap particles formed of an inorganic material, the inorganic material comprising Cl<sup>-</sup>, K<sup>+</sup>, Na<sup>+</sup>, OH<sup>-</sup>, and H<sup>+</sup>is a substance that chemically reacts with at least one ion in</p><p>A semiconductor package according to another aspect of the present invention to achieve the above object comprises a semiconductor chip including an insulating protective layer and a plurality of chip pads exposed by openings in the insulating protective layer; a rewiring layer; and wherein the redistribution layer includes a plurality of insulating layers each including an organic film and a plurality of redistribution patterns, each of the plurality of redistribution patterns corresponding to one of the plurality of insulating layers. At least one of the plurality of insulating layers includes a wiring portion formed on one surface of the insulating layer, and the organic film, which is at least one of the plurality of insulating layers, includes a filler, and the filler is included in the at least one organic film. A plurality of ion trap particles dispersed and made of inorganic material are included, wherein the ion trap particles include a material that combines with a reactive material that is corrosive to the chip pad.</p><p>A method for manufacturing a semiconductor package according to one aspect of the present invention, which has been made to achieve the above object, comprises the steps of forming at least one first insulating layer on a first surface of a semiconductor chip; and patterning the first insulating layer. exposing first chip pads, which are a plurality of metal chip pads for supplying signals and power to the semiconductor chip included in the first surface of the semiconductor chip, through openings in the patterned first insulating layer. and forming a first rewiring pattern on the first insulating layer, wherein the first rewiring pattern includes a first via portion connected to the first chip pad; a first wiring portion horizontally extending on an insulating layer and connected to the first via portion, wherein the first insulating layer includes an organic film in which a plurality of ion trapping particles are dispersed; , wherein the ion trap particles contain an inorganic substance.</p>
<p>Advantageous Effects of Invention According to the present invention, it is possible to improve the heat dissipation characteristics of a semiconductor chip mounted in a semiconductor package and prevent/reduce the damage of chip pads due to reactive substances. Therefore, reliability and durability of the semiconductor package can be improved. Also, it is possible to provide a method of manufacturing a semiconductor package that prevents warpage of the semiconductor package during the manufacturing process.</p>
<figref num="1">1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention;</figref><figref num="2A">1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention;</figref><figref num="2B">2B is an enlarged view of area A in FIG. 2A. FIG.</figref><figref num="3A">1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention;</figref><figref num="3B">FIG. 3B is an explanatory view showing an example of the forming process of the first opening according to the present embodiment, and is an enlarged view of area A in FIG. 3A.</figref><figref num="3C">FIG. 3C is an enlarged view of region B in FIG. 3B.</figref><figref num="3D">FIG. 3B is an explanatory view showing another example of the forming process of the first opening according to the present embodiment, and is an enlarged view of area A in FIG. 3A.</figref><figref num="3E">FIG. 3B is an explanatory view showing the step of forming the first opening according to the present embodiment, and is an enlarged view of area A in FIG. 3A.</figref><figref num="3F">FIG. 3E is an enlarged view of region B of FIG. 3E.</figref><figref num="4A">1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention;</figref><figref num="4B">4B is an enlarged view of area A in FIG. 4A. FIG.</figref><figref num="4C">FIG. 4B is a diagram showing the first rewiring pattern according to the present embodiment, and is an enlarged diagram of area A in FIG. 4A.</figref><figref num="4D">FIG. 4B is a diagram showing a step of forming a first rewiring pattern according to the present embodiment, and is an enlarged view of area A in FIG. 4A.</figref><figref num="4E">FIG. 4B is a diagram showing a step of forming a first rewiring pattern according to the present embodiment, and is an enlarged view of area A in FIG. 4A.</figref><figref num="5A">1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention;</figref><figref num="5B">5B is an enlarged view of area A in FIG. 5A. FIG.</figref><figref num="6A">1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention;</figref><figref num="6B">6B is an enlarged view of area A in FIG. 6A. FIG.</figref><figref num="7A">4A to 4D are cross-sectional views showing a manufacturing process of a semiconductor package according to an embodiment of the present invention;</figref><figref num="7B">4A to 4D are cross-sectional views showing a manufacturing process of a semiconductor package according to an embodiment of the present invention;</figref><figref num="8A">It is explanatory drawing which shows the manufacturing method of the semiconductor package by other embodiment of this invention.</figref><figref num="8B">It is explanatory drawing which shows the manufacturing method of the semiconductor package by other embodiment of this invention.</figref><figref num="8C">It is explanatory drawing which shows the manufacturing method of the semiconductor package by other embodiment of this invention.</figref><figref num="8D">It is explanatory drawing which shows the manufacturing method of the semiconductor package by other embodiment of this invention.</figref><figref num="9">FIG. 5 is a cross-sectional view showing a second example of a semiconductor package according to one embodiment of the present invention;</figref><figref num="10A">FIG. 10 is a plan view showing a third example of a semiconductor package according to one embodiment of the present invention;</figref><figref num="10B">FIG. 10B is a cross-sectional view taken along line I-II of FIG. 10A.</figref><figref num="10C">FIG. 10B is a cross-sectional view showing a fourth example of the semiconductor package according to one embodiment of the present invention, and is a cross-sectional view cut along line I-II shown in FIG. 10A.</figref><figref num="11A">4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention;</figref><figref num="11B">4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention;</figref><figref num="11C">4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention;</figref><figref num="12">FIG. 10 is a cross-sectional view showing another example of a semiconductor package according to still another embodiment of the present invention;</figref><figref num="13A">1 is a cross-sectional view showing a semiconductor module according to one embodiment of the present invention; FIG.</figref><figref num="13B">13B is an enlarged view of area A of FIG. 13A. FIG.</figref>
Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.
1, 2A, 3A, 4A, 5A, and 6A are cross-sectional views showing a method of manufacturing a semiconductor package according to one embodiment of the present invention. 2B, 4B, 5B, and 6B are enlarged views of area A in FIGS. 2A, 4A, 5A, and 6A, respectively. FIG. 4C is a diagram showing the first rewiring pattern according to the present embodiment, and is an enlarged diagram of area A in FIG. 4A. 4D and 4E are diagrams showing the process of forming the first rewiring pattern according to the present embodiment, and are enlarged views of area A in FIG. 4A. 3A to 3F will be described later.
Referring to FIG. 1, semiconductor chip 100 and mold membrane 200 are placed on carrier substrate 910 . The semiconductor chip 100 has an upper surface 100a and a lower surface 100b facing each other. In this specification, the first direction D1 is defined as a direction parallel to the top surface 100a of the semiconductor chip 100. As shown in FIG. A second direction D2 is defined as a direction perpendicular to the top surface 100a of the semiconductor chip 100. As shown in FIG. Also, the second direction D2 corresponds to the vertical direction and serves as a reference for upward and downward directions. A lower surface 100 b of the semiconductor chip 100 faces the carrier substrate 910 .
The semiconductor chip 100 has chip pads 110 on the bottom surface 100b. Chip pad 110 comprises metals such as aluminum, copper, silver, and/or gold, and alloys thereof. A chip pad 110 is a terminal of the semiconductor chip 100 . The chip pads 110 are electrically connected to an integrated circuit (not shown) of the semiconductor chip 100 to supply signals and/or voltages to the integrated circuit (not shown) of the semiconductor chip 100 .
As used herein, the term electrically coupled/connected to some component may refer to direct coupling/connection or through other conductive components for transmitting signals and/or voltages. Including indirect links/connections.
The integrated circuit of semiconductor chip 100 includes transistors. The semiconductor chip 100 includes a protective layer 120 that exposes the chip pads 110 . Protective layer 120 is formed during the manufacturing process of semiconductor chip 100 . After the protective layer 120 is deposited on the semiconductor wafer containing a plurality of integrated semiconductor devices, the semiconductor wafer is separated into individual semiconductor chips such as the semiconductor chip 100 (singulation). The protective layer 120 is an insulating protective layer (eg, SiO<sub>2</sub>(insulating inorganic materials such as sintered silicates) and is at least one of the topmost layers or topmost layers on a semiconductor wafer from which semiconductor chips are formed. A protective layer 120 extends over the chip pad 110 . After the semiconductor wafer is singulated, openings are formed in protective layer 120 to expose chip pads 110 . Although not shown, protective layer 120 may include multiple stacked layers.
A mold film 200 is formed on the carrier substrate 910 to cover at least a portion of the semiconductor chip 100 . As an example, the mold film 200 covers the upper surface 100a and side surfaces of the semiconductor chip 100. As shown in FIG. As another example, the mold film 200 covers the sides of the semiconductor chip 100 but exposes the top surface 100a. As yet another example, the mold film 200 is not formed on the top surface 100a of the semiconductor chip 100, but another material is formed on the top surface 100a of the semiconductor chip 100. FIG.
The mold film 200 contains, for example, resin such as epoxy molding compound (EMC). Although not shown, adhesive layers are further interposed between the carrier substrate 910 and the semiconductor chip 100 and between the carrier substrate 910 and the mold film 200 . The carrier substrate 910 and the adhesive layer are then removed to expose the bottom surface 100b of the semiconductor chip 100 and the bottom surface 200b of the mold film 200. FIG.
2A and 2B, a first upper insulating layer 310 is formed on the semiconductor chip 100. As shown in FIG. The first upper insulating layer 310 is formed by a deposition or coating process. The coating process is spin coating, spray coating, slit coating, roller coating, dip coating, or extrusion coating.
In one embodiment, a nozzle is used to deposit the material of the first upper insulating layer 310 . In another embodiment, the first upper insulating layer 310 is directly coated on the lower surface 100b of the semiconductor chip 100 and the lower surface 200b of the mold film 200 with a viscous fluid. For example, the first upper insulating layer 310 is applied by a nozzle. In another embodiment, the first upper insulating layer 310 is applied on one side of the carrier substrate 910 with a viscous fluid by a nozzle. As an example, the material of the first upper insulating layer 310 is deposited by a nozzle on the horizontal center portion of the surface on which the first upper insulating layer 310 is formed, and is rotated about the vertical axis to form the first upper insulating layer 310. material extends to the edge of the surface on which it is formed.
In the spray coating process, the material of the first upper insulating layer 310 is sprayed onto the surface where the first upper insulating layer 310 is to be formed. Spray coating then does not require any additional mechanical steps to place the material in the desired location. Spray coating includes spraying several times (eg, several sprays of a substance) onto the first upper insulating layer 310 .
Roller coating involves rolling a roller across the surface on which the first upper insulating layer 310 is formed to coat the material of the first upper insulating layer 310 to the desired thickness at that location.
Dip coating involves immersing the surface on which the first upper insulating layer 310 is to be formed in a container containing the material of the first upper insulating layer 310, and coating the surface with the first upper insulating layer 310 to the desired thickness. It includes the step of removing in a specified ratio.
After the coating step, the applied material is baked to substantially remove the flowing properties (flowability) of the material. That is, the fluid properties of the applied material are substantially eliminated. Baking is the process of removing the solvent of the applied material by evaporation.
The formation of the first upper insulating layer 310 (including the baking process) is performed at 300°C or less, eg, 150°C to 300°C. For example, none of the steps during formation of the first upper insulating layer 310 are performed at a temperature higher than 300°C.
Here, the formation of the first upper insulating layer 310 is included in the formation of the entire rewiring layer 300, which will be described later. The first upper insulating layer 310 covers the bottom surface 100b of the semiconductor chip 100 and the bottom surface 200b of the mold film 200, and contacts the bottom surface 100b of the semiconductor chip 100 and the bottom surface 200b of the mold film 200. As shown in FIG. For example, the first top insulating layer 310 covers and contacts the entire exposed bottom surface of the structure shown in FIG. 1 after the carrier substrate and adhesion layer are removed. A first upper insulating layer 310 is formed on the protective layer 120 and the chip pads 110 of the semiconductor chip 100 to contact the protective layer 120 and the chip pads 110 .
As shown in FIG. 2B, the first upper insulating layer 310 includes a first polymer film 311 and a first inorganic filler 312. As shown in FIG.
First polymer film 311 comprises an organic film. As an example, first polymer film 311 includes a photosensitive polymer. The photosensitive polymer is at least one of, for example, photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene-based polymer (BCB). Including one. The photopolymer film is electrically insulating and formed as a protective layer. As another example, first polymer film 311 includes a non-photosensitive polymer. Non-photosensitive polymers include epoxy-based polymers.
A first inorganic filler 312 is dispersed within the first polymer film 311 . First inorganic filler 312 includes a plurality of particles. As an example, first inorganic filler 312 is a particle containing an ion trapping agent.
The ion trapping agent includes at least one of magnesium (Mg) compounds, alabamine (Ab) compounds, and bismuth (Bi) compounds. Ion trapping agents trap reactive substances such as chloride ions.
A reactive substance is a substance that is corrosive to the semiconductor package and/or conductive traces (eg, metal conductors) of the semiconductor chip 100 . For example, reactive materials are by-products of the semiconductor package manufacturing process. Also, when the reactive material comes into contact with conductive wiring within the semiconductor package (eg, chip pads 110 of semiconductor chip 100), the reactive material may undesirably chemically react with the conductive wiring, or the conductive wiring may be damaged. Corrode. For example, the reactive material chemically reacts with and corrodes aluminum, copper, and silver at room temperature. By way of example, but not limitation, the reactive substance is chloride anion. For example, aluminum wiring (e.g., pads) reacts with chlorine to form AlCl<sub>2</sub>to form The reaction formula is as follows.
Al(OH)<sub>3</sub>+Cl<sup>-</sup>Al(OH)<sub>2</sub>Cl+OH<sup>-</sup>Al+3Cl-AlCl<sub>3</sub>+3e<sup>-</sup>
The reactive substance is a halogen ion (e.g., any one or more of fluorine (F), chlorine (Cl), bromine (Br), iodide (I), and/or astatine (At) ions) . A reactive substance is an acidic compound that chemically reacts with conductive interconnects (eg, Al, Cu, or Ag) at room temperature.
The ion trapping agent chemically reacts with and captures the reactive substance. In one embodiment, the chemical reaction between the ion trapping agent and the reactive substance is in the form of chemisorption, in which the reactive substance chemically bonds to the ion trapping agent and adsorbs to the surface of filler particles containing the ion trapping agent. be.
In this embodiment, the chemical reaction between the ion trapping agent and the reactive substance forms one or more chemical compounds. One or more chemical compounds remain attached to the particles of the first inorganic filler 312 . Additionally, one or more chemical compounds are separated from the first inorganic filler 312 that has chemically reacted with the reactive material, such newly separated compounds having no reactivity. For example, the isolated compound has no reactivity with the semiconductor chip 100 and/or conductive traces of the semiconductor package. For example, the newly isolated compounds do not react with aluminum, silver, and copper at room temperature or the operating temperature of semiconductor chip 100 . Here, room temperature is 21°C.
Ion trapping agents are ion exchange compounds such as halogen ion exchange agents. In the case of halogen ion exchange agents, the ions of the compound of the ion trapping agent are exchanged for halogen ions. Ion trapping agents trap halogen ions (e.g., Cl<sup>-</sup>) to form an ionic bond with a halogen ion to provide a non-reactive ion and a different consequent by-product. Anions that are exchanged ions. For example, the ion trapping agent exchanges reactive halogen ions for non-reactive ions at the same bonding (eg, ionic bonding) positions on the remaining portion of the compound forming the ion trapping agent. For example, the ion trapping agent is hydrotalcite-like compound (HTlc). A hydrotalcite-like compound (HTlc) is expressed by the following formula.
[Mg<sub>1-x</sub> Al<sub>x</sub>(OH)<sub>2</sub>]<sup>x+</sup>[A<sub>x/n</sub><sup>n-.</sup>mH<sub>2</sub>O]<sup>x</sup>(where 0<x<0.33 and A<sup>n-</sup>is an exchangeable anion with a valence of n. )
As another example, the first inorganic filler 312 includes particles that adsorb and trap reactive substances on the surfaces of the particles of the first inorganic filler 312 by physical adsorption without chemical reaction. The first inorganic filler 312 is formed of 100% of the described trapping particles. However, the first inorganic filler 312 may be other substances (eg, silicon oxide (SiO<sub>2</sub>) and aluminum oxide (Al<sub>2</sub>O<sub>3</sub>)) and trapping particles. For example, the trap particle size is 1 nm. The trap particle size is greater than 5 μm. The trap particle size is no larger than 20% of the thickness of the first polymer film 311 .
A first lower insulating layer 320 is formed on the first upper insulating layer 310 . The first lower insulating layer 320 is formed by a deposition or coating process. The first lower insulating layer 320 contains a photosensitive polymer. For example, the photosensitive polymer is at least one of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene polymer (BCB). including one. The first lower insulating layer 320 is the same photosensitive polymer as the first polymer film 311, but is not limited thereto.
The photopolymers described herein are polymers that react to light to change the chemical composition of the polymer and/or react to light with one or more photopolymer substances to change the chemical composition of the polymer. Contains photoinitiators that change. For example, the photoinitiator is a photoacid generator (PAG) and the photopolymer film comprises one or more polymers and a photoacid generator. When the photopolymer material is exposed to light, the chemical composition of the polymers of the photopolymer material changes.
The first lower insulating layer 320 does not contain ion trapping agents such as inorganic fillers that react with reactive substances (eg, chloride ions). For example, the first lower insulating layer 320 does not contain inorganic fillers (particles) such as magnesium (Mg) compounds, alabamine (Ab) compounds, and bismuth (Bi) compounds. The thickness T2 of the first lower insulating layer 320 is thicker than the thickness T1 of the first upper insulating layer 310. As shown in FIG. For example, the thickness T1 of the first upper insulating layer 310 is 10% to 70% of the thickness T2 of the first lower insulating layer 320. FIG.
No conductive components (eg, rewiring patterns or conductive patterns) are interposed between the first lower insulating layer 320 and the first upper insulating layer 310 . The first lower insulating layer 320 is directly formed on the first upper insulating layer 310 and directly contacts the first upper insulating layer 310 without any intervening material. The forming process of the first upper insulating layer 310 and the first lower insulating layer 320 includes forming the first upper insulating layer 310 and then directly forming the first lower insulating layer 320 on the first upper insulating layer 310. .
In the above process, the first upper insulating layer 310 is the lower layer and the first lower insulating layer 320 is the upper layer. Note that the terms "upper" and "lower" (with respect to first upper insulating layer 310, first lower insulating layer 320, and other layers) are generally consistent with the drawings, but "upper" and "lower" The terms "bottom" (and similar "above", "below", "left", "right" terms) are generally a component of embodiments rather than indicating device orientation in the real world. is chosen to relatively describe the position of Unless otherwise stated, the use of numbers such as "first", "second", etc. are used to distinguish between components rather than to indicate order or position. For example, a "second" component described elsewhere may correspond to a "first" component described elsewhere, and vice versa.
Referring to FIG. 3A, a first opening (aperture) 335 is formed in the first upper insulating layer 310 and the first lower insulating layer 320 . A first opening 335 passes through the first upper insulating layer 310 and the first lower insulating layer 320 . A first opening 335 exposes the chip pad 110 . The process of forming the first opening 335 will be described in more detail below.
FIG. 3B is an explanatory view showing an example of the forming process of the first opening according to the present embodiment, and is an enlarged view of area A in FIG. 3A. FIG. 3C is an enlarged view of region B in FIG. 3B.
3A, 3B, and 3C, the first lower insulating layer 320 and the first upper insulating layer 310 are patterned. The first polymer film 311 of the first upper insulating layer 310 contains a photosensitive polymer. The patterning of the first lower insulating layer 320 and the first upper insulating layer 310 is performed by exposure and development processes.
The exposure process is a general photolithographic exposure process, in which selectively exposed portions of the first lower insulating layer 320 and the first upper insulating layer 310 (for example, using a photolithographic mask) are irradiated with light. , causing a chemical change in the photosensitive polymer film (eg, the photoacid generator in the photosensitive polymer film) of the first lower insulating layer 320 and the first upper insulating layer 310 . For example, the light is extreme ultraviolet light.
The developing process selectively removes the portions of the first lower insulating layer 320 and the first upper insulating layer 310 exposed to light with a positive tone developer (or selectively removes the portions not exposed to light with a negative tone developer). remove). The first polymer film 311 of the first upper insulating layer 310 contains the same material as the photosensitive polymer of the first lower insulating layer 320 . The first upper insulating layer 310 and the first lower insulating layer 320 are patterned in a single process. For example, without removing the device from the chamber, and with the same developer and the same etchant in the same chamber without vacuum break.
The first inorganic filler 312 reflects or scatters light. First lower insulating layer 320 does not contain an inorganic filler. The transmittance of the first lower insulating layer 320 is greater than the transmittance of the first upper insulating layer 310 . In this embodiment, after the first upper insulating layer 310 is formed, a first lower insulating layer 320 is formed on the first upper insulating layer 310 . Therefore, the first lower insulating layer 320 is well exposed.
If the thickness T1 of the first upper insulating layer 310 is thicker than 70% of the thickness T2 of the first lower insulating layer 320, the chip pad 110 is difficult to expose. In this case, if the desired area of the first opening 335 is small, the patterning precision of the first upper insulating layer 310 and the first lower insulating layer 320 will be low, making it difficult to expose the chip pad 110 . In this embodiment, the thickness T1 of the first upper insulating layer 310 is less than 70% of the thickness T2 of the first lower insulating layer 320, so the first opening 335 is easily formed. The thickness T1 of the first upper insulating layer 310 is less than 20 μm.
As shown in FIG. 3C, sidewalls 310c of first upper insulating layer 310 within first opening 335 are relatively smooth. For example, the surface roughness of the sidewalls 310c of the first upper insulating layer 310 is the same as or similar to the surface roughness of the sidewalls 320c of the first lower insulating layer 320. FIG. Also, the sidewall 310c of the first upper insulating layer 310 and the sidewall 320c of the first lower insulating layer 320 in the first opening 335 have a tapered shape widening from the chip pad 110 toward the first lower insulating layer 320. As shown in FIG. After the developing process, as shown in FIG. 3B, remnants of the first lower insulating layer 320 and/or remnants (not shown) of the first upper insulating layer 310 are present in the first openings 335 as indicated by dotted lines. remain. A process of removing residues of the first lower insulating layer 320 and/or residues of the first upper insulating layer 310 is further performed.
3D and 3E are explanatory views showing another example of the first opening forming process according to the present embodiment, and are enlarged views of area A in FIG. 3A. FIG. 3F is an enlarged view of region B in FIG. 3E.
3A and 3D, the first lower insulating layer 320 is patterned to expose the first upper insulating layer 310. Referring to FIG. The patterning of the first lower insulating layer 320 proceeds through exposure and development processes. For example, exposure is a photolithographic exposure process. After selective exposure through photolithography of the first lower insulating layer 320, a development step is performed using a positive tone developer or a negative tone developer. The first polymer film 311 contains a non-photosensitive polymer and does not contain any photosensitive polymer. Also, the first polymer film 311 does not contain other chemical compositions/substances that change upon exposure to light. After the patterning process of the first lower insulating layer 320 , the first lower insulating layer 320 exposes the first upper insulating layer 310 . A residue 325 of the first lower insulating layer 320 remains on the first upper insulating layer 310 .
3A, 3E, and 3F, an etching process is performed on the first upper insulating layer 310 to remove the remnants 325 of the first lower insulating layer 320. As shown in FIG. Etching process is CF<sub>4</sub>, or a plasma etching process using argon gas. The first lower insulating layer 320 has etch selectivity with respect to the first upper insulating layer 310 . The first upper insulating layer 310 exposed by the first lower insulating layer 320 is removed by an etching process. The etching process is continued until the chip pad 110 is exposed. Thus, a first opening 335 is formed.
Since the thickness T1 of the first upper insulating layer 310 is less than 70% of the thickness T2 of the first lower insulating layer 320, the first opening 335 is easily formed. Since the first upper insulating layer 310 is etched while the residue 325 of the first lower insulating layer 320 is removed, a separate patterning process for the first upper insulating layer 310 is omitted. Therefore, the manufacturing process of the semiconductor package is simplified. Since the first lower insulating layer 320 is formed on the first upper insulating layer 310, the step of removing the residue 325 of the first lower insulating layer 320 can be performed in a single step with the etching step of the first upper insulating layer 310. carried out. For example, without removing the device from the chamber, and with the same developer and the same etchant in the same chamber without vacuum break.
The sidewalls 310c of the first upper insulating layer 310 and the sidewalls 320c of the first lower insulating layer 320 are exposed by the first openings 335, as shown in FIG. 3F. Since the first upper insulating layer 310 is patterned by a different process than the first lower insulating layer 320, the sidewalls 310c of the first upper insulating layer 310 have different surface roughness than the sidewalls 320c of the first lower insulating layer 320. have For example, the first upper insulating layer 310 is patterned by an etching process, so it is relatively rough. The surface roughness of the sidewalls 310c of the first upper insulating layer 310 is greater than the surface roughness of the sidewalls 320c of the first lower insulating layer 320. As shown in FIG.
4A, 4B and 4C, a first redistribution pattern 330 is formed in the first opening 335 and on the first lower insulating layer 320. Referring to FIG. The first rewiring pattern 330 is formed of a patterned conductive layer. The first redistribution pattern 330 penetrates the first upper insulating layer 310 and the first lower insulating layer 320 . The first rewiring pattern 330 is connected to the chip pad 110 and arranged as an electrical path between the chip pad 110 and terminals (eg, solder bumps) of the semiconductor package. For example, the first redistribution pattern 330 is directly connected to the chip pad 110 .
The first rewiring pattern 330 includes a via portion 330A and a wiring portion 330B. A via portion 330A of the first redistribution pattern 330 is formed within the first opening 335 . Via portion 330A provides vertical electrical connection. A wiring portion 330B of the first rewiring pattern 330 is disposed on the first lower insulating layer 320. As shown in FIG. Wiring portion 330B extends horizontally to provide electrical connection. The wiring portion 330B of the first rewiring pattern 330 is connected to the via portion 330A. The wiring portion 330B is integrally formed with the via portion 330A and is made of the same conductive material as the via portion 330A. The via portion 330A has a tapered shape in which the width of the via on the chip pad 110 is smaller than the width of the via on the wiring portion 330B.
Referring to FIG. 4B as an example of this embodiment, the first redistribution pattern 330 is disposed within the first opening 335 formed as shown in FIGS. 3B and 3C.
As another example, referring to FIG. 4C, the first redistribution pattern 330 is placed in a first opening 335 formed as shown in FIGS. 3D-3F. The sidewalls (310c in FIG. 3F) of the first upper insulating layer 310 are rough, and the first redistribution pattern 330 covers the sidewalls 310c of the first upper insulating layer 310. As shown in FIG. In order to simplify the description, the first opening 335 manufactured as shown in FIGS. 3B and 3C will be illustrated in this specification. However, the first opening 335 shown in Figures 3E and 3F applies equally well to other embodiments. Below, the step of forming the first rewiring pattern will be described in more detail.
4D and 4E are diagrams showing the process of forming the first rewiring pattern according to the present embodiment, and are enlarged views of area A in FIG. 4A.
Referring to FIG. 4D, a seed pattern 331 is conformally formed on the first lower insulating layer 320 and within the first opening 335 . The seed pattern 331 extends over the sidewalls of the first lower insulating layer 320 and the sidewalls of the first upper insulating layer 310 exposed by the first openings 335 to cover the chip pads 110 . A mask pattern 339 is formed on the seed pattern 331 . Mask pattern 339 exposes a portion of seed pattern 331 . An electroplating process is performed using the seed pattern 331 as an electrode to form a conductive pattern 333 . A conductive pattern 333 is selectively formed on the seed pattern 331 exposed by the mask pattern 339 . Conductive pattern 333 includes a metal such as copper. After that, mask pattern 339 is removed to expose a portion of seed pattern 331 covered by mask pattern 339 .
Referring to FIG. 4E, the exposed seed pattern 331 is removed by an etching process to form a first redistribution pattern 330. Referring to FIG. A portion of the first lower insulating layer 320 is exposed after the etching process. Conductive pattern 333 has etch selectivity to seed pattern 331 . For example, conductive pattern 333 has a lower etch rate than seed pattern 331 . The first redistribution pattern 330 includes seed patterns 331 and conductive patterns 333 .
For the sake of convenience, the figures excluding FIGS. 4D and 4E do not show the seed pattern 331 and the conductive pattern 333 separately. However, the first redistribution pattern 330, which is described and illustrated elsewhere, is formed similarly to FIGS. 4D and 4E. Another rewiring pattern is also formed of a patterned conductive layer, has the same material and structure as those described for the first rewiring pattern 330, and is formed in the same process as the first rewiring pattern 330. FIG.
5A and 5B, a second upper insulating layer 340 and a second lower insulating layer 350 are formed on the first lower insulating layer 320 in sequence. A second upper insulating layer 340 covers the first lower insulating layer 320 and the first redistribution pattern 330 . A second upper insulating layer 340 includes a second polymer film 341 and a second inorganic filler 342 . The second upper insulating layer 340 is formed in the same manner as the first upper insulating layer 310 and includes the same material. A second inorganic filler 342 is dispersed within the second polymer film 341 . Second polymer film 341 includes at least one of the materials described in the examples of first polymer film 311 shown in FIGS. 2A and 2B. For example, the second inorganic filler 342 includes at least one of a magnesium (Mg) compound, an alabamine (Ab) compound, and a bismuth (Bi) compound. The second polymer film 341 contains a photosensitive polymer. As another example, second polymer film 341 includes a non-photosensitive polymer. Second inorganic filler 342 includes at least one of the substances described in the examples of first inorganic filler 312 . The second upper insulating layer 340 is formed by a deposition or coating process as described in the example of the first upper insulating layer 310 .
A second lower insulating layer 350 covers the second upper insulating layer 340 . The second lower insulating layer 350 contacts the second upper insulating layer 340 . A second lower insulating layer 350 comprises a photosensitive polymer as previously described. The second lower insulating layer 350 is the same photosensitive polymer as the first lower insulating layer 320 . The second lower insulating layer 350 is the same photosensitive polymer as the second polymer film 341, but is not limited thereto.
Second lower insulating layer 350 does not contain an inorganic filler. The transmittance of the second lower insulating layer 350 is greater than the transmittance of the second upper insulating layer 340 . The thickness of the second lower insulating layer 350 is thicker than the thickness of the second upper insulating layer 340 . For example, the thickness of the second upper insulating layer 340 is 10% to 70% of the thickness of the second lower insulating layer 350 . The thickness of the second lower insulating layer 350 and the thickness of the second upper insulating layer 340 are set to the thicknesses described for the thickness T2 of the first lower insulating layer 320 and the thickness T1 of the first upper insulating layer 310, respectively. be done. The thickness of the second lower insulating layer 350 and the thickness of the second upper insulating layer 340 are substantially the same as the thickness T2 of the first lower insulating layer 320 and the thickness T1 of the first upper insulating layer 310, respectively. . Alternatively, the thickness of the second lower insulating layer 350 and the thickness of the second upper insulating layer 340 may be different from the thickness T2 of the first lower insulating layer 320 and the thickness T1 of the first upper insulating layer 310. FIG. The second lower insulating layer 350 is formed by a deposition or coating process.
6A and 6B, a second opening 365 is formed in the second lower insulating layer 350 and the second upper insulating layer 340. As shown in FIG. The second opening 365 penetrates the second lower insulating layer 350 and the second upper insulating layer 340 to expose the first redistribution pattern 330 . The second opening 365 is formed by substantially the same method as the example of forming the first opening 335 shown in FIGS. 3B and 3C or the example of forming the first opening 335 shown in FIGS. 3D to 3F. . A second rewiring pattern 360 is formed in the second opening 365 .
The second rewiring pattern 360 is connected to the first rewiring pattern 330 . The second rewiring pattern 360 includes via portions 360A and wiring portions 360B. The wiring portion 360B is, for example, a horizontal wiring pattern extending over the second lower insulating layer 350. As shown in FIG. The second rewiring pattern 360 is substantially the same as the method of forming the first rewiring pattern 330 described with reference to FIGS. 4A to 4E, and has the same material and connection relationship as the first rewiring pattern 330. . For example, the second redistribution pattern 360 is formed by forming a seed pattern (not shown) on the second opening 365 and the second lower insulating layer 350 and then performing an electroplating process using the seed pattern. The second rewiring pattern 360 contains copper, but is not limited thereto.
A third upper insulating layer 370 is formed over the second lower insulating layer 350 . The third upper insulating layer 370 includes a third polymer film 371 and a third inorganic filler 372, as shown in FIG. 6B. A third upper insulating layer 370 is formed in the same manner as the first upper insulating layer 310 and includes the same material as the first upper insulating layer 310 . The third inorganic filler 372 includes a plurality of particles dispersed within the third polymer film 371 . Third polymer film 371 includes at least one of the materials described in the examples of first polymer film 311 in FIGS. 2A and 2B. Third polymer film 371 comprises a photosensitive polymer as previously described. As another example, third polymer film 371 comprises a non-photosensitive polymer. Third inorganic filler 372 includes at least one of the substances described in the examples of first inorganic filler 312 .
A third lower insulating layer 380 is formed over the third upper insulating layer 370 . A third lower insulating layer 380 contacts the third upper insulating layer 370 . A third lower insulating layer 380 comprises a photosensitive polymer as previously described. The third lower insulating layer 380 includes the same photosensitive polymer as the first lower insulating layer 320 and the same photosensitive polymer as the third polymer film 371, but is not limited thereto. Third lower insulating layer 380 does not contain an inorganic filler. The transmittance of the third lower insulating layer 380 is greater than the transmittance of the third upper insulating layer 370 . The thickness of the third lower insulating layer 380 is thicker than the thickness of the third upper insulating layer 370 . For example, the thickness of the third upper insulating layer 370 is 10% to 70% of the thickness of the third lower insulating layer 380. FIG. The thickness of the third lower insulating layer 380 and the thickness of the third upper insulating layer 370 are set to the thicknesses described for the thickness T2 of the first lower insulating layer 320 and the thickness T1 of the first upper insulating layer 310, respectively. be done. The third lower insulating layer 380 and the third upper insulating layer 370 are formed by a deposition process or a coating process as described above.
A third opening 395 penetrates the third lower insulating layer 380 and the third upper insulating layer 370 to expose the second redistribution pattern 360 . A third rewiring pattern 390 is formed in the third opening 395 . The third redistribution pattern 390 includes a conductive material such as copper. Although not shown, the third rewiring pattern 390 is further horizontally extended on the third lower insulating layer 380 (eg, horizontal wiring). The third rewiring pattern 390 includes the same material and has the same electrical connection as those described with reference to FIGS. 4A to 4E.
A connection pad 410 and a connection terminal 400 are formed on the third redistribution pattern 390 . A connection pad 410 is formed between the connection terminal 400 and the third rewiring pattern 390 . The connection terminal 400 is electrically connected to the third rewiring pattern 390 . The connection terminal 400 is connected to the chip pad 110 through each rewiring pattern (330, 360, 390). The connection terminal 400 does not overlap the chip pad 110 in plan view. For example, the connection terminals 400 are not aligned with the chip pads 110 along the second direction D2.
As shown in FIG. 6A, a plurality of connection terminals 400 are arranged, and at least one of the connection terminals 400 overlaps the mold film 200 in plan view. At least one of the connection terminals 400 is directly arranged under the mold film 200 . By arranging the rewiring patterns 330 , 360 , 390 , the connection terminals 400 can be arranged more freely regardless of the arrangement of the chip pads 110 .
Each redistribution pattern (330, 360, 390) includes a plurality of separate wires that are electrically isolated from each other (i.e., the separate wires are electrically connected to the chip pad 110). transfer other signals and/or voltages between the coupling terminals 400). Even if a wiring portion (for example, 360B) is illustrated as a wiring extending horizontally in the cross section in the horizontal direction, each wiring extends in another horizontal direction (for example, a direction perpendicular to the cross section) and is non-linear. A shaped path (eg, zigzag) provides electrical connection between the connection terminal 400 and the chip pad 110 . A separate wire provides yet another electrical connection between the connection terminal 400 and the chip pad 110 .
Here, another electrical connection is between the connection terminal 400 and another package stacked on the semiconductor package 1, or between the chip pad 110 of the semiconductor chip 100 and another package stacked on the semiconductor package 1 ( For example, see FIGS. 10B and 10C)/electrical connections between other semiconductor chips in the semiconductor package 1. FIG. The connection terminals 400 may include solder balls, bumps, or pillars. The connection terminal 400 includes a conductive material such as metal.
The manufacturing of the semiconductor package 1 is completed by the manufacturing example described above.
Heat is generated in the semiconductor chip 100 during operation of the semiconductor package 1 . Each inorganic filler (312, 342, 372) has a higher thermal conductivity than each polymer film (311, 341, 371) and each lower insulating layer (320, 350, 380). By providing the inorganic fillers (312, 342, 372), the heat dissipation characteristics of the semiconductor chip 100 are improved. In some embodiments, each inorganic filler (312, 342, 372) comprises different types of particles, such as a first type comprising ion trapping agents and a second type comprising heat emitting particles. The heat emitting particles have a higher thermal conductivity than each polymer film (311, 341, 371) and each lower insulating layer (320, 350, 380). In some embodiments, the particles of each inorganic filler (312, 342, 372) comprise ion trapping agents and heat emitting particles as previously described.
Coefficient of thermal expansion of the entire redistribution layer 300 shown in FIG. 6A expansion) is different from the thermal expansion coefficient of the semiconductor chip 100 . For example, the thermal expansion coefficient of each rewiring pattern (330, 360, 390) is larger than that of the semiconductor chip 100. FIG. If the difference in thermal expansion coefficient between the rewiring layer 300 and the semiconductor chip 100 increases, the semiconductor package 1 will warp. In this embodiment, each of the first to third inorganic fillers (312, 342, 372) has a thermal expansion coefficient smaller than that of the first to third polymer films (311, 341, 371). Each inorganic filler (312, 342, 372) has a smaller coefficient of thermal expansion than each lower insulating layer (320, 350, 380). For example, each inorganic filler (312, 342, 372) has a thermal expansion coefficient of about 2 ppm/°C to about 20 ppm/°C. By including the inorganic fillers (312, 342, 372) in the rewiring layer 300, the difference in thermal expansion coefficient between the rewiring layer 300 and the semiconductor chip 100 is reduced. Therefore, warpage of the semiconductor package 1 is prevented in the manufacturing process of the semiconductor package 1 . In some embodiments, as shown in FIGS. 6A and 6B, the redistribution layer 300 includes each upper insulating layer (310, 340, 370), each lower insulating layer (320, 350, 380), and each redistribution layer. Includes wiring patterns (330, 360, 390).
The number of upper insulating layers 310, 340, 370, lower insulating layers 320, 350, 380, and rewiring patterns 330, 360, 390 may vary. For example, a fourth upper insulating layer, a fourth lower insulating layer, and a fourth rewiring pattern (not shown) are further formed between the third lower insulating layer 380 and the connection terminal 400 . Alternatively, the third upper insulating layer 370, the third lower insulating layer 380, and the third redistribution pattern 390 may be omitted. As another example, at least one of the first to third upper insulating layers (310, 340, 370) may be omitted.
7A and 7B are cross-sectional views showing manufacturing steps of a semiconductor package according to an embodiment of the present invention. In the following, the content overlapping with the previous description will be omitted.
Referring to FIG. 7A, semiconductor chip 100 is placed on carrier substrate 910 . A plurality of semiconductor chips 100 are arranged. A mold film 200 covers the semiconductor chip 100 on the carrier substrate 910 . The carrier substrate 910 is then removed to expose the bottom surface 200b of the mold film 200 and the bottom surface 100b of the semiconductor chip 100. FIG.
7B, a redistribution layer 300 is formed on the exposed lower surface 200b of the mold layer 200 and the exposed lower surface 100b of the semiconductor chip 100. Referring to FIG. The redistribution layer 300 includes upper insulating layers (310, 340, 370), lower insulating layers (320, 350, 380), and redistribution patterns (330, 360, 390). The rewiring layer 300 is formed by the same method as described with reference to FIGS. 1 to 6B. However, the redistribution layer 300 is formed at the panel level or the wafer level, and multiple redistribution layers 300 are simultaneously formed into a single integrated layer in the semiconductor package.
The single unitary layers of the multiple redistribution layers 300 of the semiconductor package are separated from each other by singulating or cutting the semiconductor package from the single unitary structure as shown in FIG. 7B. On the other hand, the semiconductor package may not be cut from a single unitary structure (eg, when forming a display made up of multiple LED chips).
FIG. 7A shows a state in which a plurality of semiconductor chips 100 are substantially simultaneously covered with a mold film 200 through a molding process. A molding process is performed after the plurality of semiconductor chips 100 are mounted on the carrier substrate 910 . The carrier substrate 910 is then removed as indicated by the dashed lines in Figure 7A. As shown in FIG. 7B, multiple redistribution layers 300 are formed in a single unitary structure to form each semiconductor package. Here, each semiconductor package corresponds to each semiconductor chip 100, but also to a plurality of semiconductor chips 100, which are stacked or attached on a carrier substrate 910 and arranged horizontally. is a group. A connection pad 410 and a connection terminal 400 are formed on the bottom surface of the redistribution layer 300 .
A plurality of semiconductor packages 1 are formed simultaneously, and initially formed into a single unitary structure as shown in FIG. 7B. The mold film 200 and the rewiring layer 300 are sawed along the dashed line shown in FIG. 7B to separate the plurality of semiconductor packages 1 from each other.
7A and 7B show an example in which the semiconductor package 1 is manufactured at the panel level. However, the semiconductor package 1 is manufactured at the chip level. For example, semiconductor packages are formed individually. For example, a mold film 200 is individually formed on each semiconductor package. Also, the semiconductor package 1 can be manufactured at the wafer level. For example, the semiconductor chips 100 are formed on a semiconductor wafer, and the rewiring layer 300 is formed before the semiconductor chips 100 are separated from the semiconductor wafer. After that, the semiconductor chips 300 corresponding to each rewiring layer 300 are separated from each other. In the following, a single semiconductor package 1 will be illustrated and described for simplification of explanation.
8A to 8D are explanatory views showing a semiconductor package manufacturing method according to another embodiment of the present invention. In the following, the content overlapping with the previous description will be omitted.
Referring to FIG. 8A, a first upper insulating layer 310 and a first lower insulating layer 320 are formed on a first carrier substrate 910'. The first upper insulating layer 310 includes a first polymer film 311 and a first inorganic filler 312 as shown in FIG. 6B. A first lower insulating layer 320 covers the first upper insulating layer 310 . The first lower insulating layer 320 contains a photosensitive polymer. A first opening 335 is formed in the first upper insulating layer 310 and the first lower insulating layer 320 . A first opening 335 exposes the first carrier substrate 910'. The method of forming the first opening 335 is the same as the method of forming the first opening 335 shown in FIGS. 3B to 3C or the example of forming the first opening 335 shown in FIGS. 3D to 3F. A first redistribution pattern 330 is formed in the first opening 335 and on the first lower insulating layer 320 .
A second upper insulating layer 340 and a second lower insulating layer 350 are formed on the first lower insulating layer 320 . A second opening 365 is formed to expose the first redistribution pattern 330 . A second opening 365 passes through the second upper insulating layer 340 and the second lower insulating layer 350 . A second redistribution pattern 360 is formed in the second opening 365 and on the second lower insulating layer 350 .
A third upper insulating layer 370 and a third lower insulating layer 380 are formed on the second lower insulating layer 350 . A third opening 395 is formed in the third upper insulating layer 370 and the third lower insulating layer 380 . A third opening 395 passes through the third upper insulating layer 370 and the third lower insulating layer 380 . A third rewiring pattern 390 is formed in the third opening 395 and connected to the second rewiring pattern 360 . Thus, the rewiring layer 300 is manufactured. The redistribution layer 300 includes upper insulating layers (310, 340, 370), lower insulating layers (320, 350, 380), and redistribution patterns (330, 360, 390).
Referring to FIG. 8B, a second carrier substrate 920 is deposited over the third lower insulating layer 380. As shown in FIG. The first carrier substrate 910' is then removed to expose the first upper insulating layer 310 and the first redistribution pattern 330. As shown in FIG.
Referring to FIG. 8C, the semiconductor chip 100 is disposed on the redistribution layer 300 and electrically connected to the redistribution layer 300. Referring to FIG. In this specification, being electrically connected to the redistribution layer 300 means being electrically connected to each redistribution pattern (330, 360, 390) of the redistribution layer 300. FIG.
According to this embodiment, conductive pads 160 are formed on the exposed first redistribution pattern 330 after the first carrier substrate 910' shown in FIG. 8B is removed. As another example, prior to forming the first redistribution pattern 330 in FIG. do. The semiconductor chip 100 is arranged on the first upper insulating layer 310 such that the chip pads 110 of the semiconductor chip 100 face the rewiring layer 300 . At this time, the connection part 150 is formed between the chip pad 110 and the conductive pad 160 . Connections 150 may include solder, solder pillars, or solder bumps. The connection part 150 is electrically connected to the chip pad 110 and the conductive pad 160 . Therefore, the semiconductor chip 100 is electrically connected to each rewiring pattern (330, 360, 390).
A mold film 200 is formed on the redistribution layer 300 , for example, the first upper insulating layer 310 to cover the semiconductor chip 100 . Unlike the figure, the mold film 200 covers the sides of the semiconductor chip 100, but may expose the top surface.
The mold layer 200 further extends to the gap between the semiconductor chip 100 and the redistribution layer 300 to seal the connection part 150 . The second carrier substrate 920 is then removed to expose portions of the third lower insulating layer 380 and the third redistribution pattern 390 .
8D, connection pads 410 and connection terminals 400 are formed on the bottom surface of the redistribution layer 300. Referring to FIG. The connection terminal 400 is electrically connected to the third rewiring pattern 390 . As described above, the semiconductor package 2 is manufactured.
FIG. 9 is a cross-sectional view showing a second example of a semiconductor package according to one embodiment of the invention. In the following, the content overlapping with the previous description will be omitted.
Referring to FIG. 9, the semiconductor package 3 includes a rewiring layer 300 and a semiconductor chip 100. As shown in FIG. However, unlike the semiconductor package 1 shown in FIG. 6A and the semiconductor package 2 shown in FIG. 8D, the mold film 200 is omitted. The width W1 of the semiconductor chip 100 is substantially the same as the width W2 of the rewiring layer 300. FIG.
First upper insulating layer 310, first lower insulating layer 320, first rewiring pattern 330, second upper insulating layer 340, second lower insulating layer 350, second rewiring pattern 360, third upper insulating layer 370, A third lower insulating layer 380 and a third rewiring pattern 390 are formed on the bottom surface 100b of the semiconductor chip 100 to form the entire rewiring layer 300 . A first upper insulating layer 310 is disposed between the first lower insulating layer 320 and the semiconductor chip 100 .
As another example, the semiconductor package 3 is manufactured by substantially the same method as the method described with reference to FIGS. 8A to 8C. Mold film 200 is not formed. In this case, a connecting portion (150 in FIG. 8D) is further formed between the chip pad 110 and the first rewiring pattern 330. FIG.
FIG. 10A is a plan view showing a third example of a semiconductor package according to one embodiment of the present invention; FIG. 10B is a cross-sectional view taken along line I-II shown in FIG. 10A. In the following, the content overlapping with the previous description will be omitted.
10A and 10B, the semiconductor package 4 includes a wiring substrate 500 in addition to the rewiring layer 300, the semiconductor chip 100, and the mold film 200. FIG. The rewiring layer 300, the semiconductor chip 100, and the mold film 200 are substantially the same as those previously described.
The wiring substrate 500 includes a base layer 510 and conductive structures 520 within the base layer 510 . As an example, a printed circuit board PCB is used as the wiring board 500 . Conductive structure 520 includes a plurality of isolated conductive traces. Conductive structure 520 includes lower metal pattern 521 , middle metal pattern 522 , via 523 and upper metal pattern 524 . The lower metal pattern 521 is exposed on the lower surface of the wiring board 500. FIG. A via 523 extends through at least one of the base layers 510 . Intermediate metal patterns 522 are interposed between base layers 510 and connected to vias 523 . The upper metal pattern 524 is exposed on the top surface of the wiring board 500 . Upper metal pattern 524 is electrically connected to lower metal pattern 521 through intermediate metal pattern 522 and via 523 . The upper metal pattern 524 is not aligned with the lower metal pattern 521 in the second direction D2. The number of upper metal patterns 524 is different from the number of lower metal patterns 521 . Unlike the illustration, the intermediate metal pattern 522 may be omitted and the upper metal pattern 524 may be aligned with the lower metal pattern 521 in the second direction D2.
The wiring board 500 further includes passive elements (not shown) therein. The passive elements are electrically connected to at least one wiring of the wiring board 500 . Passive elements include capacitors, resistors, or inductors.
Semiconductor chip 100 is placed in cavity 590 of wiring substrate 500 . Cavity 590 penetrates wiring board 500 . A mold layer 200 is formed on the entire rewiring layer 300 to cover the top surfaces of the semiconductor chip 100 and the wiring substrate 500 . Mold film 200 extends to the gap between wiring substrate 500 and semiconductor chip 100 . A hole 250 is then formed in the mold film 200 to expose the top metal pattern 524 . As another example, solder balls (not shown) are further disposed on top metal pattern 524 and exposed by holes 250 .
The rewiring layer 300 is formed on the lower surface 100b of the semiconductor chip 100 and the lower surface of the wiring substrate 500. As shown in FIG. The redistribution layer 300 has a structure as previously described and is formed as previously described. The redistribution layer 300 includes upper insulating layers (310, 340, 370), lower insulating layers (320, 350, 380), and redistribution patterns (330, 360, 390).
First rewiring pattern 330 includes a plurality of first rewiring patterns 330 . A portion of the first redistribution pattern 330 is disposed between the corresponding chip pad 110 and the lower metal pattern 521 of the first semiconductor chip 100 and electrically connected to the chip pad 110 and the lower metal pattern 521 . be. For example, one of the first rewiring patterns 330 is connected to the chip pad 110 and the other one of the first rewiring patterns 330 is connected to the lower metal pattern 521 . The other one of the first rewiring patterns 330 is connected to the chip pad 110 and the lower metal pattern 521 (not shown).
Each redistribution pattern (330, 360, 390) is connected to each other to form an isolated wiring of the redistribution layer 300. FIG. The wires are electrically connected between corresponding chip pads 110 and corresponding connection pads 410 and/or connection terminals 400 . Alternatively, the wiring is electrically connected between the corresponding lower metal pattern 520 and the corresponding connection pad 410 and/or connection terminal 400 . Some of the wires are electrically connected to the chip pad 110 and other electrical components of the semiconductor chip 100, and some of the wires are connected to the chip pad 110 and other electrical components of the semiconductor chip 100. Not electrically coupled.
The wiring board 500 is electrically connected to at least one of the connection terminal 400, the semiconductor chip 100, and the lower metal pattern 521 through each rewiring pattern (330, 360, 390). The rewiring layer 300 is formed by the method described with reference to FIGS. 2 to 6B. As another example, redistribution layer 300 is formed using the method described in the example of FIGS. 8A-8C. In this case, although not shown, the connection portion (150 in FIG. 8B) includes a plurality of connection portions 150, and the connection portion 150 is between the chip pad 110 and one of the first rewiring patterns 330, and the lower portion thereof. It is interposed between the metal pattern 521 and one of the first rewiring patterns 330 .
FIG. 10C is a cross-sectional view showing a fourth example of the semiconductor package according to one embodiment of the present invention, and is a cross-sectional view taken along line I-II shown in FIG. 10A. In the following, the content overlapping with the previous description will be omitted.
10A and 10C, the semiconductor package 6 includes a first semiconductor package 4' and a second semiconductor package 5. As shown in FIG. The first semiconductor package 4' is substantially the same as the semiconductor package 4 described with reference to FIGS. 10A and 10B. For example, the first semiconductor package 4' includes a rewiring layer 300, a semiconductor chip 100, a wiring substrate 500, and a mold film 200. FIG. A second semiconductor package 5 is arranged on the first semiconductor package 4'.
The second semiconductor package 5 includes a package substrate 710, a semiconductor device 720 and a mold film 730. As shown in FIG. Package substrate 710 is a printed circuit board. As another example, the rewiring layer 300 manufactured as in the examples of FIGS. 2 to 6B or the examples of FIGS. 8A to 8C is used as the package substrate 710. FIG. The structure of the first semiconductor package 5 is the same as the semiconductor packages described in other embodiments. A metal pad 711 is disposed on the bottom surface of the package substrate 710 . A semiconductor device 720 is placed on a package substrate 710 . Semiconductor device 720 may include memory chips, logic chips, or a combination thereof. The semiconductor device 720 is electrically connected to the metal pads 711 through internal conductive lines within the package substrate 710, as indicated by dotted lines.
In FIG. 10C, dotted lines within package substrate 710 schematically indicate internal conductive lines within package substrate 710 . The electrical connection of the lower metal pattern 521 is extended to the corresponding metal pads 711 and semiconductor elements 720 and applied to the metal pads 711 and semiconductor elements 720 . A mold film 730 covers the semiconductor device 720 on the package substrate 710 .
The solder pattern 600 is interposed between the upper metal pattern 524 and the metal pad 711 to connect the upper metal pattern 524 and the metal pad 711 . Therefore, the second semiconductor package 5 is electrically connected to the first semiconductor package 4' through the solder pattern 600. FIG. According to this embodiment, the metal pads 711 are arranged more freely by arranging the conductive structures 520 . Therefore, circuit patterns (not shown) in the package substrate 710 are arranged more freely.
11A to 11C are cross-sectional views showing a semiconductor package manufacturing method according to still another embodiment of the present invention. In the following, the content overlapping with the previous description will be omitted.
Referring to Figure 11A, a carrier substrate 910 is provided. A redistribution layer 300 is formed on the carrier substrate 910 . Formation of the redistribution layer 300 is performed by substantially the same method as described in FIG. 8A. The overall redistribution layer 300 includes upper insulating layers (310, 340, 370), lower insulating layers (320, 350, 380), and redistribution patterns (330, 360, 390). The third redistribution pattern 390 is exposed on the third lower insulating layer 380 . A conductive pad 161 is formed on the third redistribution pattern 390 and electrically connected to the third redistribution pattern 390 .
Referring to FIG. 11B, the semiconductor chip 100 is placed on the redistribution layer 300, eg, the third lower insulating layer 380. As shown in FIG. The third lower insulating layer 380 is closer to the semiconductor chip 100 than the third upper insulating layer 370 is. At this time, the chip pads 110 of the semiconductor chip 100 are aligned with the conductive pads 161 . A connection part 150 is formed between the chip pad 110 and the conductive pad 161 . The semiconductor chip 100 is electrically connected to each rewiring pattern 330, 360, 390 through the connection part 150. FIG. A mold film 200 is formed on the third lower insulating layer 380 to cover the semiconductor chip 100 . Unlike the illustration, the mold film 200 covers the sides of the semiconductor chip 100, but may expose the top surface. Mold layer 200 further extends to the gap between semiconductor chip 100 and third lower insulating layer 380 . After that, the carrier substrate 910 is removed to expose a portion of the first redistribution pattern 330 and the first upper insulating layer 310 .
11C, connection pads 410 and connection terminals 400 are formed on the bottom surface of the redistribution layer 300. Referring to FIG. A connection pad 410 is formed between the connection terminal 400 and the first redistribution pattern 330 . The connection terminal 400 is electrically connected to each rewiring pattern (330, 360, 390). By the above, the manufacture of the semiconductor package 7 is completed.
In this embodiment, the semiconductor package 7 further includes the wiring board 500 described with reference to FIGS. 10A and 10B. In this case, the redistribution layer 300 is further extended over the bottom surface of the wiring substrate 500 and electrically connected to the conductive structure 520 .
FIG. 12 is a cross-sectional view showing another example of a semiconductor package according to still another embodiment of the invention. In the following, the content overlapping with the previous description will be omitted.
Referring to FIG. 12, the semiconductor package 8 includes a rewiring layer 300 and a semiconductor chip 100. As shown in FIG. Mold film 200 is omitted. The width W1 of the semiconductor chip 100 is substantially the same as the width W2 of the rewiring layer 300. FIG.
The semiconductor package 8 is formed by substantially the same method as that described for forming the semiconductor package 7 in FIGS. 11A to 11C. However, the mold layer 200 is not formed, and the underfill layer 170 is further formed between the third lower insulating layer 380 and the semiconductor chip 100. FIG. An underfill film 170 seals the joint 150 . The underfill film 170 contains an epoxy-based polymer. The third lower insulating layer 380 is closer to the semiconductor chip 100 than the third upper insulating layer 370 is.
FIG. 13A is a cross-sectional view showing a semiconductor module according to one embodiment of the invention. FIG. 13B is an enlarged view of area A in FIG. 13A. In the following, the content overlapping with the previous description will be omitted.
13A and 13B, the semiconductor module 10 includes a module substrate 1000, an underfill film 2000, and a semiconductor package 1. FIG. Module substrate 1000 includes a printed circuit board. The module substrate 1000 has module pads 1100 on its top surface. The semiconductor package 1 is a semiconductor package manufactured as shown in FIGS. 1 to 6B. 8D, the semiconductor package 3 shown in FIG. 9, the semiconductor package 4 shown in FIGS. 10A and 10B, the semiconductor package 6 shown in FIG. 10C, the semiconductor package 7 shown in FIG. A semiconductor package 8 shown at 12 is mounted on the module substrate 1000 .
A connection terminal 400 is connected to the module pad 1100 . The semiconductor package 1 is electrically connected to the module substrate 1000 through the connection terminals 400 . An underfill film 2000 is interposed between the module substrate 1000 and the semiconductor package 1 to seal the connection terminals 400 . The underfill film 2000 physically contacts the rewiring layer 300 . The underfill film 2000 further extends over the sidewalls of the redistribution layer 300 . The underfill film 2000 is filled with liquid into the space between the module substrate 1000 and the semiconductor package 1 to surround the connection terminals 400 . The underfill film 2000 is then cured into a solid unitary encapsulant.
The underfill film 2000 includes an epoxy-based polymer and a reactive material 2100 as shown in Figure 13B. Reactive material 2100 includes chloride ions. Reactive material 2100 includes charged particles, such as ions. ions are chloride ions (Cl<sup>-</sup>), sodium ion (Na<sup>+</sup>), calcium ion (K<sup>+</sup>), hydroxide ion (OH<sup>-</sup>), and/or hydrogen ions (H<sup>+</sup>). Chloride ion (Cl<sup>-</sup>), sodium ion (Na<sup>+</sup>), and calcium ions (K<sup>+</sup>) are added to the epoxy-based polymer of the underfill film 2000 to help the underfill film 2000 flow and be evenly dispersed during the manufacturing process.
When a voltage or current is applied to the semiconductor module 10 , the reactive material 2100 inside the underfill film 2000 flows into the rewiring layer 300 . For example, when negatively charged chloride ions form the reactive material 2100, they are attracted toward the positive potential of the voltage source, causing the chloride ions and other materials (eg, epoxy-based ions) in the underfill film 2000 to It flows towards the positive potential of the voltage source. Upon contacting the chip pad 110 of the semiconductor chip 100, the reactive material 2100 chemically bonds with the material of the chip pad 110, damaging (eg, corroding) the chip pad 110. FIG. Chemical bonding and corrosion occurs at room temperature and/or the operating temperature of semiconductor chip 100 (eg, 60° C.).
At least one of each inorganic filler (312, 342, 372) includes an ion trapping agent. For example, each inorganic filler (312, 342, 372) includes a magnesium (Mg) compound, an alabamine (Ab) compound, or a bismuth (Bi) compound. In this case, each inorganic filler (312, 342, 372) captures or removes the reactive substance 2100 that has flowed into the rewiring layer 300. FIG.
For example, the compound produced by combining the reactive substance 2100 and the ion trapping agent does not chemically react with the chip pad 110 even if it contacts the chip pad 100 . In some embodiments, the compound produced has a neutral charge and a higher molecular weight, and thus less tendency to migrate. The reactive substance 2100 is adsorbed and attached to the ion trapping particles of each inorganic filler (312, 342, 372) to substantially prevent/reduce migration of the reactive substance 2100. FIG. Filler particles are reactive substances 2100 (e.g. Cl<sup>-</sup>, K<sup>+</sup>, Na<sup>+</sup>, OH<sup>-</sup>, and H<sup>+</sup>). At this time, the chemical reaction results in by-products that are separated from the binding filler particles. The following chemical reactions occur to form one or more byproducts within the semiconductor package.
<img file="JP7204371B2_D0001.tif" />
Even if the reactive material 2100 flows into each lower insulating layer (320, 350, 380), it has difficulty passing through each upper insulating layer (310, 340, 370). Therefore, damage to the chip pad 110 by the reactive material 2100 is prevented/reduced.
According to this embodiment, the thickness T1 of the first upper insulating layer 310 is equal to or greater than 10% of the thickness T2 of the first lower insulating layer 320. FIG. The reliability and durability of the semiconductor module 10 are improved. The thickness of second upper insulating layer 340 is 10% or more of the thickness of second lower insulating layer 350 . The thickness of third upper insulating layer 370 is 10% or more of the thickness of third lower insulating layer 380 . Therefore, the reliability and durability of the semiconductor module 10 are further improved.
The above detailed description of the present invention is not intended to limit the present invention to the disclosed implementation state, and various modifications can be made without departing from the technical scope of the present invention.
1, 2, 3, 4, 6, 7, 8 Semiconductor packages
4' 1st semiconductor package
Five Second semiconductor package
Ten semiconductor module
100 semiconductor chip
100a, 200a top
100b, 200b Bottom
110 chip pad
120 protective layer
150 connecting part
160, 161 conductive pads
170, 2000 Underfill film
200, 730 mold film
250 hole
300 rewiring layer
310 First upper insulating layer
311 1st polymer film
312 First inorganic filler
320 First lower insulating layer
325 remnants
330 First rewiring pattern
330A Via part
330B Wiring part
331 seed pattern
333 conductive pattern
335 1st opening
339 mask pattern
340 Second upper insulating layer
341 Second polymer film
342 Second inorganic filler
350 Second lower insulating layer
360 Second rewiring pattern
365 2nd opening
370 Third upper insulating layer
371 Third polymer film
372 Third inorganic filler
380 Third lower insulating layer
390 Third rewiring pattern
395 3rd opening
400 connecting terminal
410 connecting pad
500 wiring board
510 base layer
520 conductive structure
521 bottom metal pattern
522 intermediate metal pattern
523 Via
524 top metal pattern
590 cavity
600 solder pattern
710 package substrate
711 metal pad
720 semiconductor element
910 carrier substrate
910' 1st carrier substrate
920 Second carrier substrate
1000 module board
1100 module pad
2100 reactive substance
35 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35
Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| JP2016213466A | Cites | Japan |
| WO2017131037A1 | Cites | World Intellectual Property Organization (WIPO) |
| JP2012049279A | Cites | Japan |
| US20060079025A1 | Cites | United States of America |
| JP2001144123A | Cites | Japan |
| JP2002110855A | Cites | Japan |
| JP2005036126A | Cites | Japan |
| JP2017228755A | Cites | Japan |
| KR20060053168A | Cites | Republic of Korea |
11 members in 5 offices
Priority claims4
| Document | Office | Kind | Date |
|---|---|---|---|
| 1020170101832 | Republic of Korea | – | |
| 20170101832 | Republic of Korea | A | |
| 16010872 | United States of America | – | |
| 201816010872 | United States of America | A |
Members11
| Document | Office | Kind | |
|---|---|---|---|
| US2019051607A1 | United States of America | A1 | |
| KR20190017266A | Republic of Korea | A | |
| CN109390296A | China | A | |
| JP2019036723A | Japan | A | |
| SG10201806580YA | Singapore | A | |
| US10522471B2 | United States of America | B2 | |
| US2020098694A1 | United States of America | A1 | |
| US10964643B2 | United States of America | B2 | |
| KR102440119B1 | Republic of Korea | B1 | |
| JP7204371B2This record | Japan | B2 | |
| CN109390296B | China | B |
9 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
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|---|---|---|
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| First payment of annual fees (during grant procedure)JAPANESE INTERMEDIATE CODE: A61A61 | A61 | |
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Numbers
- Publication
- 7204371
- Application
- 149127
Titles2
- Japanese
- 半導体パッケージ及びその製造方法
- English
- Semiconductor package and its manufacturing method
Classification
- CPC, 36
- H10W20/40
- H10W70/614
- H10W74/129
- H10P72/74
- H10P72/743
- H10P72/7434
- H10W70/05
- H10W74/117
- H10W70/69
- H10W90/701
- H10W70/685
- H10W70/611
- H10W72/242
- H10W72/241
- H10W72/252
- H10W90/724
- H10W72/07207
- H10W70/60
- H10W70/09
- H10W72/0198
- H10W90/00
- H10W72/9413
- H10W72/9415
- H10W72/29
- H10W74/15
- H10W90/722
- G03F7/20
- H10W74/10
- H10W72/013
- H10W72/30
- H10W70/093
- H10W70/65
- H10W70/695
- H10W74/014
- H10W74/016
- H10W70/6528
- IPC, 5
- H01L23 12
- H01L25 07
- H01L25 065
- H01L25 18
- H10W74 01
