Method for forming metal oxide film

One aspect of the present invention relates to, for example, a semiconductor device, a display device, a light emitting device, a method for driving the same, or a method for manufacturing the same. In particular, one aspect of the present invention relates to a metal oxide film and a method for forming a metal oxide film. The present invention also relates to a semiconductor device using the metal oxide film.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

Attention is being paid to a technique for constructing a transistor using a semiconductor film formed on a substrate having an insulating surface. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also referred to simply as display devices). Silicon-based semiconductor materials are widely known as semiconductor films applicable to transistors, but metal oxides (oxide semiconductors) exhibiting semiconductor characteristics are attracting attention as other materials.

For example, Patent Document 1 discloses a technique for producing a transistor using an amorphous oxide containing In, Zn, Ga, Sn, etc. as an oxide semiconductor.

<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2006-165529</text></patcit></p>

<p>One aspect of the present invention is to provide a metal oxide film containing a crystal portion.</p><p>Alternatively, one aspect of the present invention is to provide a metal oxide film having high physical stability.</p><p>Another object of the present invention is to provide a highly reliable semiconductor device to which the above-mentioned metal oxide film or the like is applied.</p><p>Alternatively, one aspect of the present invention makes it an object to provide a novel semiconductor device. The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. It should be noted that the problems other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the problems other than these from the description of the description, drawings, claims, etc. Is.</p>

<p>One aspect of the disclosed invention is a metal oxide film containing ultrafine crystal portions to the extent that no periodicity is observed in the atomic arrangement macroscopically or long-range order is not observed macroscopically. .. In the metal oxide film of one aspect of the present invention, a halo pattern showing an amorphous state is observed in the selected area electron diffraction pattern on the membrane plane, and no halo pattern is observed in the nanobeam electron diffraction pattern of the cross section. Includes regions where non-directional spots are observed, which are different from regular spots showing crystals oriented to a particular plane. More specifically, for example, it is a metal oxide film having the following constitution.</p><p>One aspect of the present invention is a metal oxide film characterized by including a region in which a plurality of spots distributed in a circumferential shape are observed in a nanobeam electron diffraction pattern of a cross section.</p><p>Further, one aspect of the present invention is a region in which a plurality of spots distributed in a circumferential shape are observed in the nanobeam electron diffraction pattern of the cross section, and a halo pattern is observed in the selected area diffraction pattern of the plane. It is a metal oxide film characterized by containing.</p><p>In the above, it is preferable that the measurement range in the selected area electron diffraction pattern is 300 nmφ or more.</p><p>Further, in the above, it is preferable that the measurement range of nanobeam electron diffraction is 5 nmφ or more and 10 nmφ or less. By irradiating an electron beam having a beam diameter converged to 1 nmφ, a nanobeam electron diffraction pattern having a measurement range of 5 nmφ or more and 10 nmφ or less can be obtained.</p><p>Further, the nanobeam electron diffraction pattern described above is preferably a nanobeam electron diffraction pattern of a cross section of a sample sliced to a thickness of 50 nm or less, which is larger than 10 nm.</p><p>Further, in the above, the metal oxide film preferably contains a crystal portion, and the size of the crystal portion is preferably 10 nm or less. Alternatively, it is preferably 1 nm or more and 10 nm or less.</p><p>Further, one aspect of the present invention is a metal oxide film including a crystal portion, and the crystal portion has a metal oxide film larger than 10 nm and 50 nm or less in nanobeam electron diffraction with a measurement range of 5 nmφ or more and 10 nmφ or less. In the diffraction pattern of the cross section sliced to the thickness of, multiple spots distributed in a circumferential shape are observed, and in the diffraction pattern of the cross section in which the metal oxide film is sliced to a thickness of 10 nm or less, a specific surface is observed. It is a metal oxide film characterized by including a region where regular spots showing oriented crystals are observed.</p><p>Further, in any one of the above metal oxide films, the metal oxide film is preferably composed of at least indium, gallium or zinc.</p><p>Further, in another aspect of the present invention, by performing a sputtering method using an oxide target at room temperature and in an atmosphere containing oxygen, the nanobeam electron diffraction pattern in the cross-sectional direction is distributed in a circumferential shape. This is a method for forming a metal oxide film, which comprises forming a metal oxide film containing a region in which a plurality of spots are observed.</p><p>Further, in the above-mentioned method for forming a metal oxide film, it is preferable to form a film in an atmosphere in which the partial pressure of oxygen is 33% or more.</p>

<p>According to one aspect of the present invention, a metal oxide film containing a crystal portion can be provided.</p><p>Moreover, according to one aspect of the present invention, it is possible to provide a metal oxide film having high physical stability. Further, by applying the metal oxide film to a semiconductor device, a highly reliable semiconductor device can be provided.</p>

<figref num="1">Cross-sectional TEM image and nanobeam electron diffraction pattern of the metal oxide film according to one aspect of the present invention.</figref><figref num="2">A planar TEM image of a metal oxide film according to an aspect of the present invention and a selected area electron diffraction pattern.</figref><figref num="3">Conceptual diagram of electron diffraction intensity distribution.</figref><figref num="4">Nanobeam electron diffraction pattern of a quartz glass substrate.</figref><figref num="5">Cross-sectional TEM image of the metal oxide film of one aspect of the present invention.</figref><figref num="6">X-ray diffraction analysis result of the metal oxide film of one aspect of the present invention.</figref><figref num="7">The nanobeam electron diffraction pattern of the metal oxide film of one aspect of the present invention.</figref><figref num="8">The nanobeam electron diffraction pattern of the metal oxide film of one aspect of the present invention.</figref><figref num="9">The figure explaining the structural example of the transistor which concerns on embodiment.</figref><figref num="10">The figure explaining the example of the manufacturing method of the transistor which concerns on embodiment.</figref><figref num="11">The figure explaining the structural example of the transistor which concerns on embodiment.</figref><figref num="12">The figure explaining the structure of the display panel which concerns on embodiment.</figref><figref num="13">The figure explaining the block diagram of the electronic device which concerns on embodiment.</figref><figref num="14">The figure explaining the external view of the electronic device which concerns on embodiment.</figref><figref num="15">Cross-sectional TEM image and nanobeam electron diffraction pattern of the metal oxide film according to one aspect of the present invention.</figref><figref num="16">The conceptual diagram which shows the flaking method of a sample by an ion milling method.</figref><figref num="17">The nanobeam electron diffraction pattern of the metal oxide film of one aspect of the present invention.</figref><figref num="18">SIMS analysis results of the metal oxide film according to the comparative example and the embodiment.</figref><figref num="19">X-ray diffraction analysis results of samples prepared by the liquid phase method.</figref><figref num="20">Cross-sectional TEM image of the sample of the comparative example.</figref><figref num="21">A nanobeam electron diffraction pattern of a metal oxide film of one aspect of the present invention and a sample of a comparative example.</figref><figref num="22">The figure which shows the crystal structure of the oxide semiconductor layer used for calculation.</figref><figref num="23">Calculation results showing the effect of hydrogenation on the crystalline state.</figref><figref num="24">The binding energy measurement result by XPS of the metal oxide film of one aspect of the present invention and the sample of the comparative example.</figref>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and mode thereof can be changed in various ways. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

(Embodiment 1) In the present embodiment, the metal oxide film of one aspect of the present invention will be described with reference to FIGS. 1 to 7 and 15 to 21.

&lt;Crystal part of metal oxide film&gt; The metal oxide film of the present embodiment is extremely macroscopically to the extent that no periodicity is observed in the atomic arrangement, or macroscopically to the extent that long-range order is not observed. It is a metal oxide film containing fine crystal parts. Therefore, a spot having regularity indicating a crystal state may not be obtained by electron diffraction in a measurement range larger (wider) than the crystal portion contained in the metal oxide film of the present embodiment.

&lt;&lt; Cross-sectional TEM image and microelectron beam diffraction pattern &gt;&gt; Fig. 1 (A) shows a cross-sectional TEM (Transmission Electron Microscopy) image of the metal oxide film of the present embodiment. Further, the electron diffraction pattern measured by using nanobeam electron diffraction at point 1 in FIG. 1 (A) is shown in FIG. 1 (B), and the nanobeam electron diffraction pattern is shown in FIG. 1 (C) at point 2 in FIG. 1 (A). The electron diffraction pattern measured by using diffraction is shown in FIG. 1 (D), and the electron diffraction pattern measured by nanobeam electron diffraction at point 3 in FIG. 1 (A) is shown in FIG. 1 (D).

As an example of the metal oxide film, a sample in which an In-Ga-Zn-based oxide film was formed on a quartz glass substrate with a film thickness of 50 nm was used. The conditions for forming the metal oxide film are: In: Ga: Zn = 1: 1: 1 (atomic number ratio), using an oxide target, under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, DC (DC). ) The power supply was 0.5 kW and the substrate temperature was room temperature. Then, the formed metal oxide film was sliced to a thickness of about 50 nm (for example, 40 nm ± 10 nm) to obtain a cross-sectional TEM image and a nanobeam electron diffraction pattern.

The cross-sectional observation of the metal oxide film was carried out using a transmission electron microscope (H-9000NAR manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 300 kV and a magnification of 2 million times. Nanobeam electron diffraction was performed using a transmission electron microscope (HF-2000 manufactured by Hitachi High-Technologies Corporation) with an acceleration voltage of 200 kV and a beam diameter of about 1 nmφ. The measurement range of nanobeam electron diffraction is 5 nmφ or more and 10 nmφ or less.

As shown in FIG. 1 (B), in the metal oxide film of the present embodiment, a plurality of spots (bright spots) arranged in a circumferential shape are observed in the nanobeam electron diffraction pattern. In other words, in the metal oxide film of the present embodiment, a plurality of spots distributed in a circumferential shape are observed. Alternatively, it can be said that a plurality of spots distributed in a circumferential shape form a plurality of concentric circles.

Further, in FIG. 1 (D) near the interface with the quartz glass substrate and in FIG. 1 (C) at the center of the metal oxide film in the film thickness direction, the metal oxide film was distributed in a circumferential shape as in FIG. 1 (B). Multiple spots are observed. In FIG. 1 (C), the radius of the first circumference (distance from the main spot) ranged from 3.88 / nm to 4.93 / nm. When converted to surface spacing, it is 0.203 nm to 0.257 nm.

In the nanobeam electron diffraction pattern of FIG. 1, a plurality of spots are observed, unlike the halo pattern showing an amorphous state. Therefore, it is confirmed that the metal oxide film of the present embodiment has a crystal portion. However, in the nanobeam electron diffraction pattern of FIG. 1, spots having no directionality are observed instead of spots having regularity showing crystals oriented to a specific plane. Therefore, the metal oxide of the present embodiment is observed. It is presumed that the film is a film in which a plurality of crystal portions having irregular plane orientations and different sizes are mixed.

Further, FIG. 5 shows a partially enlarged view of the cross-sectional TEM image shown in FIG. 1 (A). FIG. 5 (A) is a cross-sectional TEM image of the vicinity of point 1 (the surface of the metal oxide film) in FIG. 1 (A) observed at a magnification of 8 million times. Further, FIG. 5 (B) is a cross-sectional TEM image of the vicinity of point 2 (the central portion of the metal oxide film in the film thickness direction) of FIG. 1 (A) observed at a magnification of 8 million times.

Further, the crystal structure of the metal oxide film of the present embodiment cannot be clearly confirmed from the cross-sectional TEM image shown in FIG.

&lt;&lt; Plane TEM image and selected area electron diffraction pattern &gt;&gt; Next, FIG. 2 (A) shows a plane TEM image of the metal oxide film of the present embodiment. Further, FIG. 2 (B) shows an electron diffraction pattern in which the region surrounded by a circle in FIG. 2 (A) is measured by selected area electron diffraction.

As an example of the metal oxide film, a sample in which an In-Ga-Zn-based oxide film was formed on a quartz glass substrate with a film thickness of 30 nm was used. The conditions for forming the metal oxide film are: In: Ga: Zn = 1: 1: 1 (atomic number ratio), using an oxide target, under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, DC (DC). ) The power supply was 0.5 kW and the substrate temperature was room temperature. Then, the formed sample was sliced so as to leave a metal oxide film, and a planar TEM image and a selected area electron diffraction pattern were obtained.

The image in Fig. 2 was obtained with an acceleration voltage of 300 kV using a transmission electron microscope ("H-9000NAR" manufactured by Hitachi High-Technologies Corporation). FIG. 2 (A) was obtained by observing the metal oxide film in a plane at a magnification of 500,000 times. Further, FIG. 2 (B) is a result of measurement of the inside of the circle shown in FIG. 2 (A) by selected area electron diffraction. The pattern shown in FIG. 2 (B) was obtained by performing electron diffraction with the restricted visual field region set to 300 nmφ. Considering the spread of the electron beam (about several nm), the measurement range is 300 nmφ or more.

As shown in FIG. 2 (B), in the metal oxide film of the present embodiment, in the electron diffraction pattern using the selected area electron diffraction having a wider measurement range than the micro electron diffraction, the micro electron diffraction is performed. The observed multiple spots are not seen, and the halo pattern is observed. Therefore, the metal oxide film of the present embodiment has a degree in which no periodicity is observed in the atomic arrangement macroscopically (for example, when the measurement range is 300 nmφ or more), or a long-range order macroscopically. It can be said that it is a metal oxide film containing ultrafine crystal parts to the extent that it cannot be seen.

&lt;&lt; Conceptual diagram of electron diffraction intensity distribution &gt;&gt; Fig. 3 conceptually shows the distribution of diffraction intensity in the electron diffraction patterns of FIGS. 1 and 2. FIG. 3 (A) is a conceptual diagram of the distribution of diffraction intensity in the microelectron beam diffraction pattern shown in FIGS. 1 (B) to 1 (D). Further, FIG. 3 (B) is a conceptual diagram of the distribution of the diffraction intensity in the selected area electron diffraction pattern shown in FIG. 2 (B). In addition, FIG. 3C is a conceptual diagram of the distribution of diffraction intensity in an electron beam diffraction pattern having an ideal polycrystalline structure.

In FIG. 3, the vertical axis represents the electron diffraction intensity (arbitrary unit), and the horizontal axis represents the distance from the main spot.

In the ideal polycrystalline structure shown in FIG. 3 (C), a peak is observed at a specific distance from the main spot according to the interplanar spacing (d value) of the planes on which the crystal portions are oriented. In this case, in the electron diffraction pattern, a ring having a small line width is clearly observed at a specific distance from the main spot.

On the other hand, as shown in FIG. 1, the circumferential region formed by the plurality of spots observed in the nanobeam electron diffraction pattern of the metal oxide film of the present embodiment has a relatively large width. Therefore, as shown in FIG. 3 (A), the electron diffraction intensity shows a discrete intensity distribution having a plurality of peaks (peak bands) distributed in a band shape. Further, in the nanobeam electron diffraction pattern, since a small number of spots are present between the concentric regions, as shown in FIG. 3 (A), there is a diffraction peak between the two peak bands. I understand.

On the other hand, as shown in FIG. 3B, the electron diffraction intensity distribution in the selected area electron diffraction pattern of the metal oxide film of the present embodiment shows a continuous intensity distribution. Since FIG. 3 (B) can be approximated to the result of observing the electron diffraction intensity distribution shown in FIG. 3 (A) over a wide range, the peak bands shown in FIG. 3 (A) are integrated and the continuous intensity distribution is obtained. Can be considered to have been obtained.

As shown in FIGS. 3 (A) to 3 (C), the metal oxide film of the present embodiment is a film in which a plurality of crystal portions having irregular plane orientations and different sizes are mixed. Moreover, it is suggested that the crystal portion is extremely fine so that no spot is observed in the selected area electron diffraction pattern.

The metal oxide film in which a plurality of spots are observed as shown in FIG. 1 in the nanobeam electron diffraction pattern is sliced to a thickness of about 50 nm. Moreover, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, it is presumed that the size of the crystal portion contained in the metal oxide film of the present embodiment is at least 50 nm or less, for example, 10 nm or less, or 5 nm or less.

&lt;&lt; Nanobeam electron diffraction pattern of ultrathinned sample &gt;&gt; When the size of the crystal part contained in the metal oxide film of the present embodiment is 10 nm or less, or 5 nm or less, the thickness of the metal oxide film is about 50 nm. Since the measurement range in the depth direction of the sliced sample is larger than the size of the crystal portion, a plurality of crystal portions may be included in the measurement range. Therefore, the metal oxide film was sliced to a thickness of 10 nm or less, and its cross section was observed by nanobeam electron diffraction.

The method for preparing the sample is shown below. An In-Ga-Zn-based oxide film was formed on a quartz glass substrate with a film thickness of 50 nm. The film formation conditions are In: Ga: Zn = 1: 1: 1 (atomic number ratio), using an oxide target, under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, direct current (DC) power supply 0.5 kW. , The substrate temperature was set to room temperature. Then, after forming the metal oxide film, the first heat treatment at 450 ° C for 1 hour in a nitrogen atmosphere and the second heat treatment at 450 ° C in a nitrogen and oxygen atmosphere for 1 hour. Was done.

The metal oxide film after the second heat treatment was sliced by an ion milling method using Ar ions. First, a quartz glass substrate on which a metal oxide film was formed was bonded to a dummy substrate to reinforce the flaking, and then flaked to a thickness of about 50 μm by cutting and polishing. After that, as shown in FIG. 16, the quartz glass substrate 200 and the dummy substrate 202 provided with the metal oxide film 204 are irradiated with argon ions from a low angle (about 3 °) to perform ion milling. A sliced region 210a to a thickness of about 50 nm (40 nm ± 10 nm) and a sliced region 210b to a thickness of 10 nm or less, for example, 5 to 10 nm were formed, and their cross sections were observed.

FIG. 15 (A) shows a cross-sectional TEM image of the sample sliced to a thickness of about 50 nm corresponding to the region 210a. Further, the cross section shown in FIG. 15 (A) and the electron diffraction pattern measured by nanobeam electron diffraction are shown in FIGS. 15 (B) to 15 (E). FIG. 15B shows an electron diffraction pattern using an electron beam whose beam diameter is converged to 1 nmφ. FIG. 15C shows an electron diffraction pattern using an electron beam whose beam diameter is converged to 10 nmφ. FIG. 15 (D) is an electron diffraction pattern using an electron beam whose beam diameter is converged to 20 nmφ. FIG. 15 (E) is an electron diffraction pattern using an electron beam whose beam diameter is converged to 30 nmφ.

From FIG. 15 (B), a plurality of spots (bright spots) distributed in a circumferential shape are also observed in the metal oxide film after the heat treatment, as in FIG. 1. Further, from FIGS. 15 (C) to 15 (E), it is confirmed that when the beam diameter of the electron beam is increased to widen the measurement range, the plurality of spots gradually become broad.

Further, in FIGS. 17 (A) to 17 (D), an electron beam having a beam diameter converged to 1 nmφ was used at any four points of the sample sliced to a thickness of 10 nm or less corresponding to the region 210b. The measured nanobeam electron diffraction pattern is shown.

In FIGS. 17 (A) and 17 (B), regular spots showing crystals oriented to a specific plane are observed. From this, it can be seen that the metal oxide film according to the present embodiment certainly has a crystal portion. On the other hand, in FIGS. 17 (C) and 17 (D), a plurality of spots (bright spots) distributed in a circumferential shape are observed.

As described above, the size of the crystal portion contained in the metal oxide film of the present embodiment is at least 50 nm or less, and is extremely fine, for example, 10 nm or less or 5 nm or less. Therefore, for example, when the sample is sliced to a thickness of 10 nm or less and the electron beam is converged to 1 nmφ to reduce the measurement range to, for example, a region smaller than the size of one crystal portion, depending on the region to be measured. , Spots with regularity showing crystals oriented to a specific plane can be observed. Further, when a plurality of crystal portions are included in the measurement region, the electron beam transmitted through the crystal portions may irradiate another crystal portion existing in the depth direction. In this case, it can be considered that a plurality of nanobeam electron diffraction patterns are observed.

&lt;&lt; Ultra-fine electron diffraction pattern of quartz substrate &gt;&gt; Fig. 4 shows the nanobeam electron diffraction pattern of a quartz glass substrate. The measurement conditions were the same as those of the metal oxide film shown in FIG.

From FIG. 4, in the quartz glass substrate having an amorphous structure, a halo pattern in which the brightness continuously changes from the main spot without being diffracted by a specific spot is observed. As described above, in the film having an amorphous structure, even if electron diffraction is performed in a very minute region, the film is arranged in a circumferential shape as observed in the metal oxide film of the present embodiment. Multiple spots are not observed. Therefore, it is confirmed that the plurality of spots arranged in a circumferential shape observed in FIGS. 1 (B) to 1 (D) are peculiar to the metal oxide film of the present embodiment.

&lt;&lt; Electron diffraction pattern after continuous irradiation of ultrafine electron beam &gt;&gt; In Fig. 8, the measurement was performed after irradiating point 2 shown in Fig. 1 (A) with an electron beam whose beam diameter converged to about 1 nmφ for 1 minute. The electron diffraction pattern is shown.

Similar to the electron diffraction pattern shown in FIG. 1 (C), the electron diffraction pattern shown in FIG. 8 observes a plurality of spots distributed in a circumferential shape, and no particular difference is confirmed in the measurement results of the two. .. This means that the crystal portion confirmed in FIG. 1 (C) has existed since the formation of the metal oxide film of the present embodiment, and the focused electron beam was irradiated. It means that the crystal part is not formed by.

&lt;&lt; Analysis by X-ray diffraction &gt;&gt; The sample in which the metal oxide film of the present embodiment was formed on the quartz glass substrate used in FIGS. 1 and 2 was subjected to X-ray diffraction (XRD: X-Ray Diffraction). And analyzed. Figure 6 shows the results of measuring the XRD spectrum using the out-of-plane method.

In FIG. 6, the vertical axis is the X-ray diffraction intensity (arbitrary unit), and the horizontal axis is the diffraction angle 2θ (deg.). The XRD spectrum was measured using an X-ray diffractometer D-8 ADVANCE manufactured by Bruker AXS.

As shown in FIG. 6, a peak due to quartz is observed in the vicinity of 2θ = 20 to 23 °, but a peak due to the crystal part contained in the metal oxide film cannot be confirmed.

The results of FIG. 6 also suggest that the crystal portion contained in the metal oxide film of the present embodiment is an ultrafine crystal portion.

As shown above, the metal oxide film of the present embodiment can be presumed to be a film formed by agglomeration of crystal portions having irregular plane orientations.

Further, it is presumed that the size of the crystal portion contained in the metal oxide film of the present embodiment is, for example, 10 nm or less, or 5 nm or less. The metal oxide film of the present embodiment is, for example, a metal oxide film containing a crystal portion (nanocrystal (nc)) of 1 nm or more and 10 nm or less.

&lt;Method of forming a metal oxide film&gt; The method of forming a metal oxide film of the present embodiment will be described below. As described above, the metal oxide film of the present embodiment is formed by a sputtering method at room temperature and in an atmosphere containing oxygen. By setting the film forming atmosphere to an atmosphere containing oxygen, oxygen deficiency in the metal oxide film can be reduced, and a film containing a crystal portion can be obtained.

&lt;&lt; Reduction of Oxygen Deficiency &gt;&gt; In the metal oxide film of the present embodiment, by reducing the oxygen deficiency, it is possible to obtain a film having stable physical properties. In particular, when a semiconductor device is manufactured by applying an oxide semiconductor film as the metal oxide film of the present embodiment, oxygen deficiency in the oxide semiconductor film becomes a carrier generation factor, and as a result, the electrical characteristics of the semiconductor device. It becomes a factor that fluctuates. Therefore, by manufacturing a semiconductor device using an oxide semiconductor film having reduced oxygen deficiency, it is possible to obtain a highly reliable semiconductor device.

The metal oxide film of the present embodiment is preferable because oxygen deficiency can be further reduced by increasing the oxygen partial pressure in the film forming atmosphere. For example, it is preferable that the oxygen partial pressure in the film forming atmosphere is 33% or more.

FIG. 7 shows the nanobeam electron diffraction pattern of the metal oxide film of the present embodiment in which a film was formed at an oxygen partial pressure of 33%. In the metal oxide film of the present embodiment shown in FIG. 7, the film formation atmosphere is a mixed atmosphere of argon and oxygen (Ar: O).₂It was prepared under the same conditions as the metal oxide film shown in Fig. 1 except that = 30 sccm: 15 sccm). Further, the nanobeam electron diffraction measurement was performed in the same manner as the measurement described in FIGS. 1 (B) to 1 (D).

From FIG. 7, even in the metal oxide film of the present embodiment in which the oxygen partial pressure is 33%, a plurality of spots arranged in a circumferential shape are observed in the nanobeam electron diffraction pattern, and the crystal portion is included. It is confirmed that the metal oxide film is formed.

&lt;&lt; Film formation by sputtering method &gt;&gt; The oxide target that can be used for film formation of the metal oxide film of the present embodiment is not limited to In-Ga-Zn-based oxides, for example, In-M-Zn. System oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf) can be applied.

Further, it is preferable to form a metal oxide film containing a crystal portion, which is the metal oxide film of the present embodiment, by using a sputtering target containing a polycrystalline oxide having a plurality of crystal grains. When the sputtering target has a plurality of crystal grains and there is an interface in which the bond between the plurality of crystal grains is weak and easy to open, the crystal grains are opened by colliding the ions with the sputtering target. , Plate-shaped sputtering particles may be obtained. This is because the obtained flat-plate-shaped sputtering particles may be deposited on the substrate to form a metal oxide film containing nanocrystals. However, it should be added that the film formation mechanism of the metal oxide film according to the present embodiment described above is merely a consideration.

The metal oxide film of the present embodiment shown above is a film in which a plurality of crystal portions having irregular plane orientations and different sizes are mixed, and the crystal portions are selected area electron diffraction patterns. It is suggested that the spots are extremely fine to the extent that no spots are observed.

Further, the metal oxide film of the present embodiment has a region containing a crystal portion and has stable physical properties. Therefore, by applying the metal oxide film of the present embodiment to a semiconductor device, it is possible to provide a highly reliable semiconductor device.

(Comparative Example) In this comparative example, the crystallinity of the metal oxide film produced by the liquid phase method will be described with reference to the drawings.

The method of forming the metal oxide film formed in this comparative example is shown below.

First, In₂O₃(5wt%), Ga₂O₃(3wt%), ZnO (5wt%) and a coating agent were mixed so as to have In: Ga: Zn = 1: 1: 1 and applied onto a glass substrate by spin coating. The spin coating conditions were gradually changed from 900 rpm to 2000 rpm using a spinner.

After coating, the first heat treatment was performed at 150 ° C. for 2 minutes in an air atmosphere using a hot plate.

Then, a second heat treatment was performed at 450 ° C. for 1 hour in an atmospheric atmosphere. The metal oxide film (liquid phase film formation) of this comparative example after the second heat treatment and the metal oxide film of the present embodiment prepared under the same conditions as the metal oxide film shown in FIG. 7 (liquid phase film formation). For each of the sputtering method film formation), the bonding state was evaluated using X-ray Photoelectron Spectroscopy (XPS). Figure 24 shows the evaluation results.

In the XPS analysis, PHI's Quantera SXM was used as the measuring device. In FIG. 24, for each metal oxide film, In 3d (5/2) orbital (see FIG. 24 (A)), Ga 3d orbital (see FIG. 24 (B)), Zn 3p orbital (see FIG. 24 (A)). (C)) and the spectrum of the region corresponding to the 1s orbital of O (see FIG. 24 (D)) are shown. The solid line in FIG. 24 is the evaluation result of the In-Ga-Zn oxide film formed by the liquid phase method according to this comparative example, and the broken line in FIG. 24 is formed by the sputtering method (sputtering) according to the present embodiment. This is the evaluation result of the In-Ga-Zn oxide film of the film.

From FIGS. 24 (A) to 24 (D), although a slight shift is observed in the binding energy, the metal oxide film formed by the liquid phase method shown in this comparative example and the sputtering method according to the present embodiment are used. A substantially similar spectral shape was obtained for the formed metal oxide film. Therefore, it was identified that the metal oxide film produced by using the liquid phase method shown in this comparative example is certainly an In-Ga-Zn oxide film.

Then, the prepared sample of this comparative example was analyzed by XRD. Figure 19 shows the results of analysis using the out-of-plane method.

For XRD analysis, an In-Ga-Zn oxide film was subjected to a second heat treatment at 350 ° C, 450 ° C, or 550 ° C for 1 hour after the first heat treatment in an atmospheric atmosphere. A sample was used.

In FIG. 19, the vertical axis is the X-ray diffraction intensity (arbitrary unit), and the horizontal axis is the diffraction angle 2θ (deg.). For the XRD measurement, an X-ray diffractometer D-8 ADVANCE manufactured by Bruker AXS was used.

FIG. 19 (A) shows the measurement results of the sample prepared by the liquid phase method in this comparative example. The XRD pattern of the first non-heat-treated sample is the pattern shown as as-depo. In addition, in FIGS. 19 (B), (C), and (D), a film was formed by the liquid phase method, and then heat-treated at 350 ° C, 450 ° C, or 550 ° C for 1 hour in an air atmosphere. The measurement result of the indium oxide film, the gallium oxide film, or the zinc oxide film obtained by the above is shown.

From FIG. 19, in the XRD pattern of the indium oxide film after heat treatment, In₂O₃A peak consistent with the crystal peak of was confirmed. In addition, in the XRD pattern of the zinc oxide film after heat treatment, a peak consistent with the ZnO crystal peak was confirmed. On the other hand, in the sample of this comparative example, unlike the indium oxide film and the zinc oxide film, no crystallinity peak was confirmed in the sample after the heat treatment under any temperature condition.

In addition, the film density of the sample subjected to the second heat treatment at 450 ° C. for 1 hour in the atmospheric atmosphere was measured by the X-ray reflectivity measurement method (XRR: X-Ray Reflection).

In XRR measurement, X-rays are incident on the measurement sample, the critical angle of the incident X-rays, changes in amplitude waveform, etc. are measured, and theoretical analysis is performed using the measured critical angle, amplitude waveform, etc. This is a measurement method for measuring the density of the formed thin film.

The measured film densities are shown in Table 1.

<tables num="1"><img file="JP6905042B2_D0001.tif" /></tables>

From Table 1, it was confirmed that the film obtained by the liquid phase method had a very low density as compared with the theoretical value calculated from the single crystal structure. However, it should be added that it is difficult to measure the film density with high accuracy because the film formed by the liquid phase method has a large roughness.

Next, the concentration of impurities contained in the metal oxide film of the comparative example and the metal oxide film of the present embodiment was measured by SIMS (Secondary Ion Mass Spectrometry) analysis.

FIG. 18 (A) shows hydrogen (hydrogen in the metal oxide film of the comparative example and the metal oxide film of the present embodiment).¹H) Shows the concentration profile. Further, in FIG. 18B, the carbon of the metal oxide film of the comparative example and the metal oxide film of the present embodiment (¹²C) Show the concentration profile. In FIG. 18, the horizontal axis represents the depth (nm) and the vertical axis represents the concentration of hydrogen or carbon (atoms / cm).³).

As the metal oxide film of the comparative example in FIG. 18, a sample prepared by the liquid phase method was applied in the same manner as described above. However, before spin coating, filtration was performed with a membrane filter (0.2 μm). The condition of the second heat treatment was 450 ° C, 500 ° C or 550 ° C for 1 hour in an atmospheric atmosphere. Other conditions were the same as those for the metal oxide film in the liquid phase method described above. The metal oxide film of the present embodiment was produced by a sputtering method under the same conditions as the metal oxide film shown in FIG.

From FIGS. 18 (A) and 18 (B), it was confirmed from the metal oxide film of the comparative example that a larger amount of hydrogen and carbon were uniformly present in the film than the metal oxide film of the present embodiment. rice field.

Since the carbon concentration of the metal oxide film of the present embodiment shown in FIG. 18 (B) gradually decreases from the surface to the inside of the film, the carbon contained in the metal oxide film of the present embodiment is the surface. It is suggested that the aspect derived from pollution is strong.

On the other hand, in the metal oxide film of the comparative example, hydrogen is 1 × 10 under any condition.²²(atoms / cm³) Above, carbon is 4 × 10²¹(atoms / cm³) It can be seen that the values as high as above are uniformly present in the film. It is presumed that the carbon contained in the metal oxide film of the comparative example is derived from the organic acid salt which is the raw material of the spin coating material.

Next, FIG. 20 shows a cross-sectional TEM image of the sample of this comparative example that was subjected to the second heat treatment at 450 ° C. for 1 hour in the atmospheric atmosphere. The cross-section was observed with a transmission electron microscope ("H-9000NAR" manufactured by Hitachi High-Technologies Corporation) with an acceleration voltage of 300 kV. FIG. 20 (A) is a cross-sectional observation image at a magnification of 500,000 times, FIG. 20 (B) is a cross-sectional observation image at a magnification of 2 million times, and FIG. 20 (C) is a cross-sectional observation image at a magnification of 8 million times. ..

From FIGS. 20 (A) and 20 (B), it is observed that the sample prepared by the liquid phase method in this comparative example occupies most of the amorphous region. In addition, it can be seen that there are shades (high and low brightness) due to the difference in film density.

Further, it can be said that the region a in FIG. 20C has a high brightness of the cross-sectional TEM image and a low film density. It can be said that the region b in FIG. 20 (C) is a region in which the brightness of the cross-sectional TEM image is low and the film density is high.

The regions a and b in FIG. 20 (C) were observed using nanobeam electron diffraction. FIGS. 21 (A) to 21 (C) show nanobeam electron diffraction patterns.

Electron diffraction was performed using a transmission electron microscope (HF-2000 manufactured by Hitachi High-Technologies Corporation) with an acceleration voltage of 200 kV and a beam diameter of about 1 nmφ. FIG. 21 (A) is a nanobeam electron diffraction pattern of region a in FIG. 20 (C), and FIGS. 21 (B) and 21 (C) are both nanobeam electron beams in region b of FIG. 20 (C). It is a diffraction pattern, and is the observation result of two different places (denoted as b1 and b2).

Further, FIG. 21 (D) is a nanobeam electron diffraction pattern of the metal oxide film according to one aspect of the present invention, which is an electron diffraction pattern produced and observed under the same conditions as shown in FIG. be.

From FIG. 21, in the metal oxide film produced by the liquid phase method in this comparative example, in any region, the metal oxide film of one aspect of the present invention shown in FIG. 21 (D) is observed. A pattern different from a plurality of spots (bright spots) arranged in a circumferential shape was confirmed.

From FIG. 21 (A), it was confirmed that the nanobeam electron diffraction pattern in region a was close to a halo showing amorphousness. It can be inferred that the existence of such a region having low crystallinity is derived from the low density of the film or the high concentration of impurities.

Further, from FIGS. 21 (B) and 21 (C), in the nanobeam electron diffraction pattern of the region b, spots having regularity showing crystals oriented to a specific plane (1 to 1 in FIGS. 21 (B) and 21 (C)). 3) was observed. The results of analyzing the diffraction pattern for this spot are shown in Table 2 below.

<tables num="2"><img file="JP6905042B2_D0002.tif" /></tables>

From Table 2, the measured d value derived from the spot observed in Fig. 21 (B) or Fig. 21 (C) is InGaZnO.₄It is almost the same as the theoretical value in multiple plane orientations, and the In-Ga-Zn oxide film of this comparative example formed by the liquid phase method is partially InZnGaO.₄It was confirmed that there is a crystal region due to.

From the above, although the In-Ga-Zn oxide film produced by the liquid phase method contains impurities, InZnGaO₄It can be said that a region having a periodic atomic arrangement due to the crystal of the above and a region having very low crystallinity and being close to amorphous are mixed.

Next, the effect of impurities such as hydrogen and carbon present in the metal oxide film of the comparative example on the crystallinity of the metal oxide film was evaluated by calculation.

In the calculations shown below, the effect of hydrogen on the crystallization of metal oxide films was investigated from first-principles calculations. Specifically, InGaZnO₄The energy difference between the amorphous state and the crystalline state was investigated when hydrogen was not contained and when hydrogen was contained at 6.67 atom%. In-Ga-Zn-O crystal has an atomic number density of 8.54 × 10²²atoms / cm³From the SIMS analysis results shown in FIG. 18, this hydrogen concentration is equivalent to the hydrogen concentration contained in the metal oxide film of this comparative example. In the calculation, an In-Ga-Zn oxide film having an In: Ga: Zn = 1: 1: 1 [atomic number ratio] was applied as an example of the metal oxide film.

Figure 22 shows the lattice structure of the 112-atom In-Ga-Zn-O crystal used in the calculation.

In the calculation, for the structure shown in FIG. 22, a structure without H added and a structure with 8 H added were created, and each was optimized to calculate the energy. Furthermore, based on the obtained optimized structure, an amorphous structure was created by the following process.

(1) Molecular dynamics calculation in NVT ensemble at a temperature of 3000K. (2) Molecular dynamics calculation in NVT ensemble with temperature 1000K and time 2psec. (3) Structural optimization.

However, in the calculation of (1) above, the structures after 5psec, 5.5psec, and 6psec were taken out, the calculations after (2) were performed, three amorphous structures were created, and the average value of energy was taken. .. The first-principles calculation software "VASP (Vienna Ab-initio Simulation Package)" was used for the calculation. The calculation conditions are shown in Table 3.

<tables num="3"><img file="JP6905042B2_D0003.tif" /></tables>

Figure 23 shows a part of the structure obtained by the calculation, and Table 4 shows the calculation result of the energy difference. FIG. 23 (A) shows the structure of a single crystal In-Ga-Zn oxide film without H addition (0 atom%). FIG. 23 (B) shows the structure of a single crystal In-Ga-Zn oxide film to which 8 Hs are added (6.67 atom%). FIG. 23 (C) shows the structure of an amorphous In-Ga-Zn oxide film without H addition (0 atom%). FIG. 23 (D) shows the structure of an amorphous In-Ga-Zn oxide film to which 8 Hs are added (6.67 atom%).

<tables num="4"><img file="JP6905042B2_D0004.tif" /></tables>

From Table 4, it can be seen that the energy of the In-Ga-Zn oxide film is greatly reduced by crystallization. On the other hand, the addition of H reduces the stabilization energy due to crystallization. From the above, in the metal oxide film produced by the liquid phase method of this comparative example, hydrogen was used as a factor for obtaining a nanobeam electron diffraction pattern close to the halo pattern together with a pattern containing spots showing a periodic atomic arrangement. Destabilization of the crystal structure is presumed.

As shown above, the inclusion of hydrogen, which is an impurity, in the metal oxide film reduces the stability of the crystal. This calculation result shows that the metal oxide film of the comparative example in which the nanobeam electron diffraction pattern close to the halo pattern was confirmed has a higher content of impurities hydrogen and carbon than the metal oxide film of the present embodiment. It is also consistent with that.

As described above, this embodiment can be appropriately combined with other embodiments described in the present specification.

(Embodiment 2) In the present embodiment, a drawing shows a configuration example of a transistor to which a metal oxide film (oxide semiconductor film) exhibiting semiconductor characteristics is applied, which is the metal oxide film exemplified in the first embodiment. Will be described with reference to.

&lt;Transistor Configuration Example&gt; FIG. 9A shows a schematic cross-sectional view of the transistor 100 illustrated below. The transistor 100 is a bottom gate type transistor.

The transistor 100 includes a gate electrode 102 provided on the substrate 101, an insulating layer 103 provided on the substrate 101 and the gate electrode 102, and an oxide semiconductor layer 104 provided on the insulating layer 103 so as to overlap the gate electrode 102. It has a pair of electrodes 105a and 105b in contact with the upper surface of the oxide semiconductor layer 104. Further, the insulating layer 103, the oxide semiconductor layer 104, the insulating layer 106 covering the pair of electrodes 105a and 105b, and the insulating layer 107 are provided on the insulating layer 106.

The oxide semiconductor film of one aspect of the present invention can be applied to the oxide semiconductor layer 104 of the transistor 100.

&lt;&lt; Substrate 101 &gt;&gt; There are no major restrictions on the material of the substrate 101, but at least a material having heat resistance that can withstand the subsequent heat treatment is used. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, a YSZ (yttria-stabilized zirconia) substrate, or the like may be used as the substrate 101. It is also possible to apply a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like. Further, those in which semiconductor elements are provided on these substrates may be used as the substrate 101.

Further, a flexible substrate such as plastic may be used as the substrate 101, and the transistor 100 may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 101 and the transistor 100. The release layer can be used for forming a part or all of the transistor on the upper layer, separating the transistor from the substrate 101, and reprinting the transistor on another substrate. As a result, the transistor 100 can be reprinted on a substrate having poor heat resistance or a flexible substrate.

&lt;&lt; Gate electrode 102 &gt;&gt; The gate electrode 102 uses a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-mentioned metal as a component, an alloy obtained by combining the above-mentioned metals, and the like. Can be formed. Further, a metal selected from any one or more of manganese and zirconium may be used. Further, the gate electrode 102 may have a single-layer structure or a laminated structure having two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, and a tungsten film on which a tungsten film is laminated. A layer structure, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are laminated on the titanium film, and a titanium film is further formed on the titanium film, etc. be. Further, an alloy film in which one or a plurality of metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum, or a nitrided film thereof may be used.

Further, the gate electrode 102 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. , A translucent conductive material such as indium tin oxide to which silicon oxide is added can also be applied. Further, the conductive material having the translucent property and the metal may be laminated.

Further, between the gate electrode 102 and the insulating layer 103, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, and an In-Zn-based film. An oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) and the like may be provided. Since these films have a work function of 5 eV or more or 5.5 eV or more and have a value larger than the electron affinity of the oxide semiconductor, the threshold voltage of the transistor using the oxide semiconductor should be shifted positively. It is possible to realize a switching element with so-called normally-off characteristics. For example, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration higher than that of the oxide semiconductor layer 104, specifically, a nitrogen concentration of 7 atomic% or more is used.

&lt;&lt; Insulation layer 103 &gt;&gt; The insulation layer 103 functions as a gate insulating film. The insulating layer 103 in contact with the lower surface of the oxide semiconductor layer 104 is preferably an amorphous film.

For the insulating layer 103, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, silicon nitride or the like may be used, and the insulating layer 103 may be laminated or single layered. prepare.

Further, as the insulating layer 103, hafnium silicate (HfSiO)_x), Nitrogen-added hafnium silicate (HfSi)_xO_yN_z), Nitrogen-added hafnium aluminate (HfAl)_xO_yN_z), Hafnium oxide, yttrium oxide and other high-k materials can reduce the gate leakage of the transistor.

&lt;&lt; Pair of Electrodes 105a, 105b &gt;&gt; The pair of electrodes 105a and 105b function as a source electrode or a drain electrode of a transistor.

The pair of electrodes 105a and 105b have a single-layer structure or a laminated structure in which a metal composed of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same is used as a conductive material. Can be used as. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, and a copper film on a copper-magnesium-aluminum alloy film. A two-layer structure to be laminated, a titanium film or a titanium nitride film, and a three-layer structure in which an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed on the aluminum film or the copper film. , A molybdenum film or a molybdenum nitride film, an aluminum film or a copper film laminated on the molybdenum film or the molybdenum nitride film, and a three-layer structure in which the molybdenum film or the molybdenum nitride film is further formed. A transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

&lt;&lt; Insulating Layers 106, 107 &gt;&gt; It is preferable to use an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition for the insulating layer 106. A part of oxygen is desorbed from such an oxide insulating film by heating. For example, when such an oxide insulating film is heated at a temperature equal to or higher than the heat treatment temperature in the process of manufacturing a transistor, oxygen converted into oxygen atoms is converted into oxygen atoms by thermal desorption spectroscopy (TDS) analysis. Desorption amount is 1.0 × 10¹⁸atoms / cm³Above, preferably 3.0 × 10²⁰atoms / cm³That is all.

As the insulating layer 106, silicon oxide, silicon oxide nitride, or the like can be used.

The insulating layer 106 also functions as a damage mitigating film for the oxide semiconductor layer 104 when the insulating layer 107 to be formed later is formed.

Further, an oxide film that allows oxygen to pass through may be provided between the insulating layer 106 and the oxide semiconductor layer 104.

As the oxide film that permeates oxygen, silicon oxide, silicon oxide nitride, or the like can be used. In the present specification, the silicon nitride film refers to a film having a higher oxygen content than nitrogen in its composition, and the silicon nitride film has a nitrogen content higher than oxygen in its composition. Refers to a film with a lot of oxygen.

As the insulating layer 107, an insulating film having a blocking effect of oxygen, hydrogen, water or the like can be used. By providing the insulating layer 107 on the insulating layer 106, it is possible to prevent the diffusion of oxygen from the oxide semiconductor layer 104 to the outside and the invasion of hydrogen, water, etc. from the outside into the oxide semiconductor layer 104. Examples of such an insulating film include silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, and hafnium oxide.

&lt;Example of Manufacturing Method of Transistor&gt; Subsequently, an example of the manufacturing method of the transistor 100 illustrated in FIG. 9 will be described.

First, as shown in FIG. 10A, the gate electrode 102 is formed on the substrate 101, and the insulating layer 103 is formed on the gate electrode 102.

Here, a glass substrate is used as the substrate 101.

&lt;&lt; Formation of Gate Electrode &gt;&gt; The method of forming the gate electrode 102 is shown below. First, a conductive film is formed by a sputtering method, a CVD method, a vapor deposition method, or the like, and a resist mask is formed on the conductive film by a photolithography step using a first photomask. Next, a part of the conductive film is etched with the resist mask to form the gate electrode 102. After that, the resist mask is removed.

The gate electrode 102 may be formed by an electrolytic plating method, a printing method, an inkjet method, or the like instead of the above-mentioned forming method.

&lt;&lt; Formation of Gate Insulating Layer &gt;&gt; The insulating layer 103 is formed by a sputtering method, a CVD method, a vapor deposition method, or the like.

When a silicon oxide film, a silicon nitride film, or a silicon nitride film is formed as the insulating layer 103, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide and the like.

When forming a silicon nitride film as the insulating layer 103, it is preferable to use a two-step forming method. First, a first silicon nitride film with few defects is formed by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as a raw material gas. Next, the raw material gas is switched to a mixed gas of silane and nitrogen to form a second silicon nitride film having a low hydrogen concentration and capable of blocking hydrogen. By such a forming method, a silicon nitride film having few defects and having hydrogen blocking property can be formed as the insulating layer 103.

When the gallium oxide film is formed as the insulating layer 103, it can be formed by using the MOCVD (Metal Organic Chemical Vapor Deposition) method.

&lt;&lt; Formation of Oxide Semiconductor Layer &gt;&gt; Next, as shown in FIG. 10B, the oxide semiconductor layer 104 is formed on the insulating layer 103.

The method for forming the oxide semiconductor layer 104 is shown below. First, an oxide semiconductor film is formed by the method exemplified in the first embodiment. Subsequently, a resist mask is formed on the oxide semiconductor film by a photolithography step using a second photomask. Next, a part of the oxide semiconductor film is etched with the resist mask to form the oxide semiconductor layer 104. After that, the resist mask is removed.

After this, heat treatment may be performed. When the heat treatment is performed, it is preferable to perform the heat treatment in an atmosphere containing oxygen.

&lt;&lt; Formation of a pair of electrodes &gt;&gt; Next, as shown in FIG. 10C, a pair of electrodes 105a and 105b are formed.

The method of forming the pair of electrodes 105a and 105b is shown below. First, a conductive film is formed by a sputtering method, a CVD method, a vapor deposition method, or the like. Next, a resist mask is formed on the conductive film by a photolithography step using a third photomask. Next, a part of the conductive film is etched with the resist mask to form a pair of electrodes 105a and 105b. After that, the resist mask is removed.

As shown in FIG. 10B, a part of the upper part of the oxide semiconductor layer 104 may be etched to form a thin film when the conductive film is etched. Therefore, when forming the oxide semiconductor layer 104, it is preferable to set the thickness of the oxide semiconductor film to be thick in advance.

&lt;&lt; Formation of Insulating Layer &gt;&gt; Next, as shown in FIG. 10D, an insulating layer 106 is formed on the oxide semiconductor layer 104 and the pair of electrodes 105a and 105b, and then an insulating layer 106 is formed on the insulating layer 106. Form 107.

When a silicon oxide film or a silicon nitride nitride film is formed as the insulating layer 106, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide and the like.

For example, the substrate placed in the vacuum-exhausted processing chamber of the plasma CVD apparatus is held at 180 ° C or more and 260 ° C or less, more preferably 200 ° C or more and 240 ° C or less, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less, and 0.17 W / cm is applied to the electrodes provided in the processing chamber.²More than 0.5W / cm²Below, more preferably 0.25 W / cm²More than 0.35W / cm²A silicon oxide film or a silicon nitride nitride film is formed under the following conditions for supplying high-frequency power.

By supplying high-frequency power, the decomposition efficiency of the raw material gas increases in the plasma, oxygen radicals increase, and the raw material gas oxidizes, so the oxygen content in the oxide insulating film is higher than the chemical quantity theory ratio. Become. However, in a film formed with the substrate temperature at the above temperature, a part of oxygen in the film is desorbed by heating in a later step. As a result, it is possible to form an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition and desorbing a part of oxygen by heating.

When an oxide insulating film is provided between the oxide semiconductor layer 104 and the insulating layer 106, the oxide insulating film serves as a protective film for the oxide semiconductor layer 104 in the step of forming the insulating layer 106. As a result, the insulating layer 106 can be formed by using high-frequency power having a high power density while reducing damage to the oxide semiconductor layer 104.

For example, the substrate placed in the vacuum-exhausted processing chamber of the plasma CVD apparatus is held at 180 ° C or more and 400 ° C or less, more preferably 200 ° C or more and 370 ° C or less, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is set to 20 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 250 Pa or less, and a silicon oxide film or a silicon nitride nitride film is used as the oxide insulating film under the condition of supplying high frequency power to the electrodes provided in the processing chamber. Can be formed. Further, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, it is possible to reduce damage to the oxide semiconductor layer 104 when the oxide insulating layer is formed.

As the raw material gas for the oxide insulating film, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide and the like.

The insulating layer 107 can be formed by a sputtering method, a CVD method, or the like.

When a silicon nitride film or a silicon nitride film is formed as the insulating layer 107, it is preferable to use a depositary gas containing silicon, an oxidizing gas, and a gas containing nitrogen as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide and the like. Examples of the gas containing nitrogen include nitrogen, ammonia and the like.

The transistor 100 can be formed by the above steps.

&lt;Modification Example of Transistor 100&gt; Hereinafter, a configuration example of a transistor that is partially different from the transistor 100 will be described.

&lt;&lt; Modification 1 &gt;&gt; FIG. 9B shows a schematic cross-sectional view of the transistor 110 illustrated below. The transistor 110 is different from the transistor 100 in that the structure of the oxide semiconductor layer is different. In the following, components having the same configuration as other configuration examples or components having the same function will be designated by the same reference numerals, and duplicate description will be omitted.

The oxide semiconductor layer 114 included in the transistor 110 is formed by laminating the oxide semiconductor layer 114a and the oxide semiconductor layer 114b.

Since the boundary between the oxide semiconductor layer 114a and the oxide semiconductor layer 114b may be unclear, these boundaries are shown by broken lines in the drawings such as FIG. 9B.

The oxide semiconductor film of one aspect of the present invention can be applied to either or both of the oxide semiconductor layer 114a and the oxide semiconductor layer 114b.

For example, the oxide semiconductor layer 114a is typically an In-Ga oxide, an In-Zn oxide, or an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd. , Or Hf). Further, when the oxide semiconductor layer 114a is an In-M-Zn oxide, the atomic number ratio of In and M excluding Zn and oxygen is preferably 100 atomic% when the total of In and M is 100 atomic%. 25atomic% or more, M is less than 75atomic%, more preferably In is 34atomic% or more and M is less than 66atomic%. Further, for example, the oxide semiconductor layer 114a uses a material having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more.

For example, the oxide semiconductor layer 114b contains In or Ga, and typically In-Ga oxide, In-Zn oxide, or In-M-Zn oxide (M is Al, Ti, Ga, Y, It contains Zr, La, Ce, Nd or Hf), and the energy level at the lower end of the conduction band is closer to the vacuum level than the oxide semiconductor layer 114a. Typically, the difference between the energy level at the lower end of the conduction band of the oxide semiconductor layer 114b and the energy level at the lower end of the conduction band of the oxide semiconductor layer 114a is 0.05 eV or more, 0.07 eV or more, 0.1 eV. It is preferably 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

Further, for example, when the oxide semiconductor layer 114b is an In-M-Zn oxide, the atomic number ratio of In and M excluding Zn and oxygen is preferably In, assuming that the total of In and M is 100 atomic%. Is less than 50atomic%, M is 50atomic% or more, and more preferably In is less than 25atomic% and M is 75atomic% or more.

For example, a target having an atomic number ratio of In: Ga: Zn = 1: 1: 1 or 3: 1: 2 can be used as the oxide semiconductor layer 114a. Further, as the oxide semiconductor layer 114b, a target having an atomic number ratio of In: Ga: Zn = 1: 3: 2, 1: 6: 4, or 1: 9: 6 can be used. The atomic number ratios of the oxide semiconductor layer 114a and the oxide semiconductor layer 114b may differ from the atomic number ratio of the target used, and there may be a difference of plus or minus 20%.

By using an oxide having a high content of Ga that functions as a stabilizer for the oxide semiconductor layer 114b provided in the upper layer, it is possible to suppress the release of oxygen from the oxide semiconductor layer 114a and the oxide semiconductor layer 114b. can.

In addition, the present invention is not limited to these, and a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, the carrier density and impurity concentration of the oxide semiconductor layer 114a and the oxide semiconductor layer 114b, the defect density, the atomic number ratio between the metal element and oxygen, the interatomic distance, the density, etc. Is preferably appropriate.

Although the configuration in which two oxide semiconductor layers are laminated is illustrated above as the oxide semiconductor layer 114, a configuration in which three or more oxide semiconductor layers are laminated may be used.

&lt;&lt; Modification 2 &gt;&gt; FIG. 9 (C) shows a schematic cross-sectional view of the transistor 120 illustrated below. The transistor 120 is different from the transistor 100 and the transistor 110 in that the structure of the oxide semiconductor layer is different.

The oxide semiconductor layer 124 included in the transistor 120 is configured by laminating the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c in this order.

The oxide semiconductor layer 124a and the oxide semiconductor layer 124b are provided by being laminated on the insulating layer 103. The oxide semiconductor layer 124c is provided in contact with the upper surface of the oxide semiconductor layer 124b and the upper surfaces and side surfaces of the pair of electrodes 105a and 105b.

The oxide semiconductor film of one aspect of the present invention can be applied to any one, any two, or all of the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c.

For example, as the oxide semiconductor layer 124b, the same configuration as that of the oxide semiconductor layer 114a illustrated in the first modification can be used. Further, for example, as the oxide semiconductor layers 124a and 124c, the same configuration as that of the oxide semiconductor layer 114b exemplified in the above modification 1 can be used.

For example, by using an oxide having a high content of Ga that functions as a stabilizer for the oxide semiconductor layer 124a and the oxide semiconductor layer 124c, the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c are used. It is possible to suppress the release of oxygen from.

Further, for example, when a channel is mainly formed in the oxide semiconductor layer 124b, an oxide having a high content of In is used in the oxide semiconductor layer 124b, and a pair of electrodes 105a and 105b are brought into contact with the oxide semiconductor layer 124b. By providing it, the on-current of the transistor 120 can be increased.

&lt;Other Configuration Examples of Transistors&gt; Hereinafter, configuration examples of top gate type transistors to which the oxide semiconductor film of one aspect of the present invention can be applied will be described.

&lt;&lt; Configuration Example &gt;&gt; FIG. 11 (A) shows a schematic cross-sectional view of the top gate type transistor 150 illustrated below.

The transistor 150 includes an oxide semiconductor layer 104 provided on a substrate 101 provided with an insulating layer 151, a pair of electrodes 105a and 105b in contact with the upper surface of the oxide semiconductor layer 104, and a pair of oxide semiconductor layers 104 and electrodes. It has an insulating layer 103 provided on 105a and 105b, and a gate electrode 102 provided on the insulating layer 103 so as to overlap the oxide semiconductor layer 104. Further, the insulating layer 152 is provided so as to cover the insulating layer 103 and the gate electrode 102.

The oxide semiconductor film of one aspect of the present invention can be applied to the oxide semiconductor layer 104 of the transistor 150.

The insulating layer 151 has a function of suppressing the diffusion of impurities from the substrate 101 to the oxide semiconductor layer 104. For example, the same configuration as the insulating layer 107 can be used. The insulating layer 151 may not be provided if it is unnecessary.

Similar to the insulating layer 107, an insulating film having a blocking effect on oxygen, hydrogen, water, etc. can be applied to the insulating layer 152. The insulating layer 107 may not be provided if it is unnecessary.

&lt;&lt; Deformation Example &gt;&gt; A configuration example of a transistor that is partially different from the transistor 150 will be described below.

FIG. 11B shows a schematic cross-sectional view of the transistor 160 illustrated below. The transistor 160 is different from the transistor 150 in that the structure of the oxide semiconductor layer is different.

The oxide semiconductor layer 164 included in the transistor 160 is configured by laminating an oxide semiconductor layer 164a, an oxide semiconductor layer 164b, and an oxide semiconductor layer 164c in this order.

The oxide semiconductor film of one aspect of the present invention can be applied to any one, any two, or all of the oxide semiconductor layer 164a, the oxide semiconductor layer 164b, and the oxide semiconductor layer 164c.

For example, as the oxide semiconductor layer 164b, the same configuration as that of the oxide semiconductor layer 114a illustrated in the first modification can be used. Further, for example, as the oxide semiconductor layers 164a and 164c, the same configuration as that of the oxide semiconductor layer 114b exemplified in the above modification 1 can be used.

For example, by using an oxide having a high content of Ga that functions as a stabilizer for the oxide semiconductor layer 164a and the oxide semiconductor layer 164c, the oxide semiconductor layer 164a, the oxide semiconductor layer 164b, and the oxide semiconductor layer 164c can be separated. It is possible to suppress the release of oxygen.

When the oxide semiconductor layer 164 is formed, the oxide semiconductor layer 164c and the oxide semiconductor layer 164b are processed by etching to expose the oxide semiconductor film to be the oxide semiconductor layer 164a, and then by a dry etching method. When the oxide semiconductor film is processed to form the oxide semiconductor layer 164a, the reaction product of the oxide semiconductor film reattaches to the side surfaces of the oxide semiconductor layer 164b and the oxide semiconductor layer 164c, and the side wall surface is formed. A protective layer (also called a rabbit ear) may be formed. The reaction product may be reattached by the sputtering phenomenon or may be reattached during dry etching.

FIG. 11C shows a schematic cross-sectional view of the transistor 161 when the side wall protective layer 164d is formed on the side surface of the oxide semiconductor layer 164 as described above. Other configurations of the transistor 161 are the same as those of the transistor 160.

The side wall protective layer 164d mainly contains the same material as the oxide semiconductor layer 164a. Further, the side wall protective layer 164d may contain a component (for example, silicon) of a layer (here, an insulating layer 151) provided under the oxide semiconductor layer 164a.

Further, as shown in FIG. 11C, the side surface of the oxide semiconductor layer 164b is covered with the side wall protective layer 164d so as not to be in contact with the pair of electrodes 105a and 105b, so that the oxide semiconductor layer 164b is mainly used. When a channel is formed, an unintended leakage current when the transistor is turned off can be suppressed, and a transistor having excellent off characteristics can be realized. Further, by using a material having a high content of Ga that functions as a stabilizer as the side wall protective layer 164d, the desorption of oxygen from the side surface of the oxide semiconductor layer 164b is effectively suppressed, and the stability of electrical characteristics is improved. An excellent transistor can be realized.

This embodiment can be implemented in combination with other embodiments described herein as appropriate.

(Embodiment 3) In the present embodiment, the configuration of the display panel according to one aspect of the present invention will be described with reference to FIG.

FIG. 12 (A) is a top view of the display panel of one aspect of the present invention, and FIG. 12 (B) can be used when applying a liquid crystal element to the pixels of the display panel of one aspect of the present invention. It is a circuit diagram for demonstrating a pixel circuit. Further, FIG. 12C is a circuit diagram for explaining a pixel circuit that can be used when an organic EL element is applied to the pixels of the display panel of one aspect of the present invention.

The transistor arranged in the pixel portion can be formed according to the second embodiment. Further, since the transistor can be easily made into an n-channel type, a part of the drive circuit that can be composed of the n-channel type transistor is formed on the same substrate as the transistor of the pixel portion. As described above, by using the transistor shown in the second embodiment for the pixel unit and the drive circuit, it is possible to provide a highly reliable display device.

An example of a block diagram of the active matrix type display device is shown in FIG. 12 (A). A pixel unit 501, a first scanning line driving circuit 502, a second scanning line driving circuit 503, and a signal line driving circuit 504 are provided on the substrate 500 of the display device. A plurality of signal lines are extended from the signal line drive circuit 504 and arranged in the pixel unit 501, and a plurality of scan lines are arranged so as to extend from the first scan line drive circuit 502 and the scan line drive circuit 503. There is. In the intersection region of the scanning line and the signal line, pixels having a display element are provided in a matrix. Further, the board 500 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

In FIG. 12A, the first scanning line driving circuit 502, the second scanning line driving circuit 503, and the signal line driving circuit 504 are formed on the same substrate 500 as the pixel unit 501. Therefore, the number of parts such as a drive circuit provided externally can be reduced, and the cost can be reduced. Further, when the drive circuit is provided outside the board 500, the number of connections between the wirings increases because it is necessary to extend the wiring, but by providing the drive circuit on the same board 500, the number of connections between the wirings is reduced. be able to. Therefore, it is possible to improve the reliability of the semiconductor device or the yield.

&lt;Liquid crystal panel&gt; An example of the pixel circuit configuration is shown in FIG. 12 (B). Here, a pixel circuit that can be applied to the pixels of a VA type liquid crystal display panel is shown.

This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. As a result, the signal applied to each pixel electrode layer of the multi-domain designed pixel can be independently controlled.

The gate wiring 512 of the transistor 516 and the gate wiring 513 of the transistor 517 are separated so that different gate signals can be given. On the other hand, the source electrode layer or the drain electrode layer 514 that functions as a data line is commonly used in the transistor 516 and the transistor 517. As the transistor 516 and the transistor 517, the transistor described in the second embodiment can be appropriately used. This makes it possible to provide a highly reliable liquid crystal display panel.

The shapes of the first pixel electrode layer electrically connected to the transistor 516 and the second pixel electrode layer electrically connected to the transistor 517 will be described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V-shaped spreading shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

The gate electrode of the transistor 516 is connected to the gate wiring 512, and the gate electrode of the transistor 517 is connected to the gate wiring 513. By giving different gate signals to the gate wiring 512 and the gate wiring 513 to make the operation timings of the transistor 516 and the transistor 517 different, the orientation of the liquid crystal display can be controlled.

Further, the holding capacitance may be formed by the capacitive wiring 510, the gate insulating film that functions as a dielectric, and the capacitive electrode that is electrically connected to the first pixel electrode layer or the second pixel electrode layer.

The multi-domain structure includes a first liquid crystal element 518 and a second liquid crystal element 519 in one pixel. The first liquid crystal element 518 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer in between, and the second liquid crystal element 519 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer in between. Consists of.

The pixel circuit shown in FIG. 12B is not limited to this. For example, a switch, a resistance element, a capacitance element, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel shown in FIG. 12 (B).

&lt;Organic EL panel&gt; Another example of the pixel circuit configuration is shown in FIG. 12 (C). Here, the pixel structure of the display panel using the organic EL element is shown.

In the organic EL element, by applying a voltage to the light emitting element, electrons are injected from one of the pair of electrodes and holes are injected into the layer containing the luminescent organic compound from the other, and a current flows. Then, by recombination of electrons and holes, the luminescent organic compound forms an excited state, and when the excited state returns to the ground state, it emits light. From such a mechanism, such a light emitting element is called a current excitation type light emitting element.

FIG. 12C is a diagram showing an example of an applicable pixel circuit. Here, an example in which two n-channel type transistors are used for one pixel is shown. The metal oxide film of one aspect of the present invention can be used in the channel forming region of an n-channel transistor. Further, the pixel circuit can be driven by digital time gradation.

The configuration of the applicable pixel circuit and the operation of the pixel when the digital time gradation drive is applied will be described.

The pixel 520 includes a switching transistor 521, a driving transistor 522, a light emitting element 524, and a capacitive element 523. In the switching transistor 521, the gate electrode layer is connected to the scanning line 526, the first electrode (one of the source electrode layer and the drain electrode layer) is connected to the signal line 525, and the second electrode (source electrode layer and drain electrode layer) is connected. The other) is connected to the gate electrode layer of the driving transistor 522. In the drive transistor 522, the gate electrode layer is connected to the power supply line 527 via the capacitive element 523, the first electrode is connected to the power supply line 527, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 524. It is connected. The second electrode of the light emitting element 524 corresponds to the common electrode 528. The common electrode 528 is electrically connected to a common potential line formed on the same substrate.

As the switching transistor 521 and the driving transistor 522, the transistor described in the second embodiment can be appropriately used. This makes it possible to provide a highly reliable organic EL display panel.

The potential of the second electrode (common electrode 528) of the light emitting element 524 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential set in the power supply line 527, and for example, GND, 0V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the forward threshold voltage of the light emitting element 524, and the potential difference is applied to the light emitting element 524 to cause a current to flow through the light emitting element 524 to emit light. The forward voltage of the light emitting element 524 refers to a voltage at which the desired brightness is obtained, and is at least larger than the forward threshold voltage.

The capacitive element 523 can be omitted by substituting the gate capacitance of the driving transistor 522. Regarding the gate capacitance of the driving transistor 522, a capacitance may be formed between the channel forming region and the gate electrode layer.

Next, the signal input to the drive transistor 522 will be described. Voltage input In the case of the voltage drive system, a video signal is input to the drive transistor 522 so that the drive transistor 522 is surely turned on or off. In order to operate the drive transistor 522 in the linear region, a voltage higher than the voltage of the power supply line 527 is applied to the gate electrode layer of the drive transistor 522. Further, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the power supply line voltage is applied to the signal line 525.

When analog gradation driving is performed, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. A video signal is input so that the driving transistor 522 operates in the saturation region, and a current is passed through the light emitting element 524. Further, in order to operate the drive transistor 522 in the saturation region, the potential of the power supply line 527 is set higher than the gate potential of the drive transistor 522. By making the video signal analog, a current corresponding to the video signal can be passed through the light emitting element 524 to perform analog gradation drive.

The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. 12 (C). For example, a switch, a resistance element, a capacitance element, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit shown in FIG. 12 (C).

(Embodiment 4) In the present embodiment, the configuration of a semiconductor device and an electronic device using the metal oxide film of one aspect of the present invention will be described with reference to FIGS. 13 and 14.

FIG. 13 is a block diagram of an electronic device including a semiconductor device to which the metal oxide film of one aspect of the present invention is applied.

FIG. 14 is an external view of an electronic device including a semiconductor device to which the metal oxide film of one aspect of the present invention is applied.

The electronic devices shown in FIG. 13 are RF circuit 901, analog baseband circuit 902, digital baseband circuit 903, battery 904, power supply circuit 905, application processor 906, flash memory 910, display controller 911, memory circuit 912, display 913, and touch. It consists of a sensor 919, an audio circuit 917, a keyboard 918, and so on.

The application processor 906 has a CPU 907, a DSP 908, and an interface (IF) 909. Further, the memory circuit 912 can be configured by SRAM or DRAM.

By applying the transistor described in the second embodiment to the memory circuit 912, it is possible to provide a highly reliable electronic device capable of writing and reading information.

Further, by applying the transistor described in the second embodiment to a register or the like included in the CPU 907 or the DSP 908, it is possible to provide a highly reliable electronic device capable of writing and reading information.

When the off-leakage current of the transistor described in the second embodiment is extremely small, it is possible to provide the memory circuit 912 capable of holding memory for a long period of time and having sufficiently reduced power consumption. Further, it is possible to provide a CPU 907 or a DSP 908 capable of storing a state before power gating in a register or the like during a period of power gating.

The display 913 is composed of a display unit 914, a source driver 915, and a gate driver 916.

The display unit 914 has a plurality of pixels arranged in a matrix. The pixel comprises a pixel circuit, which is electrically connected to the gate driver 916.

The transistor described in the second embodiment can be appropriately used for the pixel circuit or the gate driver 916. This makes it possible to provide a highly reliable display.

Examples of electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, cameras such as digital video cameras, digital photo frames, and mobile phones (mobile phones, mobile phones). (Also called a device), a portable game machine, a mobile information terminal, a sound reproduction device, a large game machine such as a pachinko machine, and the like.

FIG. 14A is a portable information terminal, which is composed of a main body 1001, a housing 1002, display units 1003a, 1003b, and the like. The display unit 1003b is a touch panel, and screen operations and character input can be performed by touching the keyboard button 1004 displayed on the display unit 1003b. Of course, the display unit 1003a may be configured as a touch panel. By manufacturing a liquid crystal panel or an organic light emitting panel using the transistor shown in the second embodiment as a switching element and applying it to the display units 1003a and 1003b, a highly reliable portable information terminal can be obtained.

The portable information terminal shown in FIG. 14 (A) has a function of displaying various information (still images, moving images, text images, etc.), a function of displaying a calendar, a date or time, etc. on the display unit, and a function of displaying on the display unit. It can have a function of manipulating or editing the information, a function of controlling processing by various software (programs), and the like. Further, the back surface or the side surface of the housing may be provided with an external connection terminal (earphone terminal, USB terminal, etc.), a recording medium insertion portion, or the like.

Further, the portable information terminal shown in FIG. 14A may be configured to be able to transmit and receive information wirelessly. It is also possible to purchase and download desired book data or the like from an electronic book server wirelessly.

FIG. 14B shows a portable music player, and the main body 1021 is provided with a display unit 1023, a fixed unit 1022 for attaching to the ear, a speaker, an operation button 1024, an external memory slot 1025, and the like. By manufacturing a liquid crystal panel or an organic light emitting panel using the transistor shown in the second embodiment as a switching element and applying it to the display unit 1023, a more reliable portable music player can be obtained.

Furthermore, if the portable music player shown in Fig. 14 (B) is equipped with an antenna, microphone function, and wireless function and is linked with a mobile phone, wireless hands-free conversation is possible while driving a passenger car or the like.

FIG. 14C shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 is provided with a display panel 1032, a speaker 1033, a microphone 1034, a pointing device 1036, a camera lens 1037, an external connection terminal 1038, and the like. In addition, the housing 1030 is provided with a solar cell 1040 for charging a mobile phone, an external memory slot 1041 and the like. In addition, the antenna is built in the housing 1031. By applying the transistor described in the second embodiment to the display panel 1032, a highly reliable mobile phone can be obtained.

Further, the display panel 1032 is provided with a touch panel, and in FIG. 14C, a plurality of operation keys 1035 displayed as images are shown by dotted lines. A booster circuit for boosting the voltage output by the solar cell 1040 to the voltage required for each circuit is also mounted.

For example, a power transistor used in a power supply circuit such as a booster circuit can also be formed by setting the thickness of the metal oxide film of the transistor described in the second embodiment to 2 μm or more and 50 μm or less.

The display direction of the display panel 1032 changes as appropriate according to the usage pattern. In addition, since the camera lens 1037 is provided on the same surface as the display panel 1032, it is possible to make a videophone call. The speaker 1033 and the microphone 1034 are not limited to voice calls, but can be used for videophones, recording, playback, and the like. Further, the housing 1030 and the housing 1031 can be slid and changed from the unfolded state as shown in FIG. 14C to the overlapping state, and can be miniaturized to be suitable for carrying.

The external connection terminal 1038 can be connected to various cables such as an AC adapter and a USB cable, and can be charged and data communication with a personal computer or the like is possible. Further, a recording medium can be inserted into the external memory slot 1041 to support storage and movement of a larger amount of data.

Further, in addition to the above functions, an infrared communication function, a television reception function, and the like may be provided.

FIG. 14 (D) shows an example of a television device. In the television device 1050, the display unit 1053 is incorporated in the housing 1051. The display unit 1053 can display an image. In addition, the CPU is built into the stand 1055 that supports the chassis 1051. By applying the transistor described in the second embodiment to the display unit 1053 and the CPU, a highly reliable television device 1050 can be obtained.

The operation of the television device 1050 can be performed by the operation switch provided in the housing 1051 or a separate remote control operation device. Further, the remote controller operating device may be provided with a display unit for displaying information output from the remote controller operating device.

The television device 1050 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via a modem, it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between (or between recipients, etc.).

Further, the television device 1050 includes an external connection terminal 1054, a storage medium playback / recording unit 1052, and an external memory slot. The external connection terminal 1054 can be connected to various cables such as a USB cable, and can perform data communication with a personal computer or the like. The storage medium reproduction recording unit 1052 can insert a disc-shaped recording medium, read data stored in the recording medium, and write data to the recording medium. It is also possible to display images and videos stored in the external memory 1056 inserted in the external memory slot on the display unit 1053.

Further, when the off-leakage current of the transistor described in the second embodiment is extremely small, the power consumption is sufficiently reduced by applying the transistor to the external memory 1056 or the CPU to obtain a highly reliable television device 1050. can do.

100 Transistor 101 Substrate 102 Gate electrode 103 Insulation layer 104 Oxide semiconductor layer 105a Electrode 105b Electrode 106 Insulation layer 107 Insulation layer 110 Transistor 114 Oxide semiconductor layer 114a Oxide semiconductor layer 114b Oxide semiconductor layer 120 Transistor 124 Oxide semiconductor layer 124a Oxidation Material Semiconductor layer 124b Oxide semiconductor layer 124c Oxide semiconductor layer 150 Transistor 151 Insulation layer 152 Insulation layer 160 Transistor 161 Transistor 164 Oxide semiconductor layer 164a Oxide semiconductor layer 164b Oxide semiconductor layer 164c Oxide semiconductor layer 164d Side wall protection layer 200 Quartz glass substrate 202 Dummy substrate 204 Metal oxide film 210a Region 210b Region 500 Substrate 501 Pixel part 502 Scanning line drive circuit 503 Scanning line drive circuit 504 Signal line drive circuit 510 Capacitive wiring 512 Gate wiring 513 Gate wiring 514 Drain electrode layer 516 Transistor 517 Transistor 518 Liquid crystal element 519 Liquid crystal element 520 Pixel 521 Switching transistor 522 Driving transistor 523 Capacitive element 524 Light emitting element 525 Signal line 526 Scan line 527 Power line 528 Common electrode 901 RF circuit 902 Analog baseband circuit 903 Digital baseband circuit 904 Battery 905 Power supply circuit 906 Application processor 907 CPU908 DSP910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display 915 Source driver 916 Gate driver 917 Voice circuit 918 Keyboard 919 Touch sensor 1001 Main unit 1002 Housing 1003a Display 1003b Display 1004 Keyboard button 1021 Main unit 1022 Fixed part 1023 Display part 1024 Operation button 1025 External memory slot 1030 Housing 1031 Housing 1032 Display panel 1033 Speaker 1034 Microphone 1035 Operation key 1036 Pointing device 1037 Camera lens 1038 External connection terminal 1040 Solar cell 1041 External memory slot 1050 Television device 1051 Housing 1052 Storage medium playback Recording unit 1053 Display unit 1054 External connection terminal 1055 Stand 1056 External memory