Semiconductor device and electronic device

One aspect of the present invention relates to a capacitive element and a semiconductor device having a capacitive element.

One aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, imaging devices, and the like. The driving method or the manufacturing method thereof can be given as an example.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor device such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of the semiconductor device. An image pickup device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, etc.), and an electronic device may have a semiconductor device.

Attention is being paid to a technique for constructing a transistor using a semiconductor material. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also referred to simply as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Document 1 and Patent Document 2).

Further, in recent years, with the increase in performance, miniaturization, or weight reduction of electronic devices, there is an increasing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are integrated at high density. For example, a Tri-Gate transistor and a MIM capacitance element having a COB (capacitor over bitline) structure have been introduced (Non-Patent Document 1).

<p><patcit num="1"><text>JP-A-2007-123861</text></patcit><patcit num="2"><text>JP-A-2007-96055</text></patcit></p>

<p><nplcit num="1"><text>R.Brain et al., "A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-gate Transistors and MIMCAP COB", 2013 SYMPOSIUM ON VLSI TECHNOLOGY 2-1</text></nplcit></p>

<p>One aspect of the present invention is to provide a semiconductor device suitable for miniaturization and high density.</p><p>Alternatively, one of the tasks is to impart good electrical characteristics to the semiconductor device. Alternatively, one of the issues is to provide a highly reliable semiconductor device. Alternatively, one of the issues is to provide a semiconductor device having a new configuration.</p><p>The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract issues other than these from the description of the description, drawings, claims, etc. Is.</p>

<p>One aspect of the present invention includes a first electrode having a convex portion, a first insulator on the convex portion, a second insulator covering the first electrode and the first insulator, and a second. It has a second electrode on the insulator, and the side periphery of the second electrode has a region overlapping with the first electrode via the first insulator and the second insulator. ..</p><p>The side periphery is a region consisting of ends along the side surface of the shape. In particular, when used for a structure forming a capacitive element in the present specification, it is a region where a leak current (also referred to as an edge leak) can occur at an end of the structure. For example, the lateral periphery of the second electrode is the periphery including the end of the first electrode and the second electrode where leakage current may occur.</p><p>One aspect of the present invention is a first electrode having a convex portion, a first insulator on the convex portion, a second insulator covering the first electrode and the first insulator, and a second. It has a second electrode on the insulator, and the second electrode has a first region that overlaps the first electrode via the first insulator and the second insulator, and a second insulation. It has a second region that overlaps the first electrode through the body, and the lateral periphery of the second electrode is in the first region.</p><p>Further, in the above configuration, the first electrode is electrically connected to the transistor.</p><p>Further, in the above configuration, the transistor has a third electrode, and the third electrode is provided on a conductor common to the first electrode.</p><p>Further, one aspect of the present invention is an electronic device having the above configuration and at least one of a display device, a microphone, a speaker, an operation key, a touch panel, or an antenna.</p>

<p>According to one aspect of the present invention, it is possible to provide a semiconductor device suitable for miniaturization and high density.</p><p>Alternatively, good electrical characteristics can be imparted to the semiconductor device. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device or the like having a new configuration can be provided. The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.</p>

<figref num="1">The top view of the capacitive element and the figure explaining the laminated structure which concerns on embodiment.</figref><figref num="2">The figure explaining the laminated structure of the capacitive element which concerns on embodiment.</figref><figref num="3">The top view of the capacitive element and the figure explaining the laminated structure which concerns on embodiment.</figref><figref num="4">The figure explaining the example of the manufacturing method of the capacitive element which concerns on embodiment.</figref><figref num="5">The figure explaining the example of the manufacturing method of the capacitive element which concerns on embodiment.</figref><figref num="6">The figure explaining the example of the manufacturing method of the capacitive element which concerns on embodiment.</figref><figref num="7">A configuration example and a circuit diagram of a semiconductor device according to an embodiment.</figref><figref num="8">A configuration example of a transistor according to an embodiment.</figref><figref num="9">The top view of the transistor and the figure explaining the laminated structure which concerns on embodiment.</figref><figref num="10">The top view of the transistor and the figure explaining the laminated structure which concerns on embodiment.</figref><figref num="11">A configuration example of a transistor according to an embodiment.</figref><figref num="12">A configuration example of a transistor according to an embodiment.</figref><figref num="13">The figure explaining the example of the manufacturing method of the semiconductor device which concerns on embodiment.</figref><figref num="14">The figure explaining the example of the manufacturing method of the semiconductor device which concerns on embodiment.</figref><figref num="15">A configuration example of a semiconductor device according to an embodiment.</figref><figref num="16">A configuration example of a semiconductor device according to an embodiment.</figref><figref num="17">Cs-corrected high-resolution TEM image in the cross section of CAAC-OS, and schematic cross section of CAAC-OS.</figref><figref num="18">Cs-corrected high-resolution TEM image in the plane of CAAC-OS.</figref><figref num="19">The figure explaining the structural analysis by XRD of CAAC-OS and a single crystal oxide semiconductor.</figref><figref num="20">The figure which shows the electron diffraction pattern of CAAC-OS.</figref><figref num="21">The figure which shows the change of the crystal part by electron irradiation of In-Ga-Zn oxide.</figref><figref num="22">A cross-sectional view and a circuit diagram showing one aspect of a semiconductor device.</figref><figref num="23">The cross-sectional view which shows one aspect of the semiconductor device.</figref><figref num="24">The cross-sectional view which shows one aspect of the semiconductor device.</figref><figref num="25">A circuit diagram showing one aspect of a semiconductor device.</figref><figref num="26">Configuration example of RF device tag according to the embodiment.</figref><figref num="27">CPU configuration example according to the embodiment.</figref><figref num="28">The circuit diagram of the storage element which concerns on embodiment.</figref><figref num="29">A cross-sectional view, a top view, and a circuit diagram of a display device according to an embodiment.</figref><figref num="30">A cross-sectional view and a circuit diagram of a display device according to an embodiment.</figref><figref num="31">An electronic device according to an embodiment.</figref><figref num="32">An example of using an RF device tag according to an embodiment.</figref>

The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same reference numerals are commonly used in different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular sign may be added.

In each of the figures described herein, the size, layer thickness, or region of each configuration may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

The ordinal numbers such as "first" and "second" in the present specification and the like are added to avoid confusion of the components, and are not limited numerically.

A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. Transistors in the present specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

In addition, in this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of -5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

The word "membrane" and the word "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

(Embodiment 1) [Configuration Example]

FIG. 1A shows an example of a top view of the capacitive element 300. FIG. 1 (B) is a cross-sectional view corresponding to the alternate long and short dash line AB shown in FIG. 1 (A).

The capacitive element 300 is provided on the insulating film 301 and has a first electrode 302 including the conductive layer 302a and the conductive layer 302b, a barrier layer 303, an insulator 304, and a second electrode 305.

For the conductive layer 302a and the conductive layer 302b, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. The conductive layer 302a and the conductive layer 302b may be formed of different materials or may be formed of the same material.

Further, by forming the conductive layer 302b on the conductive layer 302a so that a part of the conductive layer 302a is exposed, the first electrode 302 has a shape having undulations on the surface. Although the case where the conductive layer 302a and the conductive layer 302b are used to form the uneven portion is shown here, the uneven portion is formed by processing one conductive layer or a plurality of laminated conductive layers of three or more layers. A first electrode 302 having a shape may be formed. Further, the shape of the conductive layer 302b may be provided at least in a region overlapping the peripheral side of the second electrode 305, and an optimum shape may be appropriately designed. For example, FIG. 1 shows an example in which the conductive layer 302b has a quadrangular island shape having an opening, but the conductive layer 302b may be polygonal or circular.

The barrier layer 303 is provided on the upper surface of the conductive layer 302b. By providing the barrier layer 303, it is possible to reduce the shape defect of the capacitive element 300. As the barrier layer 303, an insulating film such as a silicon oxide film or a gallium oxide film, or a semiconductor film such as an oxide semiconductor film can be used.

The insulator 304 is provided so as to cover the conductive layer 302a, the conductive layer 302b, and the barrier layer 303. For the insulator 304, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride or the like may be used, and the insulator 304 is provided in a laminated or single layer.

The second electrode 305 is provided on the first electrode 302 via the barrier layer 303 and the insulator 304. For the second electrode 305, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten.

The second electrode 305 is provided so that the peripheral side thereof overlaps the conductive layer 302b via the barrier layer 303 and the insulator 304.

In the capacitive element 300, the peripheral side of the second electrode 305 overlaps with the conductive layer 302b via the barrier layer 303. Therefore, the distance between the second electrode 305 and the first electrode 302 increases at least due to the thickness of the barrier layer 303 around the side. Therefore, it is possible to suppress the shape defect of the capacitance element 300 according to one aspect of the present invention and provide a highly reliable capacitance element.

The capacitive element 300 can form a three-dimensional capacitive element by having the first electrode 302 having undulations. As a result, the capacitance per projected area of the capacitive element can be increased, so that the area of the semiconductor device can be reduced, highly integrated, and miniaturized.

The above is the description of the configuration example.

&lt;Application Example 1&gt; Further, as an application example of the present embodiment, a plurality of capacitive elements 300 can be stacked and used as shown in FIGS. 2 (A) and 2 (B). Fig. 2 (A) is connected in parallel, and Fig. 2 (B) is connected in series. Although FIG. 2 shows a case where two capacitance elements 300 are laminated, it is also possible to stack three or more capacitance elements 300, if necessary.

With this configuration, a three-dimensional capacitive element can be formed. As a result, the capacitance per projected area of the capacitive element can be increased, so that the area of the semiconductor device can be reduced, highly integrated, and miniaturized.

&lt;Modification Example 1&gt; Further, as a modification of the present embodiment, as shown in FIG. 3, a convex portion may be provided in the groove portion of the first electrode 302 of the capacitance element 300 by using the conductive layer 302b. The shape of the convex portion may be appropriately designed to be optimal. For example, in addition to the striped shape (lattice), if it is an island shape, it may be a quadrangular pyramid, a truncated cone, a truncated cone, a polygonal column, or a cylinder. Further, the undulating portions do not necessarily have to be formed in an aligned manner, and may be formed irregularly.

By having the convex portion, the capacitance per projected area of the capacitive element can be further increased, so that the area of the semiconductor device can be reduced, highly integrated, and miniaturized.

[Example of manufacturing method]

Hereinafter, an example of the method for manufacturing the capacitive element shown in FIG. 3 will be described with reference to FIGS. 4 to 6.

First, the conductive film 302A is formed on the insulating film 301 (FIG. 4 (A)). The insulating film 301 may be made of, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, or the like, and is provided in a laminated or single layer. The insulating film 301 can be formed by using a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film 301 by a CVD method, preferably a plasma CVD method, because the coverage can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Further, as the conductive film 302A, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium and the like, or an alloy material or compound material containing these metals as a main component. Further, polycrystalline silicon to which impurities such as phosphorus are added can be used. Further, a laminated structure of the metal nitride film and the above-mentioned metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

The conductive film 302A can be formed by a sputtering method, a vapor deposition method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.) and the like. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Subsequently, a resist mask 319 is formed on the conductive film 302A by a lithography method or the like, and an unnecessary portion of the conductive film 302A is removed. After that, the conductive layer 302a can be formed by removing the resist mask 319 (FIG. 4 (B)).

Here, a method for processing the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a lithography method or the like may be used. Further, a dummy pattern may be formed by a lithography method or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the remaining sidewall may be used as a resist mask to etch the film to be processed. Further, as the etching of the film to be processed, it is preferable to use anisotropic dry etching in order to realize a high aspect ratio. Further, a hard mask made of an inorganic film or a metal film may be used.

As the light used for forming the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet rays, KrF laser light, ArF laser light, or the like can also be used. Further, the exposure may be performed by the immersion exposure technique. Further, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-ray may be used. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays or an electron beam because extremely fine processing is possible. A photomask is not required when exposure is performed by scanning a beam such as an electron beam.

Further, before forming the resist film to be the resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed so as to cover the step of the lower layer and flatten the surface by, for example, a spin coating method, and the thickness of the resist mask provided on the upper layer of the organic resin film varies. Can be reduced. Further, particularly when performing fine processing, it is preferable to use a material that functions as an antireflection film against light used for exposure as the organic resin film. Examples of the organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed at the same time as the resist mask is removed, or may be removed after the resist mask is removed.

Next, the conductive film 302B and the barrier film 303A are formed on the conductive layer 302a. The conductive film 302B can be formed in the same manner as the conductive film 302A. Further, as the barrier film 303A, an insulating film such as a silicon oxide film or a gallium oxide film, or a semiconductor film such as an oxide semiconductor film can be used (FIG. 4 (C)).

The barrier film 303A can be formed by using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the barrier film 303A by a CVD method, preferably a plasma CVD method, because the coverage can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Then, the resist mask 320 is formed by the same method as described above, and unnecessary regions of the barrier film 303A and the conductive film 302B are removed by etching. Then, by removing the resist mask 320, the barrier layer 303 and the conductive layer 302b are formed (FIG. 4 (D)). By forming the conductive layer 302b, the first electrode 302 that serves as one electrode of the capacitive element 300 is formed.

Further, the barrier film 303A and the conductive film 302B may be etched separately. In that case, first, the barrier layer 303 may be formed by the resist mask 320, and then the conductive film 302B may be etched using the formed barrier layer 303 as a hard mask.

A barrier film may be formed on a sufficiently thick conductive film to process the first electrode 302 having a convex portion from the one-layer conductive film. A method such as half etching can also be used for processing. For example, as shown in FIGS. 5A and 5B, a resist mask 330 is formed on the barrier film 303A and the conductive film 302C formed with a sufficiently thick film, and processed to perform the barrier layer 303B and the conductivity. It forms the membrane 302c. Subsequently, as shown in FIGS. 5C and 5D, a resist mask 320 may be formed to process a part of the barrier layer 303B and the conductive film 302c. When the conductive film 302c is further processed, the processing time corresponding to the desired etching amount is calculated from the etching rate of the conductive film 302C, and the etching may be stopped halfway by a timer, or the conductive film 302c may be processed by timer etching. In this way, the first electrode 302 can be provided with a convex portion as shown in FIG. 5 (D).

Further, if an exposure method using an exposure mask provided with a semipermeable membrane, which is also called a halftone exposure method, is used, the first electrode 302 can be processed with one mask. Further, a photomask or reticle provided with an auxiliary pattern having a light intensity reducing function composed of a diffraction grating pattern may be applied to the lithography process for forming the first electrode 302.

Next, the insulator 304 is formed on the first electrode 302 and the barrier layer 303 by using the resist mask as before. The insulator 304 can be formed in the same manner as the insulating film 301 (Fig. 4 (E)).

A conductive film 305A is formed on the insulator 304 (Fig. 6 (A)). The conductive film 305A can be formed in the same manner as the conductive film 302A. Then, the resist mask 325 is formed by the same method as described above, and the second electrode 305 is formed by removing unnecessary regions of the conductive film 305A by etching. At this time, not only the conductive film 305A but also the surface of the insulator 304 is scraped off, and the film thickness of the region where the insulator 304 does not overlap with the second electrode 305 overlaps with the second electrode 305. It becomes thinner than the thickness. Further, exposure to plasma in the case of dry etching or a solvent used in the case of wet etching causes damage to the surface of the insulator 304. Therefore, in the absence of the barrier layer 303, a leak current is likely to occur around the side of the second electrode 305. Therefore, by providing the barrier layer 303, an appropriate distance is maintained between the first electrode 302 and the second electrode 305, so that a highly reliable capacitive element capable of high integration and miniaturization is possible. 300 can be formed (Fig. 6 (B)).

Subsequently, an insulating film 306 covering the capacitance element 300 is formed. The insulating film 306 can be formed by the same material and method as the insulating film 301 and the like (FIG. 6 (C)).

Further, the wiring 308 for electrically connecting the formed capacitance element 300 to another semiconductor element may be formed (FIG. 6 (D)). A conductive material such as a metal material, an alloy material, or a metal oxide material can be used for the wiring 308. In particular, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using the above materials.

By the above steps, the capacitive element of one aspect of the present invention can be manufactured. The configuration shown in FIG. 1 can be manufactured in the same manner.

In the present embodiment, one aspect of the present invention has been described. Alternatively, in another embodiment, one aspect of the present invention will be described. However, one aspect of the present invention is not limited to these. That is, since various aspects of the invention are described in this embodiment and other embodiments, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example in which a barrier layer is provided on the first electrode of the capacitive element has been shown, but one aspect of the present invention is not limited to this. In some cases, or depending on the circumstances, in one aspect of the invention, various layers may be provided on the first electrode of the capacitive element. Or, for example, in some cases, or depending on the circumstances, in one aspect of the invention, the barrier layer may not be provided on the first electrode of the capacitive element.

(Embodiment 2) [Configuration Example]

FIG. 7 shows an example of a semiconductor device (storage device) using a capacitive element which is one aspect of the present invention. Note that FIG. 7 (B) is a circuit diagram of FIG. 7 (A).

The semiconductor device shown in FIGS. 7 (A) and 7 (B) includes a first transistor 100, a second transistor 200, and a capacitive element 300. As the capacitive element 300, the capacitive element described in the first embodiment can be used.

The second transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the second transistor 200 has a small off current, it is possible to retain the stored contents for a long period of time by using it in a semiconductor device (storage device). That is, it is possible to use a semiconductor device (storage device) that does not require a refresh operation or has an extremely low frequency of refresh operations, so that power consumption can be sufficiently reduced.

In FIG. 7B, the wiring 3001 is electrically connected to the source electrode of the first transistor 100, and the wiring 3002 is electrically connected to the drain electrode of the first transistor 100. Further, the wiring 3003 is electrically connected to one of the source electrode and the drain electrode of the second transistor 200, and the wiring 3004 is electrically connected to the gate electrode of the second transistor 200. Then, the gate electrode of the first transistor 100 and the other of the source electrode and the drain electrode of the second transistor 200 are electrically connected to one of the electrodes of the capacitive element 300, and the wiring 3005 is the electrode of the capacitive element 300. It is electrically connected to the other.

Further, by arranging the semiconductor devices shown in FIG. 7A in a matrix, a storage device (memory cell array) can be configured.

The semiconductor device according to one aspect of the present invention has a capacitive element 300 in which the first electrode has a convex portion, so that the area can be reduced and the integration can be increased. Further, in the capacitive element 300, at least the distance between the electrodes in the region where the upper surface of the convex portion formed on the first electrode and the end portion of the second electrode overlap is the convex portion formed on the first electrode. Since it is provided longer than the distance between the electrodes on the side surface, a short circuit between the electrodes can be prevented.

As shown in FIG. 7A, the semiconductor device includes a first transistor 100, a second transistor 200, and a capacitive element 300. The second transistor 200 is provided above the first transistor 100, and a capacitive element 300 is provided between the first transistor 100 and the second transistor 200.

The first transistor 100 is provided on the semiconductor substrate 101, and includes a semiconductor film 102 composed of a part of the semiconductor substrate 101, a gate insulating film 104, a gate electrode 105, and a low resistance layer 103a that functions as a source region or a drain region. It has a low resistance layer 103b.

The first transistor 100 may be of either a p-channel type or an n-channel type, but an appropriate transistor may be used depending on the circuit configuration and the driving method.

It is preferable that a semiconductor such as a silicon-based semiconductor is contained in the region where the channel of the semiconductor film 102 is formed or its vicinity, the low resistance layer 103a and the low resistance layer 103b which are the source region or the drain region, and the like, and a single crystal. It preferably contains silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the first transistor 100 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

The low resistance layer 103a and the low resistance layer 103b impart n-type conductivity-imparting elements such as arsenic and phosphorus, or p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor film 102. Contains elements.

The gate electrode 105 is a semiconductor material such as silicon, a metal material, an alloy material, or metal oxidation containing an element that imparts n-type conductivity such as arsenic and phosphorus, or an element that imparts p-type conductivity such as boron. A conductive material such as a material material can be used. It is preferable to adjust the work function using a gate electrode in order to adjust the threshold voltage, and specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the gate electrode. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the gate electrode, and it is particularly preferable to use tungsten in terms of heat resistance.

Here, as the first transistor 100, a transistor as shown in FIG. 8 may be used. The cross section of the first transistor 100 in the channel length direction is shown on the left side of the alternate long and short dash line in FIG. 8, and the cross section in the channel width direction is shown on the right side of the alternate long and short dash line. In the first transistor 100 shown in FIG. 8, the semiconductor film 102 (a part of the semiconductor substrate 101) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor film 102 are provided so as to be covered by the gate electrode 105a and the gate electrode 105b via the gate insulating film 104. The gate electrode 105a may be made of a material that adjusts the work function. Since such a first transistor 100 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. In addition, an insulating film that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

The insulating film 121, the insulating film 122, and the insulating film 301 are laminated in this order so as to cover the first transistor 100.

The insulating film 121 functions as a flattening film that flattens the step generated by the first transistor 100 or the like provided under the insulating film 121. The upper surface of the insulating film 121 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, the insulating film 121, the insulating film 122, and the insulating film 301 are embedded with a capacitance element 300, a wiring 110 electrically connected to the second transistor 200, and the like. In the present specification and the like, the electrode and the wiring electrically connected to the electrode may be integrated. That is, a part of the wiring may function as an electrode, or a part of the electrode may function as a wiring.

As the material of each wiring (wiring 308, etc.), a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In particular, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using the above materials.

A first electrode 302 of the capacitive element 300 is provided on the upper portion of the insulating film 301 and the upper portion of the wiring 308. The first electrode 302 is electrically connected to the wiring 308.

The barrier layer 303 and the insulator 304 are provided on the first electrode 302 of the capacitance element 300, and the second electrode 305 of the capacitance element 300 is provided on the insulator 304.

Further, it is preferable that the capacitive element 300 is provided so as to be embedded in the insulating film 306, and the upper surface of the insulating film 306 is flattened.

An insulating film is formed on the insulating film 306. In this embodiment, two layers of the insulating film 201 and the insulating film 202 are formed, but it may be a single layer or a laminated layer of three or more layers.

For the insulating film 202, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating.

As the oxide material that desorbs oxygen by heating, it is preferable to use an oxide containing more oxygen than oxygen satisfying the stoichiometric composition. In an oxide film containing more oxygen than oxygen satisfying a stoichiometric composition, some oxygen is eliminated by heating. Oxide films containing more oxygen than oxygen satisfying the stoichiometric composition are desorbed from oxygen in terms of oxygen atoms by thermal desorption spectroscopy (TDS) analysis. Is 1.0 × 10¹⁸atoms / cm³Above, preferably 3.0 × 10²⁰atoms / cm³This is the oxide film described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C or more and 700 ° C or less, or 100 ° C or more and 500 ° C or less.

For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxide nitride. Alternatively, a metal oxide can be used. In the present specification, silicon oxide refers to a material whose composition has a higher oxygen content than nitrogen, and silicon nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.

A second transistor 200 is provided above the insulating film 202.

One of the electrodes 204a and 204b functions as a source electrode and the other functions as a drain electrode.

The electrode 204a and the electrode 204b use a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component as a single layer structure or a laminated structure. .. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, and a copper film on a copper-magnesium-aluminum alloy film. Two-layer structure for laminating, two-layer structure for laminating a copper film on a titanium film, two-layer structure for laminating a copper film on a tungsten film, a titanium film or a titanium nitride film, and the titanium film or the titanium nitride film. A three-layer structure, a molybdenum film or molybdenum nitride film, in which an aluminum film or copper film is laminated and a titanium film or titanium nitride film is formed on the aluminum film or copper film There is a three-layer structure in which a film is laminated and a molybdenum film or a molybdenum nitride film is further formed on the film. A transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

The gate insulating film 205 includes, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO).₃) Or (Ba, Sr) TiO₃Insulating films containing so-called high-k materials such as (BST) can be used in single layers or in layers. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulating films. Alternatively, these insulating films may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated on the above insulating film.

Further, as the gate insulating film 205, it is preferable to use an oxide insulating film containing more oxygen than oxygen satisfying the chemical quantitative composition as in the insulating film 202.

When a specific material is used for the gate insulating film, electrons can be captured by the gate insulating film under specific conditions to increase the threshold voltage. For example, a material with a high electron capture level such as hafnium oxide, aluminum oxide, and tantalum oxide is used for a part of the gate insulating film, such as a laminated film of silicon oxide and hafnium oxide, and a higher temperature (use of a semiconductor device) is used. The potential of the gate electrode is higher than the potential of the source electrode and drain electrode under a temperature higher than the temperature or storage temperature, or 125 ° C or higher and 450 ° C or lower, typically 150 ° C or higher and 300 ° C or lower). By maintaining the high state for 10 milliseconds or more, typically 1 minute or more, electrons move from the semiconductor film toward the gate electrode, and some of them are captured at the electron capture level.

In the transistor in which the required amount of electrons is captured in the electron capture level in this way, the threshold voltage shifts to the positive side. By controlling the voltage of the gate electrode, the amount of electrons captured can be controlled, and the threshold voltage can be controlled accordingly. Further, the process of capturing electrons may be performed in the process of manufacturing the transistor.

For example, it is performed at any stage before the factory shipment, such as after forming the wiring to be connected to the source electrode or drain electrode of the transistor, after the completion of the previous process (wafer processing), after the wafer dicing process, after packaging, and the like. It is good. In either case, it is preferable not to be subsequently exposed to temperatures above 125 ° C for more than 1 hour.

The gate electrode 206 having the conductor 206a and the conductor 206b is a metal selected from, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-mentioned metal as a component, or a combination of the above-mentioned metals. It can be formed by using a metal alloy or the like. Further, a metal selected from any one or more of manganese and zirconium may be used. Further, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, and a silicide such as nickel silicide may be used. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film or a tungsten nitride film. There are a two-layer structure in which a tungsten film is laminated on top, a titanium film, and a three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed on the titanium film. Further, an alloy film or a nitride film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum may be used.

Further, the gate electrode 206 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. , A translucent conductive material such as indium tin oxide to which silicon oxide is added can also be applied. Further, the conductive material having the translucent property and the metal may be laminated.

Here, a configuration example of a transistor applicable to the second transistor 200 will be described. FIG. 9 (A) is a schematic top view of the transistor illustrated below, and FIGS. 9 (B) and 9 (C) are cut along the cutting lines A1-A2 and B1-B2 in FIG. 9 (A), respectively. It is a cross-sectional schematic diagram at the time of. Note that FIG. 9B corresponds to a cross section in the channel length direction of the transistor, and FIG. 9C corresponds to a cross section in the channel width direction of the transistor.

As shown in FIG. 9C, in the cross section in the channel width direction of the transistor, the gate electrode 206 is provided facing the upper surface and the side surface of the oxide semiconductor layer 203b, so that only the vicinity of the upper surface of the oxide semiconductor layer 203b is provided. Instead, a channel is formed near the side surface, the effective channel width is increased, and the current in the on state (on current) can be increased. In particular, when the width of the oxide semiconductor layer 203b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably 20 nm or less), the region where channels are formed extends to the inside of the oxide semiconductor layer 203b. The smaller the size, the greater the contribution to the on-current.

As shown in FIGS. 10 (A), 10 (B), and 10 (C), the width of the gate electrode 206 may be narrowed. In that case, for example, impurities such as argon, hydrogen, phosphorus, and boron can be introduced into the oxide semiconductor layer 203b and the like using the electrodes 204a and 204b and the gate electrode 206 as masks. As a result, the low resistance region 209a and the low resistance region 209b can be provided in the oxide semiconductor layer 203b and the like. The low resistance region 209a and the low resistance region 209b do not necessarily have to be provided. The width of the gate electrode 206 can be narrowed not only in FIG. 9 but also in other drawings.

The transistors shown in FIGS. 11 (A) and 11 (B) are mainly provided in that the oxide semiconductor layer 203c is provided in contact with the lower surfaces of the electrodes 204a and 204b, as compared with the transistors illustrated in FIG. Is different.

With such a configuration, when the films constituting the oxide semiconductor layer 203a, the oxide semiconductor layer 203b, and the oxide semiconductor layer 203c are formed, they are continuously formed without being exposed to the atmosphere. Therefore, each interface defect can be reduced.

Further, in the above description, the configuration in which the oxide semiconductor layer 203a and the oxide semiconductor layer 203c are provided in contact with the oxide semiconductor layer 203b has been described, but one or both of the oxide semiconductor layer 203a and the oxide semiconductor layer 203c may be provided. It may be configured not to be provided.

In FIG. 11, the width of the gate electrode 206 can be narrowed as in FIG. Examples of this case are shown in FIGS. 12 (A) and 12 (B). The width of the gate electrode 206 can be narrowed not only in FIGS. 9 and 11 but also in other drawings.

The channel length is, for example, in the top view of the transistor, in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap, or in the region where the channel is formed. , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, the region where the semiconductor (or the part where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap, or the region where the channel is formed, where the source and drain face each other. The length of the part that is present. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). ) And may be different. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap, is referred to as enclosure channel width (SCW). : Surrounded Channel Width) ". Further, in the present specification, when simply described as a channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by acquiring a cross-sectional TEM image and analyzing the image. it can.

When calculating the electric field effect mobility of a transistor, the current value per channel width, or the like, the enclosed channel width may be used for calculation. In that case, the value may be different from that calculated using the effective channel width.

The above is the description of the second transistor 200.

The insulating film 207 and the insulating film 208 that cover the second transistor 200 may function as a barrier film or a flattening film that covers the uneven shape of the lower layer thereof.

The above is the description of the configuration example.

[Example of manufacturing method]

Hereinafter, an example of the method for manufacturing the semiconductor device shown in the above configuration example will be described with reference to FIGS. 13 to 15.

First, the semiconductor substrate 101 is prepared. As the semiconductor substrate 101, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. Moreover, you may use the SOI substrate as the semiconductor substrate 101. Hereinafter, a case where single crystal silicon is used as the semiconductor substrate 101 will be described.

Subsequently, an element separation layer is formed on the semiconductor substrate 101. The device separation layer may be formed by using a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

When forming a p-type transistor and an n-type transistor on the same substrate, n-wells or p-wells may be formed in a part of the semiconductor substrate 101. For example, even if an impurity element such as boron that imparts p-type conductivity is added to an n-type semiconductor substrate 101 to form a p-well, and an n-type transistor and a p-type transistor are formed on the same substrate. Good.

Subsequently, an insulating film to be the gate insulating film 104 is formed on the semiconductor substrate 101. For example, the surface nitriding treatment may be followed by an oxidation treatment to oxidize the silicon-silicon nitride interface to form a silicon oxide nitride film. For example NH₃A silicon oxide film is obtained by forming a hot silicon nitride film on the surface at 700 ° C in an atmosphere and then performing oxygen radical oxidation.

The insulating film includes sputtering method, CVD (Chemical Vapor Deposition) method (including thermal CVD method, MOCVD (Metal Organic CVD) method, PECVD (Plasma Enhanced CVD) method, etc.), MBE (Molecular Beam Epitaxy) method, ALD ( It may be formed by forming a film by an Atomic Layer Deposition) method, a PLD (Pulsed Laser Deposition) method, or the like.

Subsequently, a conductive film to be the gate electrode 105 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium and the like, or an alloy material or compound material containing these metals as a main component. Further, polycrystalline silicon to which impurities such as phosphorus are added can be used. Moreover, you may use the laminated structure of the metal nitride film and the said metal film. As the metal nitride, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented. Further, a metal film for controlling the work function of the gate electrode 105 may be provided.

The conductive film can be formed by a sputtering method, a vapor deposition method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.) and the like. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Subsequently, a resist mask is formed on the conductive film by a lithography method or the like, and an unnecessary portion of the conductive film is removed. After that, the gate electrode 105 can be formed by removing the resist mask.

Here, a method for processing the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a lithography method or the like may be used. Further, a dummy pattern may be formed by a lithography method or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the remaining sidewall may be used as a resist mask to etch the film to be processed. Further, as the etching of the film to be processed, it is preferable to use anisotropic dry etching in order to realize a high aspect ratio. Further, a hard mask made of an inorganic film or a metal film may be used.

As the light used for forming the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet rays, KrF laser light, ArF laser light, or the like can also be used. Further, the exposure may be performed by the immersion exposure technique. Further, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-ray may be used. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays or an electron beam because extremely fine processing is possible. A photomask is not required when exposure is performed by scanning a beam such as an electron beam.

Further, before forming the resist film to be the resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed so as to cover the step of the lower layer and flatten the surface by, for example, a spin coating method, and the thickness of the resist mask provided on the upper layer of the organic resin film varies. Can be reduced. Further, particularly when performing fine processing, it is preferable to use a material that functions as an antireflection film against light used for exposure as the organic resin film. Examples of the organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed at the same time as the resist mask is removed, or may be removed after the resist mask is removed.

After forming the gate electrode 105, a sidewall covering the side surface of the gate electrode 105 may be formed. The sidewall can be formed by forming an insulating film thicker than the thickness of the gate electrode 105 and then performing anisotropic etching to leave the insulating film only on the side surface portion of the gate electrode 105.

When the sidewall is formed, the insulating film that becomes the gate insulating film 104 is also etched at the same time, so that the gate electrode 105 and the gate insulating film 104 are formed under the sidewall. Alternatively, the gate insulating film 104 may be formed by etching the insulating film using a resist mask for processing the gate electrode 105 or the gate electrode 105 as an etching mask after forming the gate electrode 105. Alternatively, the insulating film can be used as it is as the gate insulating film 104 without being processed by etching.

Subsequently, an element that imparts n-type conductivity such as phosphorus or an element that imparts p-type conductivity such as boron is added to the region of the semiconductor substrate 101 where the gate electrode 105 (and sidewall) is not provided. To do. The schematic cross-sectional view at this stage corresponds to FIG. 13 (A).

Subsequently, after the insulating film 121 is formed, the first heat treatment for activating the above-mentioned element that imparts conductivity is performed.

The insulating film 121 may be made of, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, or the like, and is provided in a laminated or single layer. Further, it is preferable to use silicon nitride (SiNOH) containing oxygen and hydrogen because the amount of hydrogen desorbed by heating can be increased. Further, silicon oxide having good step coating property formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen or nitrous oxide can also be used.

The insulating film 121 can be formed by using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

The first heat treatment can be carried out in an atmosphere of an inert gas such as a rare gas or nitrogen gas, or in a reduced pressure atmosphere, for example, at 400 ° C. or higher and below the strain point of the substrate.

At this stage, the first transistor 100 is formed.

Subsequently, the upper surface of the insulating film 121 is flattened by using the CMP method or the like.

Subsequently, an opening is formed in the insulating film 121 to reach the low resistance layer 103a, the low resistance layer 103b, the gate electrode 105, and the like. After that, a conductive film is formed so as to fill the opening, and the conductive film is flattened so that the upper surface of the insulating film 121 is exposed to form wiring 111a, wiring 111b, wiring 110, and the like. The conductive film can be formed by using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like.

Subsequently, a conductive film is formed on the insulating film 121. After that, a resist mask is formed by the same method as described above, and an unnecessary portion of the conductive film is removed by etching. After that, the resist mask is removed to form the wiring, and then the insulating film 122 is further formed, and the embedded wiring is formed by flattening the wiring by using the CMP method or the like until the upper surface of the wiring can be seen. Further, it may be formed by using the damascene method. The insulating film 122 can be made of the same material and method as the insulating film 121.

Next, after forming the insulating film 301, a contact hole is formed in the insulating film 301 to reach the wiring connected to the wiring 110, and the wiring 308 is formed by the same material and method as the wiring 110. The schematic cross-sectional view at this stage corresponds to FIG. 13 (B).

Subsequently, the capacitance element 300 is formed so as to be connected to the wiring 308. The creation method is shown in the example of the creation method of the first embodiment. A schematic cross-sectional view at the stage of forming the capacitive element 300 corresponds to FIG. 13 (C).

Subsequently, an insulating film to be an insulating film 306 covering the capacitance element 300 is formed. The insulating film to be the insulating film 306 can be formed by the same material and method as the insulating film 121 and the like.

Further, after forming the insulating film to be the insulating film 306, the insulating film 306 is formed by performing a flattening treatment using a CMP method or the like in order to improve the flatness of the upper surface thereof.

Subsequently, an insulating film to be the insulating film 201 and the insulating film 202 is formed. The insulating film 201 and the insulating film 202 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. it can. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Further, in order to excessively contain oxygen in the insulating film to be the insulating film 202, for example, the insulating film to be the insulating film 202 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film to be the insulating film 202 after the film formation to form a region containing an excess of oxygen, or both means may be combined.

For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film to be the insulating film 202 after film formation to form a region containing an excess of oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction treatment, a rare gas may be contained in the gas containing oxygen, and for example, a mixed gas of carbon dioxide, hydrogen and argon can be used.

Further, after forming the insulating film to be the insulating film 202, the insulating film 202 may be formed by performing a flattening treatment using a CMP method or the like in order to improve the flatness of the upper surface thereof.

Subsequently, an oxide semiconductor film to be the oxide semiconductor layer 203a and an oxide semiconductor film to be the oxide semiconductor layer 203b are formed in this order. It is preferable that the oxide semiconductor film is continuously formed without being exposed to the atmosphere.

It is preferable to perform heat treatment after forming the oxide semiconductor film to be the oxide semiconductor layer 203b. The heat treatment may be carried out at a temperature of 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, in an atmosphere of an inert gas, an atmosphere containing 10 ppm or more of an oxidizing gas, or a reduced pressure state. Further, the heat treatment atmosphere may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after the oxide semiconductor film to be the oxide semiconductor layer 203b is formed, or the oxide semiconductor film to be the oxide semiconductor layer 203b is processed to form an island-shaped oxide semiconductor layer 203b. It may be done after forming. By the heat treatment, oxygen is supplied from the insulating film 202 to the oxide semiconductor layer, and oxygen deficiency in the oxide semiconductor layer can be reduced.

Then, a conductive film to be a hard mask and a resist mask are formed on the oxide semiconductor film to be the oxide semiconductor layer 203b by the same method as described above, and unnecessary portions of the conductive film are removed by etching. Then, the unnecessary portion of the oxide semiconductor film is removed by etching using the conductive film as a mask. After that, by removing the resist mask, a laminated structure of the island-shaped oxide semiconductor layer 203a and the island-shaped oxide semiconductor layer 203b can be formed. The conductive film serving as a hard mask may be used as a part of the electrodes 204a and 204b to be formed later.

Next, a resist mask is formed on the insulating film 202, the island-shaped oxide semiconductor layer 203a, and the island-shaped oxide semiconductor layer 203b, and the insulating film 202, the insulating film 201, the insulating film 306, the insulator 304, and the barrier are formed. A contact hole 310 is formed through the layer 303 (see FIG. 14 (A)).

Subsequently, a conductive film is formed. The conductive film can be formed by using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the conductive film by a CVD method, preferably a plasma CVD method, because the coating property can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Next, a resist mask is formed on the conductive film by the same method as described above, and an unnecessary portion of the conductive film is removed by etching. After that, by removing the resist mask, the wiring 307 that connects the electrodes 204a, 204b, and the electrodes 204a and the first electrode 302 of the capacitive element 300 via the contact hole 310 can be formed at the same time.

Subsequently, an oxide semiconductor film to be the oxide semiconductor layer 203c and an insulating film are formed in this order. A resist mask is formed on the insulating film by the same method as described above, and unnecessary portions of the insulating film and the oxide semiconductor film are removed by etching. After that, the resist mask is removed to form the oxide semiconductor layer 203c and the gate insulating film 205.

Subsequently, a conductive film is formed to form a conductor 206a and a gate electrode 206 having the conductor 206b.

At this stage, the second transistor 200 is formed.

Subsequently, the insulating film 207 and, if necessary, the insulating film 208 are formed. The insulating film 207 and the insulating film 208 can be formed by using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable (see FIG. 14 (B)).

Through the above steps, the semiconductor device according to one aspect of the present invention can be manufactured.

&lt;Modification Example 1&gt; Further, as a modification of the present embodiment, as shown in FIG. 15, the position of the capacitance element 300 may be provided above the second transistor 200. Specifically, the capacitance element 300 may be formed after the second transistor 200 is formed on the first transistor 100. The first transistor 100 and the second transistor 200 are connected via the wiring 250. Further, a contact hole is formed in the interlayer insulating film so as to reach the extending wiring of the electrode 204b of the second transistor 200. Then, by forming the wiring 350 in the contact hole, the capacitance element 300, the first transistor 100, and the second transistor 200 may be electrically connected.

&lt;Modification 2&gt; Further, as shown in FIGS. 16A and 16B, one of the source electrode or the drain electrode of the second transistor 200 and the first electrode of the capacitive element 300 are the same. It may be configured to be provided by the conductive layer of. Therefore, the electrode 204b shown in the figure has a function as one of the source electrode or the drain electrode of the second transistor 200 and the first electrode of the capacitive element 300.

FIG. 16A will be specifically described. The conductive film to be the electrode 204b is formed to be sufficiently thick. A resist mask is formed by the same method as described above, and an unnecessary portion of the conductive film is removed. Next, after removing the resist mask, an oxide semiconductor film to be the oxide semiconductor layer 203c and the barrier layer 303 is formed. A resist mask is formed in the same manner as described above, and unnecessary portions of the oxide semiconductor film are removed. By removing the resist mask, the oxide semiconductor layer 203c and the barrier layer 303 are formed.

Next, using the oxide semiconductor layer 203c and the barrier layer 303 as masks, the conductive film to be the electrode 204b is half-etched to the extent that it does not reach the insulating film 202, thereby causing one of the source electrode and the drain electrode of the second transistor 200. , And the electrode 204b, which functions as the first electrode of the capacitive element 300, can be formed.

Subsequently, the insulator 304 (gate insulating film 205) is formed. By forming a conductive film on the insulator 304, forming a resist mask in the same manner as described above, and removing unnecessary portions of the conductive film, the second transistor 200 and the capacitive element 300 can be formed at the same time.

FIG. 16B will be specifically described. It forms an electrode 204b that functions as one of the source or drain electrodes of the second transistor 200 and as part of the first electrode of the capacitive element 300. Subsequently, after forming the conductive layer 302b and the barrier layer 303 which are the convex portions of the first electrode of the capacitive element 300, the oxide semiconductor film which becomes the oxide semiconductor layer 203c and the intermediate layer 340, the insulator 304 and An insulating film to be the gate insulating film 205, a second electrode 305 having the conductor 305a and the conductor 305b, and a conductive film to be the gate electrode 206 having the conductor 206a and the conductor 206b are formed. By forming the resist mask in the same manner as described above and removing unnecessary portions of the oxide semiconductor film, the insulating film, and the conductive film, the second transistor 200 and the capacitive element 300 can be formed at the same time.

By using the structure of FIG. 16A or FIG. 16B, it is possible to provide a semiconductor device suitable for miniaturization and high density without reducing or increasing the number of steps and the number of masks.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 3) In the present embodiment, an oxide semiconductor that can be suitably used for the semiconductor film of the semiconductor device of one aspect of the present invention will be described.

&lt;Structure of Oxide Semiconductor&gt; The structure of the oxide semiconductor will be described below.

Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Non-single crystal oxide semiconductors include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline Oxide Semiconductor), and pseudo-amorphous oxide semiconductor (a-like OS: amorphous). like Oxide Semiconductor), amorphous oxide semiconductors, etc.

From another viewpoint, oxide semiconductors are divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

As a definition of an amorphous structure, it is generally known that it is not immobilized in a metastable state, and that it is isotropic and does not have an inhomogeneous structure. In addition, it can be rephrased as a structure in which the coupling angle is flexible and short-range order is provided, but long-range order is not provided.

On the contrary, an essentially stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has a void (also referred to as a void) and has an unstable structure. Therefore, it can be said that the physical characteristics are close to those of an amorphous oxide semiconductor.

&lt;CAAC-OS&gt; First, CAAC-OS will be explained.

CAAC-OS is one of oxide semiconductors having a plurality of c-axis oriented crystal portions.

When observing a composite analysis image (also called a high-resolution TEM image) of a bright-field image of CAAC-OS and a diffraction pattern with a transmission electron microscope (TEM), multiple crystal parts can be confirmed. it can. On the other hand, in a high-resolution TEM image, the boundary between crystal portions, that is, the grain boundary (also referred to as grain boundary) cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries.

The CAAC-OS observed by TEM will be described below. Figure 17 (A) shows a high-resolution TEM image of the cross section of CAAC-OS observed from a direction substantially parallel to the sample surface. The spherical aberration correction (Spherical Aberration Corrector) function was used to observe the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be acquired by, for example, the atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

A Cs-corrected high-resolution TEM image obtained by enlarging the area (1) of FIG. 17 (A) is shown in FIG. 17 (B). From FIG. 17 (B), it can be confirmed that the metal atoms are arranged in layers in the crystal portion. The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film, and is parallel to the surface to be formed or the upper surface of CAAC-OS.

As shown in FIG. 17 (B), CAAC-OS has a characteristic atomic arrangement. FIG. 17 (C) shows the characteristic atomic arrangement with auxiliary lines. From FIGS. 17 (B) and 17 (C), the size of one crystal portion is about 1 nm or more and 3 nm or less, and the size of the gap generated by the inclination between the crystal portions is about 0.8 nm. Understand. Therefore, the crystal part can also be called a nanocrystal (nc: nanocrystal). CAAC-OS can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals).

Here, if the arrangement of the crystal part 5100 of CAAC-OS on the substrate 5120 is schematically shown based on the Cs-corrected high-resolution TEM image, the structure is as if bricks or blocks were stacked (Fig. 17 (D). )reference.). The portion where the inclination occurs between the crystal portion observed in FIG. 17 (C) corresponds to the region 5161 shown in FIG. 17 (D).

In addition, Fig. 18 (A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. Cs-corrected high-resolution TEM images obtained by enlarging the region (1), region (2), and region (3) of FIG. 18 (A) are shown in FIGS. 18 (B), 18 (C), and 18 (D), respectively. Shown. From FIGS. 18 (B), 18 (C) and 18 (D), it can be confirmed that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape in the crystal portion. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

Next, CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, InGaZnO₄When the structural analysis by the out-of-plane method is performed on CAAC-OS having crystals of, a peak may appear in the diffraction angle (2θ) near 31 ° as shown in FIG. 19 (A). This peak is InGaZnO₄Since it is attributed to the (009) plane of the crystal, it can be confirmed that the CAAC-OS crystal has c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface.

In the structural analysis by the out-of-plane method of CAAC-OS, in addition to the peak near 31 ° in 2θ, the peak may appear near 36 ° in 2θ. The peak with 2θ near 36 ° indicates that some crystals in CAAC-OS do not have c-axis orientation. For more preferable CAAC-OS, 2θ shows a peak near 31 ° and 2θ does not show a peak near 36 ° in the structural analysis by the out-of-plane method.

On the other hand, when structural analysis is performed by the in-plane method in which X-rays are incident on CAAC-OS from a direction substantially perpendicular to the c-axis, a peak appears at 2θ near 56 °. This peak is InGaZnO₄It is attributed to the (110) plane of the crystal. In the case of CAAC-OS, even if 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Fig. 19 (B) shows. No clear peaks appear as shown. On the other hand, InGaZnO₄In the case of the single crystal oxide semiconductor of, when 2θ is fixed near 56 ° and φ scan is performed, as shown in Fig. 19 (C), there are 6 peaks attributed to the crystal plane equivalent to the (110) plane. Observed. Therefore, structural analysis using XRD confirms that CAAC-OS has irregular orientations on the a-axis and b-axis.

Next, CAAC-OS analyzed by electron diffraction will be described. For example, InGaZnO₄When an electron beam having a probe diameter of 300 nm is incident on CAAC-OS having the above crystals in parallel with the sample surface, a diffraction pattern (also referred to as a limited field transmission electron diffraction pattern) as shown in FIG. 20 (A) is obtained. May appear. InGaZnO is used for this diffraction pattern.₄Includes spots due to the (009) plane of the crystal. Therefore, it can be seen from the electron diffraction that the crystal portion contained in CAAC-OS has c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. On the other hand, FIG. 20 (B) shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. 20 (B). Therefore, it can be seen that the a-axis and b-axis of the crystal portion contained in CAAC-OS do not have orientation even by electron diffraction. The first ring in Fig. 20 (B) is InGaZnO.₄It is considered that this is due to the (010) plane and the (100) plane of the crystal of. Further, it is considered that the second ring in FIG. 20 (B) is caused by the surface (110) and the like.

As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of an oxide semiconductor may decrease due to the inclusion of impurities or the formation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (oxygen deficiency, etc.) from the opposite perspective.

Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than the metal element constituting the oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen and lowers the crystallinity. It becomes a factor. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may fluctuate due to light, heat, or the like. For example, impurities contained in an oxide semiconductor may serve as a carrier trap or a carrier generation source. In addition, oxygen deficiency in the oxide semiconductor may become a carrier trap, or may become a carrier generation source by capturing hydrogen.

CAAC-OS, which has few impurities and oxygen deficiency, is an oxide semiconductor with a low carrier density. Specifically, the carrier density is 8 × 10.¹¹/cm³Less than, preferably 1x10¹¹/cm³Less than, more preferably 1x10¹⁰/cm³Less than 1x10^-9/cm³It can be the above. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

&lt;nc-OS&gt; Next, nc-OS will be described.

The nc-OS has a region in which a crystal portion can be confirmed and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal part contained in nc-OS is often 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less in size. An oxide semiconductor having a crystal portion larger than 10 nm and 100 nm or less may be referred to as a microcrystalline oxide semiconductor. In nc-OS, for example, in a high-resolution TEM image, the grain boundaries may not be clearly confirmed. Nanocrystals may have the same origin as the crystal part in CAAC-OS.

nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different crystal parts. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors depending on the analysis method. For example, when X-rays having a diameter larger than that of the crystal part are used for nc-OS, the peak indicating the crystal plane is not detected by the analysis by the out-of-plane method. Further, when electron diffraction is performed on nc-OS using an electron beam having a probe diameter larger than that of the crystal portion (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, spots are observed when nanobeam electron diffraction is performed on nc-OS using an electron beam having a probe diameter close to the size of the crystal portion or smaller than the crystal portion. In addition, when nanobeam electron diffraction is performed on nc-OS, a region with high brightness (ring-shaped) may be observed in a circular motion. Furthermore, a plurality of spots may be observed in the ring-shaped region.

In this way, since the crystal orientation does not have regularity between the crystal parts (nanocrystals), nc-OS is used as an oxide semiconductor having RANC (Random Aligned nanocrystals), or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor having.

nc-OS is an oxide semiconductor with higher regularity than the amorphous oxide semiconductor. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in crystal orientation between different crystal parts. Therefore, nc-OS has a higher defect level density than CAAC-OS.

&lt;a-like OS&gt; a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

In a-like OS, voids may be observed in high-resolution TEM images. Further, in the high-resolution TEM image, it has a region where the crystal portion can be clearly confirmed and a region where the crystal portion cannot be confirmed.

The a-like OS has an unstable structure because it has voids. In the following, we show that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, so we show the structural changes due to electron irradiation.

Prepare a-like OS (denoted as sample A), nc-OS (denoted as sample B) and CAAC-OS (denoted as sample C) as samples to be subjected to electron irradiation. Both samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, it can be seen that each sample has a crystal part.

It should be noted that the determination as to which portion is regarded as one crystal portion may be performed as follows. For example, InGaZnO₄It is known that the unit cell of the crystal of is having a structure in which a total of 9 layers are layered in the c-axis direction, which has 3 layers of In-O and 6 layers of Ga-Zn-O. .. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, InGaZnO is located where the spacing between the plaids is 0.28 nm or more and 0.30 nm or less.₄It can be regarded as the crystal part of. The plaid is InGaZnO.₄Corresponds to the ab plane of the crystal.

FIG. 21 is an example of investigating the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 21, it can be seen that in the a-like OS, the crystal portion becomes larger according to the cumulative irradiation amount of electrons. Specifically, as shown in (1) in Fig. 21, the cumulative irradiation dose of the crystal part (also called the initial nucleus), which was about 1.2 nm at the initial stage of TEM observation, is 4.2 × 10.⁸e^-/ nm²It can be seen that the size of the plant has grown to about 2.6 nm. On the other hand, nc-OS and CAAC-OS have a cumulative electron irradiation dose of 4.2 x 10 from the start of electron irradiation.⁸e^-/ nm²It can be seen that there is no change in the size of the crystal part in the range up to. Specifically, as shown in (2) and (3) in FIG. 21, the size of the crystal part of nc-OS and CAAC-OS is about 1.4 nm, respectively, regardless of the cumulative irradiation amount of electrons. It can be seen that it is about 2.1 nm.

As described above, in a-like OS, the growth of the crystal part may be observed by electron irradiation. On the other hand, it can be seen that in nc-OS and CAAC-OS, almost no growth of the crystal part due to electron irradiation is observed. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

In addition, because it has voids, a-like OS has a structure with a lower density than nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of single crystals having the same composition. The density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of single crystals having the same composition. It is difficult to form an oxide semiconductor having a density of less than 78% of a single crystal.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], a single crystal InGaZnO having a rhombohedral structure.₄Density is 6.357g / cm³Will be. Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm.³More than 5.9g / cm³Will be less than. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm.³More than 6.3g / cm³Will be less than.

In some cases, single crystals having the same composition do not exist. In that case, the density corresponding to the single crystal in the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, the density is preferably estimated by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, and each has various characteristics. The oxide semiconductor may be, for example, a laminated film having two or more of amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

(Embodiment 4) In the present embodiment, an example of the configuration of a semiconductor device using the transistor of one aspect of the present invention will be described with reference to the drawings.

[Cross-sectional structure]

FIG. 22 (A) shows a cross-sectional view of the semiconductor device according to one aspect of the present invention. The semiconductor device shown in FIG. 22 (A) has a transistor 2200 using the first semiconductor material at the lower part and a transistor 2100 using the second semiconductor material at the upper part. The left side of the alternate long and short dash line is the cross section of the transistor in the channel length direction, and the right side is the cross section in the channel width direction.

The transistor 2100 may be provided with a back gate.

It is preferable that the first semiconductor material and the second semiconductor material have different energy gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphorus, gallium arsenide, organic semiconductor, etc.). The second semiconductor material can be an oxide semiconductor. Transistors using single crystal silicon or the like as a material other than oxide semiconductors are easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor has a low off-current.

The transistor 2200 may be either an n-channel type transistor or a p-channel type transistor, and an appropriate transistor may be used depending on the circuit. In addition to using the transistor of one aspect of the present invention using an oxide semiconductor, it is not necessary to limit the specific configuration of the semiconductor device to those shown here, such as the material and structure used.

In the configuration shown in FIG. 22 (A), the transistor 2100 is provided above the transistor 2200 via the insulating film 2201 and the insulating film 2207. Further, a plurality of wirings 2202 are provided between the transistor 2200 and the transistor 2100. In addition, the wiring and electrodes provided in the upper layer and the lower layer are electrically connected by a plurality of plugs 2203 embedded in various insulating films. Further, an interlayer insulating film 2204 is provided to cover the transistor 2100.

By stacking the two types of transistors in this way, the occupied area of the circuit can be reduced, and a plurality of circuits can be arranged at a higher density.

Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, hydrogen in the insulating film provided in the vicinity of the semiconductor film of the transistor 2200 terminates the dangling bond of silicon, and the reliability of the transistor 2200 is improved. It has the effect of improving. On the other hand, when an oxide semiconductor is used for the transistor 2100 provided in the upper layer, hydrogen in the insulating film provided in the vicinity of the semiconductor film of the transistor 2100 becomes one of the factors for generating carriers in the oxide semiconductor. It may cause a decrease in the reliability of the transistor 2100. Therefore, when the transistor 2100 using the oxide semiconductor is laminated on the upper layer of the transistor 2200 using the silicon-based semiconductor material, it is particularly important to provide the insulating film 2207 having a function of preventing the diffusion of hydrogen between them. It is effective. The insulating film 2207 improves the reliability of the transistor 2200 by confining hydrogen in the lower layer, and also improves the reliability of the transistor 2100 by suppressing the diffusion of hydrogen from the lower layer to the upper layer. it can.

As the insulating film 2207, for example, aluminum oxide, aluminum nitride, gallium oxide, gallium nitride oxide, yttrium oxide, yttrium nitride, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.

Further, a block film having a function of preventing hydrogen from being mixed may be formed on the transistor 2100 so as to cover the transistor 2100 including the oxide semiconductor film. As the blocking film, the same material as the insulating film 2207 can be used, and it is particularly preferable to apply aluminum oxide. The aluminum oxide film has a high blocking effect that does not allow the film to permeate both impurities such as hydrogen and water and oxygen. Therefore, by using an aluminum oxide film as a block film covering the transistor 2100, it is possible to prevent oxygen from being desorbed from the oxide semiconductor film contained in the transistor 2100 and to prevent water and hydrogen from being mixed into the oxide semiconductor film. can do.

The transistor 2200 can be not only a planar type transistor but also various types of transistors. For example, it can be a FIN type transistor, a TRI-GATE type transistor, or the like. An example of a cross-sectional view in that case is shown in FIG. 22 (D). An insulating film 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a convex portion (also referred to as a fin) having a thin tip. An insulating film may be provided on the convex portion. The insulating film functions as a mask for preventing the semiconductor substrate 2211 from being etched when the convex portion is formed. The convex portion does not have to have a thin tip. For example, the convex portion may be a substantially rectangular parallelepiped convex portion or a convex portion having a thick tip. A gate insulating film 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided on the gate insulating film 2214. In the present embodiment, the gate electrode 2213 has a one-layer structure, but the present invention is not limited to this, and two or more layers may be laminated. A source region and a drain region 2215 are formed on the semiconductor substrate 2211. Although the example in which the semiconductor substrate 2211 has a convex portion is shown here, the semiconductor device according to one aspect of the present invention is not limited to this. For example, the SOI substrate may be processed to form a semiconductor region having a convex portion.

[Circuit configuration example]

In the above configuration, various circuits can be configured by differently connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device of one aspect of the present invention will be described.

The circuit diagram shown in FIG. 22B shows the configuration of a so-called CMOS circuit in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their respective gates are connected.

Further, the circuit diagram shown in FIG. 22C shows a configuration in which the sources and drains of the transistors 2100 and 2200 are connected. With such a configuration, it can function as a so-called analog switch.

FIG. 23 shows a cross-sectional view of a semiconductor device in the case where a CMOS circuit is composed of transistors 2200 and transistors 2300 having the first semiconductor material as a channel.

The transistor 2300 has an impurity region 2301 that functions as a source region or a drain region, a gate electrode 2303, a gate insulating film 2304, and a side wall insulating film 2305. Further, the transistor 2300 may be provided with an impurity region 2302 that functions as an LDD region under the side wall insulating film 2305. For the other components of FIG. 23, the description of FIG. 22 (A) may be incorporated.

It is preferable that the transistor 2200 and the transistor 2300 are transistors having different polarities from each other. For example, when the transistor 2200 is a p-channel type transistor, the transistor 2300 is preferably an n-channel type transistor.

Further, the semiconductor device shown in FIGS. 22 (A) and 23 may be provided with a photoelectric conversion element such as a photodiode.

The photodiode may be formed by using a single crystal semiconductor or a polycrystalline semiconductor. A photodiode using a single crystal semiconductor or a polycrystalline semiconductor is preferable because it has high light detection sensitivity.

FIG. 24A shows a cross-sectional view when the photodiode 2400 is provided on the substrate 2001. The photodiode 2400 is a conductive film that electrically connects a conductive film 2401 having a function as one of an anode and a cathode, a conductive film 2402 having a function as one of an anode and a cathode, and a conductive film 2402 and a plug 2004. It has 2403 and. The conductive film 2401 to the conductive film 2403 may be produced by injecting impurities into the substrate 2001.

In FIG. 24 (A), the photodiode 2400 is provided so that the current flows in the vertical direction with respect to the substrate 2001, but the photodiode 2400 may be provided so that the current flows in the horizontal direction with respect to the substrate 2001. ..

FIG. 24B is a cross-sectional view of a semiconductor device in the case where the photodiode 2500 is provided on the upper layer of the transistor 2100. The photodiode 2500 has a conductive film 2501 having a function as one of an anode and a cathode, a conductive film 2502 having a function as one of an anode and a cathode, and a semiconductor layer 2503. Further, the photodiode 2500 is electrically connected to the transistor 2100 via a plug 2504.

In FIG. 24B, the photodiode 2500 may be provided in the same layer as the transistor 2100. Further, the photodiode 2500 may be provided in the layer between the transistor 2200 and the transistor 2100.

For more information on the other components of FIGS. 24 (A) and 24 (B), the descriptions in FIGS. 22 (A) and 23 may be incorporated.

Further, the photodiode 2400 or the photodiode 2500 may be formed by using a material capable of absorbing radiation and generating an electric charge. Materials capable of absorbing radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

For example, when selenium is used for the photodiode 2400 or the photodiode 2500, it is possible to realize a photoelectric conversion element having a light absorption coefficient over a wide wavelength band such as X-rays and gamma rays in addition to visible light and ultraviolet light.

&lt;Storage Device&gt; Fig. 25 is an example of a semiconductor device (storage device) that uses a transistor according to one aspect of the present invention, can retain stored contents even in a situation where power is not supplied, and has no limit on the number of writes. Shown in.

The semiconductor device shown in FIG. 25 is different from the storage device shown in the first embodiment in that the transistor 100 is not provided. In this case as well, the information can be written and held by the same operation as described above.

Next, reading out information of the semiconductor device shown in FIG. 25 will be described. When the transistor 200 is turned on, the floating wiring 3003 and the capacitance element 300 are electrically connected, and the electric charge is redistributed between the wiring 3003 and the capacitance element 300. As a result, the potential of the wiring 3003 changes. The amount of change in the potential of the wiring 3003 takes a different value depending on the potential of one of the electrodes of the capacitance element 300 (or the electric charge accumulated in the capacitance element 300).

For example, if the potential of one of the electrodes of the capacitance element 300 is V, the capacitance of the capacitance element 300 is C, the capacitance component of the wiring 3003 is CB, and the potential of the wiring 3003 before the charge is redistributed is VB0. The potential of the wiring 3003 after being redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, assuming that the potential of one of the electrodes of the capacitive element 300 takes two states of V1 and V0 (V1&gt; V0) as the state of the memory cell, the potential of the wiring 3003 when the potential V1 is held (= (= ( CB × VB0 + C × V1) / (CB + C)) is larger than the potential of wiring 3003 (= (CB × VB0 + C × V0) / (CB + C)) when the potential V0 is held. You can see that it will be higher.

Then, the information can be read out by comparing the potential of the wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor material is applied is used for the drive circuit for driving the memory cell, and a transistor to which the second semiconductor material is applied is laminated on the drive circuit as the transistor 200. And it is sufficient.

In the semiconductor device shown in the present embodiment, it is possible to retain the stored contents for an extremely long period of time by applying a transistor using an oxide semiconductor and having an extremely small off-current to the channel forming region. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Further, even when there is no power supply (however, it is desirable that the potential is fixed), it is possible to retain the stored contents for a long period of time.

Further, in the semiconductor device shown in the present embodiment, a high voltage is not required for writing information, and there is no problem of element deterioration. For example, unlike the conventional non-volatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating film does not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times that is a problem in the conventional non-volatile memory, and the reliability is dramatically improved. Further, since information is written depending on whether the transistor is on or off, high-speed operation can be easily realized.

The storage device shown in this embodiment is also applied to, for example, CPU (Central Processing Unit), DSP (Digital Signal Processor), custom LSI, LSI such as PLD (Programmable Logic Device), and RF-ID (Radio Frequency Identification). It is possible.

As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments.

(Embodiment 5) In the present embodiment, the transistor or RF device tag including the storage device exemplified in the above embodiment will be described with reference to FIG. 26.

The RF device tag in the present embodiment has a storage circuit inside, stores information necessary for the storage circuit, and exchanges information with the outside by using non-contact means, for example, wireless communication. Due to these characteristics, the RF device tag can be used in an individual authentication system or the like that identifies an article by reading individual information of the article or the like. In addition, extremely high reliability is required for use in these applications.

The configuration of the RF device tag will be described with reference to FIG. FIG. 26 is a block diagram showing a configuration example of an RF device tag.

As shown in FIG. 26, the RF device tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader / writer, etc.). Further, the RF device tag 800 has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. It should be noted that a material capable of sufficiently suppressing the reverse current, for example, an oxide semiconductor may be used for the transistor having a rectifying action included in the demodulation circuit 807. As a result, it is possible to suppress a decrease in the rectifying action due to the reverse current and prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit can be made linear with respect to the input of the demodulation circuit. There are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other to communicate by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. Be separated. The RF device tag 800 shown in the present embodiment can be used in any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal at the antenna 804, for example, half-wave double pressure rectification, and the signal rectified by the capacitive element provided in the subsequent stage is used. It is a circuit for generating an input potential by smoothing. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so that power exceeding a certain power is not input to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. The constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating the reset signal of the logic circuit 809 by utilizing the rise of the stable power supply voltage.

The demodulation circuit 807 is a circuit for generating a demodulated signal by demodulating the input AC signal by detecting the envelope. Further, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The storage circuit 810 is a circuit that holds the input information, and has a row decoder, a column decoder, a storage area, and the like. The ROM811 is a circuit for storing a unique number (ID) and the like and outputting according to processing.

It should be noted that each of the above-mentioned circuits can be appropriately discarded as needed.

Here, the storage device described in the previous embodiment can be used for the storage circuit 810. Since the storage device of one aspect of the present invention can retain information even when the power supply is cut off, it can be suitably used for an RF device tag. Further, the storage device of one aspect of the present invention does not cause a difference in the maximum communication distance between reading and writing data because the power (voltage) required for writing data is significantly smaller than that of the conventional non-volatile memory. It is also possible. Further, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power when writing data.

Further, since the storage device of one aspect of the present invention can be used as a non-volatile memory, it can also be applied to ROM 811. In that case, it is preferable that the producer separately prepares a command for writing data to the ROM 811 so that the user cannot freely rewrite the data. By shipping the product after the producer writes the unique number before shipping, it is possible to assign the unique number only to the non-defective product to be shipped, instead of assigning the unique number to all the RF device tags produced. , The unique number of the product after shipment does not become discontinuous, and customer management corresponding to the product after shipment becomes easy.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 6) In the present embodiment, at least the transistor described in the embodiment can be used, and the CPU including the storage device described in the previous embodiment will be described.

FIG. 27 is a block diagram showing an example configuration of a CPU using at least a part of the transistors described in the previous embodiment.

The CPU shown in FIG. 27 is an ALU1191 (ALU: Arithmetic logic unit, arithmetic unit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, and bus interface 1198 on the board 1190. It has an (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided on separate chips. Of course, the CPU shown in FIG. 27 is only an example showing a simplified configuration, and an actual CPU has a wide variety of configurations depending on its use. For example, the configuration including the CPU or the arithmetic circuit shown in FIG. 27 may be one core, and a plurality of the cores may be included so that each core operates in parallel. In addition, the number of bits that the CPU can handle in the internal arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit based on its priority and mask state during CPU program execution. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the CPU.

Further, the timing controller 1195 generates a signal for controlling the operation timing of the ALU1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the above-mentioned various circuits.

In the CPU shown in FIG. 27, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor shown in the previous embodiment can be used.

In the CPU shown in FIG. 27, the register controller 1197 selects the holding operation in the register 1196 according to the instruction from ALU1191. That is, in the memory cell of the register 1196, it is selected whether to hold the data by the flip-flop or the data by the capacitive element. When holding data by flip-flop is selected, the power supply voltage is supplied to the memory cell in register 1196. When data retention in the capacitive element is selected, the data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

FIG. 28 is an example of a circuit diagram of a storage element that can be used as the register 1196. The storage element 1200 has a selection function of a circuit 1201 in which stored data is volatilized when the power is cut off, a circuit 1202 in which the stored data is not volatilized when the power is cut off, a switch 1203, a switch 1204, a logic element 1206, and a capacitance element 1207. It has a circuit 1220 and has. Circuit 1202 includes capacitive elements 1208, transistors 1209, and transistors 1210. The storage element 1200 may further include other elements such as a diode, a resistance element, and an inductor, if necessary.

Here, the storage device described in the previous embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the storage element 1200 is stopped, the ground potential (0V) or the potential at which the transistor 1209 is turned off is continuously input to the gate electrode of the transistor 1209 of the circuit 1202. For example, the gate electrode of the transistor 1209 is grounded via a load such as a resistor.

The switch 1203 is configured with a monoconductive (eg, n-channel) transistor 1213, and the switch 1204 is configured with a conductive (eg, p-channel) transistor 1214 that is the opposite of the monoconductive. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source electrode and the drain electrode of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source electrode and the drain electrode of the transistor 1213, and the switch 1203 The control signal RD input to the gate electrode of transistor 1213 selects conduction or non-conduction (ie, on or off state of transistor 1213) between the first and second terminals. The first terminal of switch 1204 corresponds to one of the source and drain electrodes of transistor 1214, the second terminal of switch 1204 corresponds to the other of the source and drain electrodes of transistor 1214, and switch 1204 corresponds to the other of transistor 1214. The control signal RD input to the gate electrode selects conduction or non-conduction between the first terminal and the second terminal (that is, the on or off state of the transistor 1214).

One of the source and drain electrodes of transistor 1209 is electrically connected to one of the pair of electrodes of capacitive element 1208 and the gate electrode of transistor 1210. Here, the connection part is node M2. One of the source electrode and the drain electrode of the transistor 1210 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power potential, and the other is the first terminal of the switch 1203 (the source electrode of the transistor 1213). And one of the drain electrodes) is electrically connected. The second terminal of switch 1203 (the other of the source and drain electrodes of transistor 1213) is electrically connected to the first terminal of switch 1204 (one of the source and drain electrodes of transistor 1214). The second terminal of switch 1204 (the other of the source and drain electrodes of transistor 1214) is electrically connected to a wire that can supply the power potential VDD. The second terminal of switch 1203 (the other of the source and drain electrodes of transistor 1213), the first terminal of switch 1204 (one of the source and drain electrodes of transistor 1214), and the input terminal of logic element 1206. One of the pair of electrodes of the capacitive element 1207 is electrically connected. Here, the connection part is node M1. The other of the pair of electrodes of the capacitive element 1207 can be configured to receive a constant potential. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) can be input. The other of the pair of electrodes of the capacitive element 1207 is electrically connected to a wire (eg, a GND line) capable of supplying a low power potential. The other of the pair of electrodes of the capacitive element 1208 can be configured to receive a constant potential. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) can be input. The other of the pair of electrodes of the capacitive element 1208 is electrically connected to a wire (eg, a GND line) capable of supplying a low power potential.

The capacitive element 1207 and the capacitive element 1208 can be omitted by positively utilizing the parasitic capacitance of the transistor and the wiring.

The control signal WE is input to the first gate electrode of transistor 1209. The switch 1203 and switch 1204 are selected from the conductive state and the non-conducting state between the first terminal and the second terminal by the control signal RD different from the control signal WE, and the first terminal and the second terminal of one switch are selected. When there is a conductive state between the terminals of, there is a non-conducting state between the first terminal and the second terminal of the other switch.

A signal corresponding to the data held in the circuit 1201 is input to the other of the source electrode and the drain electrode of the transistor 1209. FIG. 28 shows an example in which the signal output from the circuit 1201 is input to the other of the source electrode and the drain electrode of the transistor 1209. The signal output from the second terminal of the switch 1203 (the other of the source electrode and the drain electrode of the transistor 1213) becomes an inverted signal whose logic value is inverted by the logic element 1206, and is input to the circuit 1201 via the circuit 1220. Will be done.

Note that FIG. 28 shows an example in which the signal output from the second terminal of the switch 1203 (the other of the source electrode and the drain electrode of the transistor 1213) is input to the circuit 1201 via the logic element 1206 and the circuit 1220. Is not limited to this. The signal output from the second terminal of switch 1203 (the other of the source electrode and drain electrode of transistor 1213) may be input to circuit 1201 without inverting the logic value. For example, in the circuit 1201, when the node signal whose logic value of the input signal from the input terminal is inverted is held there, the second terminal of the switch 1203 child (the source electrode and the drain electrode of the transistor 1213 The signal output from (the other) can be input to the relevant node.

Further, in FIG. 28, among the transistors used in the storage element 1200, the transistors other than the transistor 1209 can be a transistor having a channel formed on a layer made of a semiconductor other than an oxide semiconductor or a substrate 1190. For example, it can be a transistor in which a channel is formed on a silicon layer or a silicon substrate. Further, all the transistors used in the storage element 1200 may be transistors whose channels are formed of an oxide semiconductor film. Alternatively, the storage element 1200 may include a transistor whose channel is formed of an oxide semiconductor film in addition to the transistor 1209, and the remaining transistor has a channel on a layer or substrate 1190 made of a semiconductor other than the oxide semiconductor. It can also be a transistor to be formed.

For the circuit 1201 in FIG. 28, for example, a flip-flop circuit can be used. Further, as the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device according to one aspect of the present invention, the data stored in the circuit 1201 can be held by the capacitive element 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the storage element 1200.

Further, the off-current of the transistor in which the channel is formed in the oxide semiconductor film is extremely small. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor film is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held by the capacitive element 1208 is maintained for a long period of time even when the power supply voltage is not supplied to the storage element 1200. In this way, the storage element 1200 can retain the stored contents (data) even when the supply of the power supply voltage is stopped.

Further, since the storage element is characterized in that the precharge operation is performed by providing the switch 1203 and the switch 1204, the time until the circuit 1201 re-holds the original data after the power supply voltage supply is restarted is shortened. be able to.

Further, in the circuit 1202, the signal held by the capacitive element 1208 is input to the gate electrode of the transistor 1210. Therefore, after the supply of the power supply voltage to the storage element 1200 is resumed, the signal held by the capacitive element 1208 can be converted into the state (on state or off state) of the transistor 1210 and read out from the circuit 1202. it can. Therefore, it is possible to accurately read the original signal even if the potential corresponding to the signal held by the capacitive element 1208 fluctuates to some extent.

By using such a storage element 1200 in a storage device such as a register or a cache memory included in the processor, it is possible to prevent data loss in the storage device due to a stop supply of the power supply voltage. Further, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply is stopped in a short time. Therefore, the power consumption can be suppressed because the power can be stopped even for a short time in the entire processor or one or a plurality of logic circuits constituting the processor.

In the present embodiment, the storage element 1200 has been described as an example of using the storage element 1200 for the CPU, but the storage element 1200 includes a DSP (Digital Signal Processor), a custom LSI, an LSI such as a PLD (Programmable Logic Device), and an RF-ID (Radio Frequency). It can also be applied to Identification).

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 7) In the present embodiment, the display device according to one aspect of the present invention will be described with reference to FIGS. 29 and 30.

As the display element used in the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element (also referred to as a light emitting display element), or the like can be used. The light emitting element includes an element whose brightness is controlled by current or voltage in its category, and specifically includes an inorganic EL (Electroluminescence), an organic EL, and the like. Hereinafter, as an example of the display device, a display device using an EL element (EL display device) and a display device using a liquid crystal element (liquid crystal display device) will be described.

The display device shown below includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel.

The display device shown below refers to an image display device or a light source (including a lighting device). In addition, the display device includes all connectors such as FPC, a module to which TCP is attached, a module having a printed wiring board at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by the COG method.

FIG. 29 is an example of an EL display device according to one aspect of the present invention. FIG. 29 (A) shows a circuit diagram of the pixels of the EL display device. FIG. 29B is a top view showing the entire EL display device. Further, FIG. 29 (C) is an MN cross section corresponding to a part of the alternate long and short dash line MN of FIG. 29 (B).

FIG. 29 (A) is an example of a circuit diagram of pixels used in an EL display device.

In addition, in this specification etc., it is not necessary to specify the connection destinations of all the terminals of active elements (transistors, diodes, etc.), passive elements (capacitive elements, resistance elements, etc.), etc. For example, it may be possible to construct one aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. Then, when the content in which the connection destination is specified is described in the present specification or the like, it can be determined that one aspect of the invention in which the connection destination is not specified is described in the present specification or the like. There is. In particular, when a plurality of locations are assumed as the connection destinations of the terminals, it is not necessary to limit the connection destinations of the terminals to a specific location. Therefore, one aspect of the invention can be configured by specifying the connection destination of only some terminals of active elements (transistors, diodes, etc.), passive elements (capacitive elements, resistance elements, etc.). In some cases.

In the present specification and the like, a person skilled in the art may be able to specify the invention if at least the connection destination is specified for a certain circuit. Alternatively, a person skilled in the art may be able to specify the invention by at least specifying the function of a certain circuit. That is, it can be said that one aspect of the invention is clear if the function is specified. Then, it may be possible to determine that one aspect of the invention whose function has been specified is described in the present specification or the like. Therefore, for a certain circuit, if the connection destination is specified without specifying the function, it is disclosed as one aspect of the invention, and one aspect of the invention can be configured. Alternatively, for a certain circuit, if the function is specified without specifying the connection destination, it is disclosed as one aspect of the invention, and one aspect of the invention can be configured.

The EL display device shown in FIG. 29 (A) includes a switch element 743, a transistor 741, a capacitance element 742, and a light emitting element 719.

Since FIG. 29 (A) and the like are examples of the circuit configuration, it is possible to further add a transistor. Conversely, it is possible not to add transistors, switches, passive elements, etc. at each node in FIG. 29 (A).

The gate electrode of the transistor 741 is electrically connected to the first terminal of the switch element 743 and one electrode of the capacitive element 742. The source electrode of the transistor 741 is electrically connected to the other electrode of the capacitive element 742 and is electrically connected to one electrode of the light emitting element 719. The drain electrode of transistor 741 is given the power supply potential VDD. The second terminal of the switch element 743 is electrically connected to the signal line 744. The other electrode of the light emitting element 719 is given a constant potential. The constant potential is the ground potential GND or a potential smaller than that.

It is preferable to use a transistor as the switch element 743. By using a transistor, the pixel area can be reduced and an EL display device with high resolution can be obtained. Further, if a transistor manufactured through the same process as the transistor 741 is used as the switch element 743, the productivity of the EL display device can be increased. As the transistor 741 and / and the switch element 743, for example, the above-mentioned transistor can be applied.

FIG. 29B is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealing material 734, a drive circuit 735, a drive circuit 736, a pixel 737, and an FPC 732. The sealing material 734 is arranged between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. The drive circuit 735 and / and the drive circuit 736 may be arranged outside the sealing material 734.

FIG. 29 (C) is a cross-sectional view of an EL display device corresponding to a part of the alternate long and short dash line MN of FIG. 29 (B).

In FIG. 29 (C), the conductor 712 on the substrate 700, the semiconductor 706a and the semiconductor 706b on the insulator 712, and the conductor 716a and the conductor 716b in contact with the semiconductor 706a and the semiconductor 706b are shown as transistors 741. A structure having a semiconductor 706c and an insulator 718 on a semiconductor 706b, a conductor 716a and a conductor 716b, and a conductor 714a and a conductor 714b on the semiconductor 718 and overlapping the semiconductor 706c is shown. The structure of the transistor 741 is an example, and the structure may be different from the structure shown in FIG. 29 (C).

Therefore, in the transistor 741 shown in FIG. 29 (C), the conductor 714a and the conductor 714b have a function as a gate electrode, the insulator 718 has a function as a gate insulator, and the conductor 716a is a source electrode. The conductor 716b has a function as a drain electrode.

In FIG. 29C, as the capacitance element 742, a capacitance element having the same structure as the capacitance element 300 shown in the above embodiment can be used. By using the capacitive element having the above configuration, a three-dimensional capacitive element can be formed. As a result, the capacitance per projected area of the capacitive element can be increased, so that the area of the EL display device can be reduced, highly integrated, and miniaturized.

Further, the capacitive element 742 can be manufactured by using a film common to the transistor 741. Further, it is preferable that the conductor 716a and the first electrode of the capacitive element 742 are the same type of conductor. In that case, the conductor 716a and the first electrode of the capacitive element 742 can be formed through the same steps. Further, it is preferable that the conductor 714a and the conductor 714b are the same type of conductors as the second electrode of the capacitive element 742. In that case, the conductor 714a and the conductor 714b and the second electrode of the capacitive element 742 can be formed through the same process.

The capacitance element 742 shown in FIG. 29 (C) is a capacitance element having a large capacitance per occupied area. Therefore, FIG. 29 (C) is an EL display device having high display quality.

An insulator 720 is arranged on the transistor 741 and the capacitive element 742. Here, the insulator 720 may have an opening that reaches the conductor 716a, which functions as a source electrode for the transistor 741. A conductor 781 is arranged on the insulator 720. The conductor 781 may be electrically connected to the transistor 741 through the opening of the insulator 720.

On the conductor 781, a partition wall 784 having an opening reaching the conductor 781 is arranged. A light emitting layer 782 in contact with the conductor 781 at the opening of the partition wall 784 is arranged on the partition wall 784. A conductor 783 is arranged on the light emitting layer 782. The overlapping region of the conductor 781, the light emitting layer 782, and the conductor 783 is the light emitting element 719.

Up to this point, an example of an EL display device has been described. Next, an example of the liquid crystal display device will be described.

FIG. 30A is a circuit diagram showing a configuration example of pixels of a liquid crystal display device. The pixel shown in FIG. 30 has a transistor 751, a capacitive element 752, and an element (liquid crystal element) 753 in which liquid crystal is filled between a pair of electrodes.

In the transistor 751, one of the source electrode and the drain electrode is electrically connected to the signal line 755, and the gate electrode is electrically connected to the scanning line 754.

In the capacitive element 752, one electrode is electrically connected to the other of the source electrode and the drain electrode of the transistor 751, and the other electrode is electrically connected to the wiring that supplies a common potential.

In the liquid crystal element 753, one electrode is electrically connected to the other of the source electrode and the drain electrode of the transistor 751, and the other electrode is electrically connected to the wiring that supplies a common potential. The common potential given to the wiring electrically connected to the other electrode of the capacitance element 752 described above and the common potential given to the other electrode of the liquid crystal element 753 may be different potentials.

The top view of the liquid crystal display device will be described as being the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the alternate long and short dash line MN of FIG. 29 (B) is shown in FIG. 30 (B). In FIG. 30B, the FPC 732 is connected to the wiring 733a via the terminal 731. The wiring 733a may use a conductor or semiconductor of the same type as any of the conductors or semiconductors constituting the transistor 751.

Transistor 751 refers to the description of transistor 741. Further, for the capacitive element 752, refer to the description of the capacitive element 742. Note that FIG. 30 (B) shows the structure of the capacitive element 752 corresponding to the capacitive element 742 of FIG. 29 (C), but the present invention is not limited to this.

When an oxide semiconductor is used as the semiconductor of the transistor 751, it can be a transistor having an extremely small off-current. Therefore, the electric charge held in the capacitive element 752 is less likely to leak, and the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, by turning off the transistor 751 when displaying a moving image or a still image with little movement, power for the operation of the transistor 751 is not required, and a liquid crystal display device having low power consumption can be obtained. Further, since the occupied area of the capacitive element 752 can be reduced, it is possible to provide a liquid crystal display device having a high aperture ratio or a liquid crystal display device having a high definition.

An insulator 721 is arranged on the transistor 751 and the capacitive element 752. Here, the insulator 721 has an opening that reaches the transistor 751. A conductor 791 is arranged on the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 721.

An insulator 792 that functions as an alignment film is arranged on the conductor 791. A liquid crystal layer 793 is arranged on the insulator 792. An insulator 794 that functions as an alignment film is arranged on the liquid crystal layer 793. A spacer 795 is arranged on the insulator 794. A conductor 796 is placed on the spacer 795 and the insulator 794. The substrate 797 is arranged on the conductor 796.

By having the above-mentioned structure, it is possible to provide a display device having a capacitive element having a small occupied area, or to provide a display device having high display quality. Alternatively, a high-definition display device can be provided.

For example, in the present specification and the like, the display element, the display device which is a device having a display element, the light emitting element, and the light emitting device which is a device having a light emitting element use various forms or have various elements. Can be done. The display element, display device, light emitting element or light emitting device is, for example, a light emitting diode (LED: Light Emitting) such as white, red, green or blue. Diode), transistor (transistor that emits light according to current), electron emitting element, liquid crystal element, electronic ink, electrophoresis element, grating light valve (GLV), plasma display (PDP), MEMS (micro electromechanical system) ), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), IMOD (Interference Modulation) Element, Shutter-type MEMS Display Element, Optical Interference-type MEMS Display, Electro It has at least one such as a wetting element, a piezoelectric ceramic display, and a display element using carbon nanotubes. In addition to these, a display medium whose contrast, brightness, reflectance, transmittance, etc. change due to an electric or magnetic action may be provided.

An example of a display device using an EL element is an EL display. An example of a display device using an electron emitting element is a field emission display (FED) or a surface-conduction electron-emitter display (SED). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using an electronic ink, an electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

When an LED is used, graphene or graphite may be arranged under the LED electrode or the nitride semiconductor. Graphene and graphite may be formed into a multilayer film by stacking a plurality of layers. By providing graphene or graphite in this way, a nitride semiconductor, for example, an n-type GaN semiconductor having crystals, can be easily formed on the graphene. Further, a p-type GaN semiconductor having a crystal or the like can be provided on the p-type GaN semiconductor to form an LED. An AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having crystals. The GaN semiconductor of the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor contained in the LED can also be formed by a sputtering method.

(Embodiment 8) The semiconductor device according to one aspect of the present invention reproduces a recording medium such as a display device, a personal computer, and an image playback device (typically, a DVD: Digital Versatile Disc) including a recording medium, and reproduces the recording medium. It can be used for a device having a display capable of displaying an image). In addition, as electronic devices that can use the semiconductor device according to one aspect of the present invention, mobile phones, game machines including portable types, mobile data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, and goggles. Type display (head mount display), navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer compound machine, automatic teller machine (ATM), vending machine, etc. Be done. Specific examples of these electronic devices are shown in FIG.

FIG. 31 (A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, an operation key 907, a stylus 908, and the like. The portable game machine shown in FIG. 31 (A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this.

FIG. 31B is a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connecting portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. is there. The image in the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 in the connection unit 915. Further, a display device having a function as a position input device may be used for at least one of the first display unit 913 and the second display unit 914. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, which is also called a photo sensor, in the pixel portion of the display device.

FIG. 31 (C) is a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard 923, a pointing device 924, and the like.

FIG. 31 (D) is an electric refrigerator / freezer, which has a housing 931, a refrigerator door 932, a freezer door 933, and the like.

FIG. 31 (E) is a video camera, which has a first housing 941, a second housing 942, a display unit 943, an operation key 944, a lens 945, a connection unit 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by the connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. is there. The image on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 on the connection unit 946.

FIG. 31 (F) is a passenger car, which has a vehicle body 951, wheels 952, dashboard 953, lights 954, and the like.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 9) In the present embodiment, an example of using the RF device tag according to one aspect of the present invention will be described with reference to FIG. 32. RF device tags have a wide range of uses, such as banknotes, coins, securities, bearer bonds, certificates (driver's license, residence card, etc., see Figure 32 (A)), recording media (DVD and video tape). Etc. (see Fig. 32 (B)), packaging containers (wrapping paper, bottles, etc., see Fig. 32 (C)), vehicles (bicycles, etc., see Fig. 32 (D)), personal belongings (bags, glasses, etc.) ), Foods, plants, animals, human body, clothing, daily necessities, medical products containing chemicals and drugs, or electronic devices (liquid crystal display device, EL display device, television device, or mobile phone) Or, it can be used by being provided on a tag attached to each article (see Fig. 32 (E) and Fig. 32 (F)).

The RF device tag 4000 according to one aspect of the present invention is fixed to an article by being attached to or embedded in a surface. For example, if it is a book, it is embedded in paper, and if it is a package made of organic resin, it is embedded inside the organic resin and fixed to each article. Since the RF device tag 4000 according to one aspect of the present invention realizes small size, thinness, and light weight, the design of the article itself is not impaired even after being fixed to the article. Further, an authentication function can be provided by providing the RF device tag 4000 according to one aspect of the present invention on banknotes, coins, securities, bearer bonds, certificates, etc., and if this authentication function is utilized, , Can prevent counterfeiting. Further, by attaching the RF device tag 4000 according to one aspect of the present invention to packaging containers, recording media, personal belongings, foods, clothing, daily necessities, electronic devices, etc., the efficiency of the system such as the inspection system Can be achieved. Further, even for vehicles, the security against theft can be enhanced by attaching the RF device tag 4000 according to one aspect of the present invention.

As described above, by using the RF device tag according to one aspect of the present invention for each of the applications listed in the present embodiment, the operating power including writing and reading of information can be reduced, so that the maximum communication distance can be lengthened. It becomes possible. Further, since the information can be retained for an extremely long period even when the power is cut off, it can be suitably used for applications in which the frequency of writing and reading is low.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

100 Transistor 101 Semiconductor substrate 102 Semiconductor film 103a Low resistance layer 103b Low resistance layer 104 Gate insulating film 105 Gate electrode 105a Gate electrode 105b Gate electrode 110 Wiring 111a Wiring 111b Wiring 121 Insulating film 122 Insulating film 200 Transistor 201 Insulating film 202 Insulating film 203a Oxide semiconductor layer 203b Oxide semiconductor layer 203c Oxide semiconductor layer 204a Electrode 204b Electrode 205 Gate insulating film 206 Gate electrode 206a Conductor 206b Conductor 207 Insulating film 208 Insulating film 209a Low resistance region 209b Low resistance region 250 Wiring 300 Capacitive element 301 Insulating film 302 Electrode 302a Conductive layer 302A Conductive layer 302b Conductive layer 302B Conductive 302C Conductive 302c Conductive 303 Barrier layer 303A Barrier film 303B Barrier layer 304 Insulation 305 Electrode 305A Conductor 305a Conductor 305b Conductor 306 Insulation film 307 Wiring 308 Wiring 310 Contact hole 319 Resist mask 320 Resist mask 325 Resist mask 330 Resist mask 340 Intermediate layer 350 Wiring 700 Substrate 706a Semiconductor 706b Semiconductor 706c Semiconductor 712 Insulation Body 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718 Insulator 719 Light emitting element 720 Insulator 721 Insulator 731 Terminal 732 FPC733a Wiring 734 Sealing material 735 Drive circuit 736 Drive circuit 737 Pixel 741 Transistor 742 Capacitive element 743 Switch element 744 Signal line 750 Board 751 Transistor 752 Capacitive element 753 Liquid crystal element 754 Scan line 755 Signal line 781 Conductor 782 Light emitting layer 783 Conductor 784 Partition 791 Conductor 792 Insulation 793 Liquid crystal layer 794 Insulation 795 Spacer 796 Conductor 797 Board 800 RF device tag 801 Communicator 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Storage circuit 811 ROM901 Housing 902 Housing 903 Display 904 Display 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display 914 Display 915 Connection 916 Operation key 921 Housing 922 Display 923 Keyboard 924 Pointing device 931 Housing 932 Refrigerating room door 933 Freezing room door 941 Housing 942 Housing 943 Display 944 Operation keys 945 Lens 946 Connection 951 Body 952 Wheel 953 Dashboard 954 Light 1189 ROM interface 1190 Board 1191 ALU1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM1200 Storage element 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic element 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2001 Board 2004 Plug 2100 Transistor 2200 Transistor 2201 Insulation film 2202 Wiring 2203 Plug 2204 Interlayer insulation film 2207 Insulation film 2211 Semiconductor substrate 2212 Insulating film 2213 Gate electrode 2214 Gate insulating film 2215 Source area and drain area 2300 Transistor 2301 Impurity area 2302 Impermentation area 2303 Gate electrode 2304 Gate insulating film 2305 Side wall insulating film 2400 Photoconductor 2401 Conductive 2402 Conductive 2403 Conductive 2500 Photodiode 2501 Conductive 2502 Conductive 2503 Semiconductor layer 2504 Plug 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 4000 RF device tag 5100 Crystal part 5120 Substrate 5161 area