Timebase synchronization

The embodiments described herein relate to time-based synchronization in integrated circuits such as systems on a chip (SOC). [Explanation of related technologies]

In digital systems, real time (or "wall clock time") is represented by a timebase. Typically, the timebase is reset to zero at system startup and incremented according to the clock in the system. If the real time at system startup is known (usually maintained by software), the timebase value can be added to the real time to determine the current time.

For larger systems, or integrated circuits within the system, it is difficult to access a single global timebase with short latency. In the past, global timebase buses were sent across SOCs where access to the timebase was needed. Although this technique can provide short latency access, it increases the area overhead to route the bus to all desired access points and is physically designed for signal propagation latency on the bus. It is difficult to close the timing of. Another approach involves adding a local timebase across the SOC. However, due to fluctuations in the local clock, as well as different clock sources for clocks at various points, synchronization between the global timebase and the local timebase can easily be lost. The software can read the global timebase, propagate this timebase to the local timebase, and synchronize it to the local timebase, but you must consider the latency of propagating new values. It is difficult to make an accurate judgment. In addition, software synchronization can be much less frequent than desired, causing the local timebase to experience large fluctuations during the time period between synchronizations.

In addition, high quality crystal clock signals are required to maintain time-based accuracy. Low frequency crystal clock signals may be available, but such clocks have higher timebase accuracy because timebase updates occur too rarely compared to the operating clock frequencies of the various components of the SOC. / Does not provide grain size. It is difficult to obtain the required frequency via the crystal signal. Moreover, although an external timebase can be maintained based on the low frequency crystal clock signal, synchronization between the external timebase and the various timebases within the SOC can be difficult to achieve.

In one embodiment, integrated circuits such as SOCs (or even individual chip systems) include one or more local timebases at various locations. The timebase can be incremented based on a high frequency local clock that can fluctuate during use. Periodically, the local timebase can be synchronized to the exact time using hardware circuits, based on a low frequency clock that is less subject to fluctuations. Specifically, the exact timebase value for the next synchronization can be sent to each local timebase, and the local timebase control circuit will have the exact value in the local timebase before the synchronization occurs. Can be configured to saturate the local timebase to the correct value when it reaches. Similarly, if synchronization occurs and the local timebase has not reached the exact timebase, the control circuit can be configured to load the exact timebase value. Therefore, it is possible to eliminate the need for software synchronization while supporting high time-based resolution / particle size, short latency access to the time base, and high time base accuracy. Synchronization to external timebases can also be performed, for example, by sending the exact timebase values for the external timebases in the next synchronization event to the local timebases and saturating / updating to those local timebases. it can. The following detailed description will refer to the accompanying drawings briefly described below.

<figref num="1">It is a block diagram of one Embodiment of an integrated circuit including SOC.</figref><figref num="2">It is a block diagram of one Embodiment of a local time base circuit.</figref><figref num="3">It is a block diagram of one Embodiment of a global time base circuit.</figref><figref num="4">It is a timing diagram which shows one Embodiment of time-based synchronization.</figref><figref num="5">It is a flowchart which shows the operation of one Embodiment of a local time base circuit for synchronizing a time base.</figref><figref num="6">It is a flowchart which shows the operation of one Embodiment of the global time base circuit for synchronizing the time base.</figref><figref num="7">It is a flowchart which shows the operation of one Embodiment of a global time base circuit and a local time base circuit for initializing a time base.</figref><figref num="8">It is a block diagram of one Embodiment of a system.</figref>

Although there may be room for various modifications and alternatives to the embodiments described in this disclosure, specific embodiments thereof are shown in the drawings as examples and will be described in detail in the present specification. However, the drawings and the detailed description of the drawings are not intended to limit the embodiments to the particular embodiments disclosed, but rather the intent is to all modifications contained within the gist and scope of the appended claims. , Equal forms, and alternative forms should be understood. The headings used herein are for construction purposes only and are not intended to be used to limit the scope of the description. As used throughout this application, the word "may" does not have an obligatory meaning (ie, means must), but an acceptable meaning (ie, must). (Meaning that it has the potential). Similarly, the terms "include," "including," and "includes" mean to include, but not to be limited to, something. ..

Various units, circuits, or other components may be described as "configured to" performing one task (s). In such situations, "configured to" has "having" to perform a task (s) during operation. It is a broad description of the structure that broadly means "circuits)". Thus, a unit / circuit / component can be configured to perform a task even when the unit / circuit / component is not currently operating. In general, the circuit forming the structure corresponding to "configured as" may include a hardware circuit. Hardware circuits include combination logic circuits, clocked storage devices such as flops, registers and latches, finite state machines, memory such as static random access memory or embedded dynamic random access memory, custom designed circuits, analog circuits, programmable logic arrays, etc. Can include any combination of. Similarly, various units / circuits / components may be described as performing a task (s) for the sake of brevity. Such an explanation should be construed as including the phrase "consisting as". The description of a unit / circuit / component that is configured to perform one or more tasks explicitly does not refer to the interpretation of 35 USC 112 (f) for that unit / circuit / component. Intended to.

In one embodiment, a hardware circuit according to the present disclosure describes the circuit in a hardware description language such as Verilog or VHDL. It may be implemented by coding in language) (HDL). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons and sent to the foundry as a result. It becomes a final design database that can be used, masks can be generated, and finally integrated circuits can be manufactured. Some hardware circuits or parts thereof can also be custom designed in the schematic editor and incorporated into the integrated circuit design along with the synthesized circuit. The integrated circuit may include a transistor and may further include other circuit elements (eg, passive elements such as capacitors, resistors, inductors) and interconnects between the transistor and the circuit element. Some embodiments may implement multiple integrated circuits that are integrally coupled to implement a hardware circuit, and / or, in some embodiments, individual devices may be used. .. Alternatively, the HDL design is a field programmable gate array. It may be synthesized into a programmable logical array such as array) (FPGA) or implemented in the FPGA.

This specification includes references to "one embodiment" or "an embodiment". Embodiments that include any combination of features are generally intended, but unless expressly denied herein, the phrase "in one embodiment" or "in an embodiment" is not necessarily the same embodiment. Does not point to. Specific functions, structures or properties may be combined in any suitable manner consistent with the present disclosure.

Next, referring to FIG. 1, a block diagram of an embodiment of SOC 10 coupled to memory 12 and an external clock source 34 is shown. As the name implies, the components of SOC10 can be integrated on a single semiconductor substrate as an integrated circuit "chip". In some embodiments, the components may be mounted on two or more separate chips in the system. However, in this specification, SOC10 is used as an example. In an exemplary embodiment, the components of SOC10 are central processing. unit) (CPU) complex 14, "always on" component 16, peripheral components 18A-18B (easier, "peripheral"), memory controller 22, power manager (PMGR) 32, internal clock generator 36, And communication fabric 27. The components 14, 16, 18A-18B, 22, 32, and 36 can all be coupled to the communication fabric 27. The memory controller 22 can be coupled to the memory 12 during use. The always-on component 16 can be connected to an external clock source 34. In an exemplary embodiment, the CPU complex 14 may include one or more processors (P30 in FIG. 1). The processor 30 can form the CPU (s) of the CPU complex 14 in the SOC 10. In some embodiments, a second internal clock generator 37 may be included and may be coupled to one or more local timebases (eg, the local timebase 26B of FIG. 1). In such an embodiment, the local timebase 26B does not have to be coupled to the clock generator circuit 36. In still other embodiments, additional clock generation circuits may be included.

Various components within SOC10 may have access to the timebase to determine the time. You can use a timebase to generate a time stamp of an event (for example, to be able to see the temporal order of the events, or to associate a given event with a particular real-time (wall clock time)). Can be done). Timebases can be used to provide time to an application (eg, display to the user or enable time-based notifications such as alerts or alarms). You can use the timebase to measure elapsed time (for example, schedule the execution of tasks in a multitasking operating system). In general, the time base can be any unit of time. In one embodiment, the timebase may be a value representing a particular particle size of time (eg, the least significant digit can represent a particular time). Some of the least significant digits do not have to be implemented in practice (for example, if the timebase value measures time at a higher particle size than the SOC10 clock can allow). In other embodiments, the timebase value may measure the clock tick of SOC10. Real time can be calculated based on the frequency of the clock.

Components that use the timebase can include local timebase circuits (eg, local timebase circuits 26A-26D, peripherals 18A, memory controller 22, and PMGR32 in the CPU complex 14 of FIG. 1). In one embodiment, the component can have multiple local timebase circuits (eg, there may be local timebase circuits 26A-26D for each CPU 30 in the CPU complex 14), and / Or multiple components may share the local timebase circuits 26A-26D. The global timebase circuit 20 in the always-on component 16 may be configured to synchronize the local timebase maintained by the local timebase circuits 26A-26D. In some embodiments, the global timebase circuit 20 can also maintain a global timebase.

The clock generator 36 is configured to generate a relatively high frequency clock (Fr_clk) that can be used to update the local timebase (and optionally the global timebase if included). You may. As a result, Fr_clk is coupled between the clock generator 36, the local timebase circuits 26A to 26D, and the global timebase circuit 20 optionally. The clock generator 36 may have any design and configuration, such as a phase-locked-loop (PLL), a delay-locked-loop (DLL), and the like. In general, the clock generator 36 may be under the influence of sources of various inaccuracies that lead to fluctuations in the clock frequency of Fr_clk during use. For example, the circuit in the clock generator 36 may be susceptible to fluctuations due to temperature changes, power supply voltage fluctuations that change the circuit delay, jitter, noise, and the like. Examples of the power supply voltage fluctuation include noise, transient fluctuation due to load, and intentional fluctuation such as dynamic voltage change during use. The frequency of Fr_clk may drift over time and is faster and / or slower than the desired frequency. This can lead to errors in the local timebase.

Based on circuit analysis, empirical data, and / or simulation, the frequency variation can be determined to be within the range around the desired frequency. The desired frequency (ie, the frequency expected from the clock generator 36) can be referred to as the nominal frequency. The clock can be said to have a given frequency nominally known to have some variation around the nominal frequency. Clocks can be nominally referred to as having higher or lower frequencies by comparing their nominal frequencies and knowing that fluctuations can change frequencies.

The low frequency clock (Rt_clk) can be received on the input to SOC10 (eg for external clock source 34). The external clock source 34 can be a "high quality" clock source, such as a crystal oscillator. Clock quality can be measured in a variety of ways, but generally refers to clocks that experience low fluctuations during use. This allows Rt_clk to have lower variability in use than, for example, Fr_clk. That is, the range of fluctuation of the clock frequency around the nominal frequency of Rt_clk can be made smaller than the range of fluctuation of Fr_clk.

Therefore, synchronization events can be triggered from Rt_clk to synchronize local timebases (both with each other and with exact timebase values). The synchronization event can be any communication that causes time-based synchronization. For example, the global timebase circuit 20 can be configured to assert the signal triggered by Rt_clk to the local timebase circuits 26A-26C. The global timebase circuit 20 can also communicate the next timebase sync value based on Rt_clk so that the local timebase has a sync value for updates. In one embodiment, the global timebase circuit 20 can trigger a synchronization event once each period of the Rt_clk signal. For example, a synchronization event may be triggered at the edge of the clock. As an example of this explanation, a rising edge may be used, but a falling edge may be used. The global timebase circuit 20 can also transmit the next timebase synchronization value depending on the edge (eg, the edge opposite the edge of the synchronization event, or the falling edge relative to the rising edge example). Other embodiments can optionally define synchronization events to occur for multiple periods of Rt_clk, or at once on each edge of Rt_clk.

The next time-based synchronization value may generate each synchronization period from the previous synchronization value and a value that depends on the frequency ratio of Fr_clk to Rt_clk. Since this ratio is not an integer value, the timebase may have an integer part and a decimal part with respect to the Rt_clk period. For example, in one embodiment, Fr_clk may be 24 MHz (MHz) and Rt_clk may be 32,768 Hz. In this example, in the simplest mathematical form, the ratio is 24MHz / 32,768Hz, or 46875/64. Therefore, the difference between consecutive synchronous timebase values may be 46875, and each clock period in Fr_clk may be an increment of 64 on the local timebase. The fractional part may be 5 bits because each increment is 64, and in various embodiments, the fractional part may or may not be implemented, if desired. In some embodiments, the fractional part can be used to prevent drift of the local timebase to a timebase derived from an external clock source. This allows both the increment of Fr_clk and the difference between successive sync values to depend on the frequency ratio.

In one embodiment, at least one local timebase circuit 26A-26D is configured to capture the next timebase synchronization value transmitted by the global timebase circuit 20 so that the local timebase is within a given synchronization period. Once incremented, the local timebase can be compared to the next timebase sync value. If Fr_clk is operating at a higher frequency than expected, the local timebase can reach the next timebase synchronization value before the end of the synchronization period. The local timebase circuits 26A to 26D can saturate the local timebase value to the next timebase synchronization value for the rest of the synchronization period. This ensures that the local timebase does not have to be "forward" to the exact timebase value, much more than the timebase would have at the end of the synchronization period. In addition, depending on the synchronization event, the local timebase circuits 26A-26D may load the next timebase synchronization value into the local timebase (assuming the local timebase has not reached the next synchronization value). do it). Loading the next time-based synchronization value can prevent the local time base from coming "after" the exact time base beyond the synchronization period.

The following time-based synchronization values can be transmitted from the global time-based circuit 20 to the local time-based circuits 26A-26D using any communication mechanism. In one embodiment, the value can be transmitted using a serial interface at the speed of Fr_clk. In this example, since Fr_clk has a much higher frequency than Rt_clk, the local timebase circuits 26A-26B can receive the next timebase synchronization value long before the end of the synchronization period.

An exemplary embodiment shows one Fr_clk provided by the clock generator circuit 36 to the local timebase circuits 26A-26D and the global timebase circuit 20, while the other embodiment is in chained line form in FIG. It is possible to have multiple sources of Fr_clk, such as a clock generator 37 that provides the indicated Fr_clk2 to the local timebase circuit 26B. In such an embodiment, the local timebase circuit 26B does not have to receive Fr_clk from the clock generator circuit 36. In yet another embodiment, there may be more internal clock generators that provide other Fr_clk to the various local timebase circuits 26A-26D. The sources may be independent of each other so that the clock phases and frequencies can be different during use.

As mentioned above, the increment can be saturated to the next time-based synchronization value for a given synchronization period. In general, saturating a value may mean incrementing to that value, but then holding the incremented result at that value steadily for additional increments. Incrementing can generally refer to increasing the value by a certain amount during use. A quantification may, in some embodiments, be one or any other integer or other value. In the example described above, the increment may be 64.

In one embodiment, the always-on component 16 appears to remain powered on when the other components of the SOC 10 (eg, CPU complex 14, peripherals 18A-18B, and PMGR32) are powered off. Can be configured in. More specifically, the always-on component 16 has a SOC 10 external power management unit (power management). It can be turned on whenever it is receiving power from the unit) (PMU). Thus, the always-on component can be powered on when the SOC10 is receiving some power (eg, when the device containing the SOC10 is in standby mode or is actively operating). , SOC10 is "always on" in the sense that it does not have to be turned on when it is not receiving any power (eg, when the device is completely turned off). The always-on component 16 may support certain functions while the rest of the SOC 10 is off, allowing low power operation. In addition, the global timebase circuit 20 can continue to maintain the global timebase for the system, eliminating the need to reconfigure the global timebase the next time the SOC10 is powered up.

In FIG. 1, a dotted line 24 that separates the always-on component 16 from other components may indicate an independent power domain for the always-on component 16. Other components, groups of components, and / or subcomponents may also have independent power domains. In general, a power domain can be configured to receive (ie, power on) or not receive (ie, power off) the power supply voltage independently of the other power domains. In some embodiments, different power supply voltages of different magnitudes can be supplied to multiple power domains at the same time. Independence can be brought about in various ways. For example, independence is to provide a power switch between the power supply voltage input and the components by providing a separate power supply voltage input from the external PMU to control the power switch for a given domain as a unit. And / or by the combination of the above. There may also be more power domains than illustrated in Figure 1. For example, the CPU complex 14 may, in certain embodiments, have an independent power domain (each CPU processor 30 may also have an independent power domain). In certain embodiments, one or more peripheral components 18A-18B may be in one or more independent power domains.

In general, components can be referred to as powered on or powered off. The components can be powered on when receiving a power supply voltage so that they can operate as designed. When the component is powered off, it is not receiving power voltage and is not operating. A component may also be referred to as being powered on when the power is turned on and also as being powered off when the power is turned off. Powering on a component can mean supplying a power supply voltage to a component that is turned off, and powering off a component can mean ending the supply of a power supply voltage to the component. Similarly, any subcomponent and / or the entire SOC10 can be referred to as powered on / off, and so on. A component can be a predetermined block of circuit that provides a specified function within SOC10 and has a particular interface to the rest of SOC10. Therefore, the always-on component 16, peripheral devices 18A to 18B, and the CPU complex 14, memory controller 22, and PMGR32 can be examples of components, respectively.

A component can be active if it is powered on and not clock gated. So, for example, the processor in CPU complex 14 may be available for instruction execution when active. A component can be inactive if it is powered off or in another low power state where significant delays can be experienced before an instruction can be executed. For example, a component can be inactive, even while powered, if it requires a phase-locked loop (PLL) reset or relock. The component can also be inactive if it is clock gated. Clock gate means a technique that temporarily "turns off" the clock to the digital circuits in the component and prevents the state from being captured from the digital circuits in the clock-controlled storage device such as flops and registers. Can be.

As mentioned above, the CPU complex 14 can include one or more processors 30 that can function as the CPU (s) of the CPU complex 14 in the SOC 10. The CPU of a system includes a processor (s) that runs the system's main control software, such as an operating system. In general, software executed by the CPU during use can control other components of the system to achieve the desired functionality of the system. The processor can also execute other software such as application programs. The application program may provide user functionality and may depend on the operating system for low-level device control, scheduling, memory management, and so on. Therefore, the processor can also be referred to as an application processor. The CPU complex 14 may further include other hardware such as an interface to the L2 cache and / or other components of the system (eg, an interface to the communication fabric 27).

The operating point can mean a combination of the magnitude of the power supply voltage and the operating frequencies of the CPU complex 14, the always-on component 16, the other components of the SOC 10. The operating frequency can be the frequency of the clock that controls the clock of the component. The operating frequency may also be referred to as the clock frequency or simply the frequency. The operating point may also be referred to as an operating state or a power state. The operating point can be part of programmable configuration data that is stored in the always-on component 16 and can be reprogrammed into the component when a reconfiguration occurs.

In general, a processor may include any circuit and / or microcode configured to execute instructions defined within the instruction set architecture implemented by the processor. The processor may include a processor core implemented as a system-on-chip (SOC 10) or other integrated level along with other components on an integrated circuit. Processors may further include separate microprocessors, processor cores and / or microprocessors integrated within a multi-chip module implementation, processors implemented as multiple integrated circuits, and the like.

The memory controller 22 may generally include circuits for receiving memory operations from other components of SOC 10 and accessing memory 12 to complete the memory operations. The memory controller 22 can be configured to access any form of memory 12. For example, memory 12 is a dynamic RAM such as static random access memory (SRAM), synchronous DRAM (SDRAM) including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. It can be (dynamic RAM) (DRAM). DDR Low power / mobile versions of DRAM (eg LPDDR, mDDR, etc.) may be supported. The memory controller 22 may include a queue for memory operations for ordering (and optionally reordering) the operations and presenting the operations to memory 12. The memory controller 22 may further include a data buffer for storing write data waiting to be written to the memory and read data waiting to be returned to the source of the memory operation. In some embodiments, the memory controller 22 may include a memory cache for storing recently accessed memory data. In the SOC implementation, for example, the memory cache can reduce the power consumption in the SOC by avoiding re-access of the data from the memory 12 if the data is expected to be accessed again soon. In some cases, memory caches can also be referred to as system caches, unlike private caches that serve only certain components, such as L2 caches or caches within a processor. In addition, in some embodiments, the system cache does not need to be located within the memory controller 22.

Peripherals 18A-18B can be any set of additional hardware features contained within SOC10. For example, peripheral devices 18A-18B display video data on a video peripheral, such as an image signal processor, configured to process image capture data from a camera or other image sensor, or one or more display devices. It may include display controllers, graphics processing units (GPUs), video encoders / decoders, scalers, rotators, blenders, etc. configured in. Peripherals may include microphones, speakers, interfaces to microphones and speakers, audio peripherals such as audio processors, digital signal processors, mixers and the like. Peripherals are peripheral components, including Universal Serial Bus (USB) and PCI Express (PCIe). It may include interface controllers for various interfaces outside the SOC10 (eg, peripheral device 18B), including interfaces such as interconnect) (PCI), serial and parallel ports. Peripherals may include network peripherals such as media access controllers (MACs). Any set of hardware may be included.

The communication fabric 27 can be any communication interconnect and communication protocol for communicating between the components of SOC10. The communication fabric 27 can be bus-based, including shared bus configurations, crossbar configurations, and layered buses with bridges. The communication fabric 27 can also be packet-based, a hierarchical structure with bridges, a crossbar, point-to-point, or other interconnect.

The PMGR32 may be configured to control the magnitude of the supply voltage required by the external PMU. There may be multiple supply voltages generated for SOC 10 by an external PMU. For example, even if there is a power supply voltage for the CPU complex 14, a power supply voltage for the rest of the SOC, a power supply voltage for the memory 12, and so on. The PMGR32 may be under direct software control (eg, the software may directly request powering up and / or powering off of the components) and / or monitoring SOC10 for various components. May be configured to determine when the power should be turned on or off.

Note that the number of components of SOC10 (and the number of subcomponents for what is shown in FIG. 1, such as in CPU complex 14) can vary from embodiment to embodiment. The number of each component / subcomponent may be greater or less than that shown in FIG.

FIG. 2 is a block diagram of an embodiment of the local time base circuit 26A. The same can be applied to other local time base circuits 26B to 26D. In the embodiment of FIG. 2, the local timebase circuit 26A includes a control circuit 40, the next synchronization value register 42, a local timebase register 44, and an increment register 46. The control circuit 40 is coupled from the global timebase circuit 20 to the Fr_clk input and the global timebase interface, and further coupled to the next synchronization value register 42, the local timebase register 44, and the increment register 46.

The control circuit 40 can be configured to increment the local time-based register 44 according to saturation at the next time-based synchronization value ("next synchronization value") in register 42, depending on Fr_clk. For example, an increment can be applied for each rising edge of Fr_clk. As mentioned above, in an exemplary embodiment, the magnitude of the increment can depend on the ratio of the Fr_clk frequency to the Rt_clk frequency. The magnitude of the increment may be programmed in the increment register 46, for example. The control circuit 40 can add an increment to the current local timebase and write the result (saturated at the next synchronization value) to the local timebase register 44.

In one embodiment, the next synchronization value may be transmitted to the local timebase circuit 26A via the global timebase interface during the period between synchronization events. In the above example, a synchronization event occurs at the rising edge of Rt_clk and the next sync value is sent at the falling edge of Rt_clk. More specifically, the global time-based interface may be a serial interface operating at the Fr_clk frequency, in one embodiment transmitting the next sync value over multiple clock cycles of Fr_clk starting at the falling edge of Rt_clk. You may. The control circuit 40 can be configured to operate the next synchronization value register 42 as a shift register when the next synchronization value is provided, and after shifting to the next synchronization value register 42, the next synchronization value. Can be configured to indicate that is valid. The control circuit 40 may be configured to invalidate the next synchronization value in response to a synchronization event until the updated value is transmitted. In other embodiments, the values can be transmitted as a parallel bus or using other mechanisms.

In other embodiments, the local timebase circuit 26A may receive the difference between the sync values from the global timebase circuit 20 and by adding the difference to the previous value, the next sync value locally. May be configured to generate.

Next, moving to FIG. 3, a block diagram of an embodiment of the global time base circuit 20 is shown. In the embodiment of FIG. 3, the global timebase circuit 20 includes a control circuit 50, the next synchronization value register 52, a global timebase register 54, an increment register 56, and a synchronization increment register 58. The control circuit 50 is coupled to the Rt_clk input, the Fr_clk input, and the global timebase interface to the local timebase circuits 26A-26D. The control circuit 50 is further coupled to the following synchronization value register 52, global timebase register 54, increment register 56, and synchronization increment register 58.

Similar to the discussion above for local timebase circuit 26A, control circuit 50 now increments global timebase register 54 according to saturation at the next timebase synchronization value ("next synchronization value") in register 52. Can be configured. The magnitude of the increment may be programmed in the increment register 56, for example. The control circuit 50 can add an increment to the current global timebase and write the result (saturated at the next synchronization value) to the global timebase register 54. In other embodiments, the global timebase register 54 may not be provided. For example, if all components accessing the timebase have access to the local timebase circuits 26A-26D, the global timebase register 54 may not be needed. Alternatively, the global timebase circuit 20 can be responsible for local timebase synchronization depending on Rt_clk.

In one embodiment, the control circuit 50 responds to a synchronization event by adding the synchronization increment from register 58 to the current contents of the next synchronization value register 52 and writing the result to the next synchronization value register 52. The following synchronization values may be generated. The synchronous increment may be programmed in the synchronous increment register 58 or may depend on the frequency ratio of Fr_clk to Rt_clk. The control circuit 50 shall be configured to transmit the next synchronization value to the local timebase circuits 26A-26D via the global timebase interface during the period between synchronization events, as described above for the local timebase circuit 26A. Can be done.

FIG. 4 is a timing diagram showing the operation of one embodiment of the local time base circuits 26A to 26D and the global time base circuit 20. Figure 4 shows Rt_clk as well as Fr_clk (although it is not an exact scale for large frequency ratios with respect to Fr_clk). sync_time can be the next sync value in the next sync value register 56 in the global timebase circuit 50. This allows sync_time to change to the next sync value at the current rising Rt_clk edge (valid for subsequent rising Rt_clk edges). This causes sync_time to change from N to N + M (where M is the synchronous increment in the synchronous increment register 58) during the first period of Rt_clk in Figure 4, and N + during the second period. It changes to 2M and N + 3M in the third period. The global timebase circuit 20 can send sync_time to the local timebase circuits 26A-26D according to the falling edge of Rt_clk, and therefore the following synchronization values shown in FIG. 4 (local timebase circuits 26A-26D). The next sync value in register 42 of) can be updated approximately in the middle of the Rt_clk period.

Global and local timebase values are also shown for each period. At the beginning of the first period illustrated (dotted line 60), both timebases are synchronized to N. In the first clock period, Fr_clk may be delayed, so at the end of this period (dotted line 62), the timebase is below the next sync value (eg, relative to the global timebase). N + Mx, and N + My for local timebase). The global and local timebases may differ due to different clock sources for Fr_clk, or other variations of Fr_clk (eg, due to an unbalanced clock tree for Fr_clk or other local variations). In other cases, x and y may be equal.

Global timebase circuits 20 and local timebase circuits 26A-26D load the next synchronization value in response to a synchronization event (before updating the next synchronization value for the next period), and therefore global timebase and local. Both of the timebases may be transitioned to N + M at the beginning of the second period. In the second period, Fr_clk may run faster than expected, which causes the global and local timebases to saturate at N + 2M at the end of the second period (eg, dotted line 64). You may.

It should be noted that the timing diagram of FIG. 4 is merely exemplary to show both saturation and load of synchronization values. In practice, adjacent periods may often have the same behavior (eg, saturation or load), and switching to opposite synchronization is infrequent.

FIG. 5 is a flowchart showing the operation of one embodiment of the local time base circuits 26A to 26D (more specifically, in the embodiment of FIG. 2, the control circuit 40). The blocks are shown in a particular order for ease of understanding, but other orders may be used. The block is a combination logic circuit in the control circuit 40 and may be executed in parallel. Blocks, block combinations, and / or entire flowcharts can be pipelined over multiple clock periods. The control circuit 40 can be configured to perform the operation shown in FIG.

When the next synchronization value is received from the global time base circuit 20 ("Yes" branch of determination block 70), the control circuit 40 is configured to capture the next synchronization value in the next synchronization value register 42. May be (block 72). For example, as described above, the global timebase circuit 20 may transmit the next synchronization value as a serial bitstream at the Fr_clk clock rate. In such an embodiment, capturing the next synchronization value can include shifting to the next synchronization value register 42 with serial data. The next synchronization value can be invalid from the beginning of the synchronization period until data is populated in register 42.

Fr_clk The rising edge of the clock is detected ("Yes" branch of judgment block 74), and the next synchronization value is not valid ("No" branch of judgment block 76), or the next synchronization value is valid (judgment). If either the "yes" branch of block 76) and the local timebase value has not reached the next synchronization value (the "no" branch of decision block 78), the control circuit 40 is local to register 44. It can be configured to update the timebase (block 80). More specifically, in one embodiment, the update may be an increment of a value in register 44 by an increment value in register 46. On the other hand, the Fr_clk clock rising edge is detected ("Yes" branch of judgment block 74), the next synchronization value is valid ("Yes" branch of judgment block 76), and the local timebase value is the next synchronization. If the value has been reached (a "yes" branch of decision block 78), the control circuit 40 can be configured to saturate the local timebase of register 44 to the next synchronization value (block 82).

If the synchronization event is signaled by global timebase circuit 20 ("yes" branch of decision block 84), control circuit 40 localizes the next synchronization value if the local timebase is not already saturated. It can be configured to load on a timebase (block 86). Since the saturation is at the next synchronization value, the load can be performed independently of the contents of the local timebase at the time of the synchronization event. If the local timebase is saturated, it is already at the next sync value and therefore does not need to be loaded, but it can be loaded anyway.

FIG. 6 is a flowchart showing the operation of one embodiment of the global time base circuit 20 (more specifically, the control circuit 50 in the embodiment of FIG. 3). The blocks are shown in a particular order for ease of understanding, but other orders may be used. The blocks are combination logic circuits in control circuit 50 and may be executed in parallel. Blocks, block combinations, and / or entire flowcharts can be pipelined over multiple clock periods. The control circuit 50 can be configured to perform the operation shown in FIG.

Rt_clk If a falling edge is detected (a "yes" branch of decision block 90), the control circuit 50 should send the next sync value of the next sync value register 52 to the local timebase circuits 26A-26D. Can be configured (block 92). For example, as described above, the global timebase circuit 20 may transmit the next synchronization value as a serial bitstream at the clock speed of Fr_clk.

Fr_clk If a rising edge of the clock is detected (a "yes" branch in decision block 94) and the global timebase value has not reached the next sync value (a "no" branch in decision block 96), control circuit 50 Can be configured to update the global timebase of register 54 (block 98). More specifically, in one embodiment, the update may be an increment of value in register 54 by an increment value in register 56. On the other hand, if the rising edge of the Fr_clk clock is detected ("Yes" branch of judgment block 94) and the global timebase value reaches the next synchronization value ("Yes" branch of judgment block 96), control is performed. Circuit 50 can be configured to saturate the global timebase of register 54 to the next synchronization value (block 100).

If a rising edge of Rt_clk is detected (a "yes" branch of decision block 102), a synchronization event occurs. The control circuit 50 may be configured to load the next synchronization value into the global timebase if the global timebase is not already saturated (block 104). Saturation is at the next synchronization value, so the load can be performed independently of the contents of the global timebase at the time of the synchronization event. The control circuit 50 may be configured to signal synchronization events to local timebase circuits 26A-26D (block 106). In addition, the control circuit 50 can be configured to update the next synchronization value in register 52 by adding the current value to the synchronization increment from register 58 (block 108).

FIG. 7 is a flow chart showing global and local timebase initialization for one embodiment (more specifically, control circuits 40 and 50 for each of the embodiments of FIGS. 2 and 3). The blocks are shown in a particular order for ease of understanding, but other orders may be used. The blocks are combination logic circuits within control circuits 40 and 50 and may be executed in parallel. Blocks, block combinations, and / or entire flowcharts can be pipelined over multiple clock periods. The control circuits 40 and 50 can be configured to perform the operation shown in FIG.

The global timebase circuit 20 may be part of the always-on component 16, which may be reset based on the release of the reset to the always-on component 16. Specifically, the always-on component 16 may be reset when the SOC 10 is first powered after an uninterruptible period. In general, as long as the SOC10 is powered, the always-on component 16 is on and does not need to be reset, even if the rest of the SOC10 is powered off. When always-on component 16 is reset and the reset is released (a "yes" branch of decision block 110), control circuit 50 starts at 0 and updates the global timebase register 54 based on Fr_clk. May be (block 112). This update may be performed as described above for FIG.

If another component in SOC10 (other than the always-on component 16) has been reset and the reset is released (a "yes" branch of decision block 114), the corresponding local timebase circuit 26A-26D The control circuit 40 in the device can start fetching the next synchronization value in the next synchronization value register 42 for each transmission from the global time base circuit 20 (block 116). However, in embodiments where the next sync value is transmitted serially, a reset may be released during transmission and therefore the next sync value may not be captured correctly. Therefore, the control circuit 40 can wait to detect a second synchronization event after the reset is released (block 118), after which it loads the next synchronization value from the next synchronization register 42 into the local timebase register 44. May (block 120). The control circuit 40 may then start updating registers with the value of Fr_clk, as described for FIG. 5 (block 122).

Next, moving to FIG. 8, a block diagram of one embodiment of the system 150 is shown. In an exemplary embodiment, system 150 includes at least one instance of SOC10 coupled to one or more peripherals 154 and external memory 12. A power management unit (PMU) 156 is presented that supplies a power supply voltage to the SOC 10 and one or more power supply voltages to the memory 12 and / or the peripheral device 154. In some embodiments, two or more instances of SOC10 may be included (and two or more memories 12 may also be included).

The PMU156 generally generates supply voltages and provides those supply voltages to other components of the system such as various off-chip peripheral components 154 such as SOC10, memory 12, display devices, image sensors, user interface devices, etc. It may include a circuit for doing so. The PMU156 may thus include a programmable voltage regulator, logic to interface to the SOC10 to receive voltage requirements, and more specifically to the SOC's PMGR16.

Peripheral device 154 may include any desired circuit depending on the type of system 150. For example, in one embodiment, system 150 can be a mobile device (eg, personal digital assistant (PDA), smartphone, etc.) and peripheral device 154 can be WiFi, Bluetooth®, cellular, etc. It may include devices for various wireless communications such as Global Positioning System. Peripheral device 154 may also include RAM storage, solid state storage, or additional storage including disk storage. Peripheral devices 154 may include display screens, including touch display screens or multi-touch display screens, keyboards or other input devices, and user interface devices such as microphones, speakers. In other embodiments, the system 150 can be any type of computing system (eg, desktop personal computer, laptop computer, workstation, nettop, etc.).

As the external memory 12, any kind of memory can be mentioned. For example, the external memory 12 is a dynamic RAM (eg LPDDR, mDDR, etc.) such as SRAM, Synchronous DRAM (SDRAM), Double Data Rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM, DDR DRAM low power version (eg LPDDR, mDDR, etc.). It can be DRAM). The external memory 12 may include one or more memory modules fitted with memory devices such as single inline memory modules (SIMM), dual inline memory modules (DIMM). Alternatively, the external memory 12 may include one or more memory devices mounted on the SOC 10 in a chip-on-chip or package-on-package implementation.

Many modifications and modifications will be apparent to those skilled in the art if the above disclosures are fully understood. The following "claims" are intended to be construed to include all such modifications and amendments.